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2020 – today
- 2024
[j51]Yuechen Chen
, Ahmed Louri, Shanshan Liu, Fabrizio Lombardi:
A Balanced Sparse Matrix Convolution Accelerator for Efficient CNN Training. IEEE Trans. Circuits Syst. I Regul. Pap. 71(10): 4638-4651 (2024)- [j50]Yuan Li, Ahmed Louri, Avinash Karanth:
A High-Performance and Energy-Efficient Photonic Architecture for Multi-DNN Acceleration. IEEE Trans. Parallel Distributed Syst. 35(1): 46-58 (2024) - [j49]Jiaqi Yang, Hao Zheng, Ahmed Louri:
Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration. IEEE Trans. Parallel Distributed Syst. 35(2): 349-361 (2024) - [j48]Ke Wang, Hao Zheng, Jiajun Li, Ahmed Louri:
Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration. IEEE Trans. Sustain. Comput. 9(2): 115-127 (2024) - [c78]Shilin Tian, Chase Szafranski, Ce Zheng, Fan Yao, Ahmed Louri, Chen Chen, Hao Zheng:
VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design. DAC 2024: 274:1-274:6 - [c77]Yingnan Zhao, Ke Wang, Jiaqi Yang, Ahmed Louri:
An Efficient Hardware Accelerator Design for Dynamic Graph Convolutional Network (DGCN) Inference. DAC 2024: 324:1-324:6 - [c76]Juliana Curry, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu:
PCM Enabled Low-Power Photonic Accelerator for Inference and Training on Edge Devices. IPDPS (Workshops) 2024: 600-607 - [c75]Jiaqi Yang, Hao Zheng, Ahmed Louri:
Aurora: A Versatile and Flexible Accelerator for Graph Neural Networks. IPDPS 2024: 890-902 - 2023
- [j47]Jiajun Li, Ke Wang, Hao Zheng, Ahmed Louri:
GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators. J. Comput. Sci. Technol. 38(1): 115-127 (2023) - [j46]Shanshan Liu, Pedro Reviriego, Anees Ullah, Ahmed Louri, Fabrizio Lombardi:
Error-Resilient Data Compression With Tunstall Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 1963-1975 (2023) - [j45]Yuechen Chen, Shanshan Liu, Fabrizio Lombardi, Ahmed Louri:
A Technique for Approximate Communication in Network-on-Chips for Image Classification. IEEE Trans. Emerg. Top. Comput. 11(1): 30-42 (2023) - [j44]Yuechen Chen, Ahmed Louri, Shanshan Liu, Fabrizio Lombardi:
Slack-Aware Packet Approximation for Energy-Efficient Network-on-Chips. IEEE Trans. Sustain. Comput. 8(1): 120-132 (2023) - [c74]Yuan Li, Ahmed Louri, Avinash Karanth:
A Silicon Photonic Multi-DNN Accelerator. PACT 2023: 238-249 - [c73]Jiaqi Yang, Hao Zheng, Ahmed Louri:
Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications. DAC 2023: 1-6 - [c72]Lingxiang Yin, Amir Ghazizadeh, Ahmed Louri, Hao Zheng:
ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible Interconnects. ICCAD 2023: 1-9 - [c71]Lingxiang Yin, Amir Ghazizadeh, Shilin Tian, Ahmed Louri, Hao Zheng:
Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration. ICCD 2023: 166-169 - [c70]Kyle Shiflett, Avinash Karanth, Razvan C. Bunescu, Ahmed Louri:
Flumen: Dynamic Processing in the Photonic Interconnect. ISCA 2023: 75:1-75:13 - 2022
- [j43]Yuan Li, Ke Wang, Hao Zheng, Ahmed Louri, Avinash Karanth:
Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2730-2741 (2022) - [j42]Xiaochen Tang, Shanshan Liu, Farzad Niknia, Pedro Reviriego, Ziheng Wang, Wei Tang, Ahmed Louri, Fabrizio Lombardi:
A Delta Sigma Modulator-Based Stochastic Divider. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3272-3283 (2022) - [j41]Hao Zheng, Ahmed Louri:
Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip Design. IEEE Trans. Emerg. Top. Comput. 10(1): 223-236 (2022) - [j40]Yuan Li, Ahmed Louri, Avinash Karanth:
SPRINT: A High-Performance, Energy-Efficient, and Scalable Chiplet-Based Accelerator With Photonic Interconnects for CNN Inference. IEEE Trans. Parallel Distributed Syst. 33(10): 2332-2345 (2022) - [j39]Jiajun Li, Hao Zheng, Ke Wang, Ahmed Louri:
SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With Workload Balancing. IEEE Trans. Parallel Distributed Syst. 33(11): 2834-2845 (2022) - [j38]Jiajun Li, Ahmed Louri:
AdaPrune: An Accelerator-Aware Pruning Technique for Sustainable CNN Accelerators. IEEE Trans. Sustain. Comput. 7(1): 47-60 (2022) - [j37]Ke Wang, Hao Zheng, Yuan Li, Ahmed Louri:
SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design. IEEE Trans. Sustain. Comput. 7(3): 709-723 (2022) - [c69]Ke Wang, Hao Zheng, Yuan Li, Jiajun Li, Ahmed Louri:
AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems. DATE 2022: 849-854 - [c68]Jiaqi Yang, Hao Zheng, Ahmed Louri:
Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation. ACM Great Lakes Symposium on VLSI 2022: 287-292 - [c67]Yuan Li, Ahmed Louri, Avinash Karanth:
SPACX: Silicon Photonics-based Scalable Chiplet Accelerator for DNN Inference. HPCA 2022: 831-845 - [c66]Yingnan Zhao, Ke Wang, Ahmed Louri:
FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture. ICCD 2022: 545-552 - [c65]Yuechen Chen, Ahmed Louri, Shanshan Liu, Fabrizio Lombardi:
Approximate Network-on-Chips with Application to Image Classification. NAS 2022: 1-8 - 2021
- [j36]Shanshan Liu, Xiaochen Tang, Farzad Niknia, Pedro Reviriego, Weiqiang Liu, Ahmed Louri, Fabrizio Lombardi:
Stochastic Dividers for Low Latency Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4102-4115 (2021) - [j35]Shanshan Liu, Ke Chen, Pedro Reviriego, Weiqiang Liu, Ahmed Louri, Fabrizio Lombardi:
Reduced Precision Redundancy for Reliable Processing of Data. IEEE Trans. Emerg. Top. Comput. 9(4): 1960-1971 (2021) - [j34]Yuan Li, Ahmed Louri:
ALPHA: A Learning-Enabled High-Performance Network-on-Chip Router Design for Heterogeneous Manycore Architectures. IEEE Trans. Sustain. Comput. 6(2): 274-288 (2021) - [c64]Yuan Li, Ahmed Louri, Avinash Karanth:
Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects. DAC 2021: 931-936 - [c63]Kyle Shiflett, Avinash Karanth, Ahmed Louri, Razvan C. Bunescu:
Bitwise Neural Network Acceleration Using Silicon Photonics. ACM Great Lakes Symposium on VLSI 2021: 9-14 - [c62]Jiajun Li, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu:
CSCNN: Algorithm-hardware Co-design for CNN Accelerators using Centrosymmetric Filters. HPCA 2021: 612-625 - [c61]Hao Zheng, Ke Wang, Ahmed Louri:
Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures. HPCA 2021: 723-735 - [c60]Jiajun Li, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu:
GCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional Neural Networks. HPCA 2021: 775-788 - [c59]Kyle Shiflett, Avinash Karanth, Razvan C. Bunescu, Ahmed Louri:
Albireo: Energy-Efficient Acceleration of Convolutional Neural Networks via Silicon Photonics. ISCA 2021: 860-873 - 2020
- [j33]Ke Wang, Hao Zheng, Ahmed Louri:
TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture. IEEE Micro 40(5): 56-63 (2020) - [j32]Ahmed Louri:
State of the Journal. IEEE Trans. Computers 69(4): 466-467 (2020) - [j31]Quintin Fettes, Avinash Karanth, Razvan C. Bunescu, Ahmed Louri, Kyle Shiflett:
Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3638-3649 (2020) - [j30]Yuechen Chen, Ahmed Louri:
Learning-Based Quality Management for Approximate Communication in Network-on-Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3724-3735 (2020) - [j29]Yuechen Chen, Ahmed Louri:
An Approximate Communication Framework for Network-on-Chips. IEEE Trans. Parallel Distributed Syst. 31(6): 1434-1446 (2020) - [j28]Ke Wang, Ahmed Louri:
CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning. IEEE Trans. Parallel Distributed Syst. 31(9): 2125-2138 (2020) - [c58]Hao Zheng, Ke Wang, Ahmed Louri:
A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures. DAC 2020: 1-6 - [c57]Kyle Shiflett, Dylan Wright, Avinash Karanth, Ahmed Louri:
PIXEL: Photonic Neural Network Accelerator. HPCA 2020: 474-487 - [c56]Talha Furkan Canan, Savas Kaya, Avinash Karanth, Ahmed Louri:
4-Input NAND and NOR Gates Based on Two Ambipolar Schottky Barrier FinFETs. ICECS 2020: 1-4 - [c55]Mark Clark, Yingping Chen, Avinash Karanth, Dongsheng Brian Ma, Ahmed Louri:
DozzNoC: Reducing Static and Dynamic Energy in NoCs with Low-latency Voltage Regulators using Machine Learning. IPDPS 2020: 1-11
2010 – 2019
- 2019
- [j27]Quintin Fettes, Mark Clark, Razvan C. Bunescu, Avinash Karanth, Ahmed Louri:
Dynamic Voltage and Frequency Scaling in NoCs With Supervised and Reinforcement Learning Techniques. Computer 52(9): 4-5 (2019) - [j26]Ahmed Louri, Jacques Henri Collet, Avinash Karanth:
Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs. ACM J. Emerg. Technol. Comput. Syst. 15(1): 4:1-4:16 (2019) - [j25]Dylan Machovec, Bhavesh Khemka, Nirmal Kumbhare, Sudeep Pasricha, Anthony A. Maciejewski, Howard Jay Siegel, Ali Akoglu, Gregory A. Koenig, Salim Hariri, Cihan Tunc, Michael Wright, Marcia Hilton, Rajendra Rambharos, Christopher Blandin, Farah Fargo, Ahmed Louri, Neena Imam:
Utility-based resource management in an oversubscribed energy-constrained heterogeneous environment executing parallel applications. Parallel Comput. 83: 48-72 (2019) - [j24]Ahmed Louri:
Editorial from the Incoming Editor-in-Chief. IEEE Trans. Computers 68(1): 3 (2019) - [j23]Quintin Fettes, Mark Clark, Razvan C. Bunescu, Avinash Karanth, Ahmed Louri:
Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques. IEEE Trans. Computers 68(3): 375-389 (2019) - [j22]Avinash Karanth, Savas Kaya, Md. Ashif I. Sikder, Daniel Carbaugh, Soumyasanta Laha, Dominic DiTomaso, Ahmed Louri, Hao Xin, JunQiang Wu:
Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies. IEEE Trans. Sustain. Comput. 4(3): 293-307 (2019) - [c54]Hao Zheng, Ahmed Louri:
An Energy-Efficient Network-on-Chip Design using Reinforcement Learning. DAC 2019: 47 - [c53]Ke Wang, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu:
High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin. DATE 2019: 1166-1171 - [c52]Yuechen Chen, Ahmed Louri:
An online quality management framework for approximate communication in network-on-chips. ICS 2019: 217-226 - [c51]Ke Wang, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu:
IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores. ISCA 2019: 589-600 - 2018
- [j21]Hao Zheng, Ahmed Louri:
EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs. IEEE Comput. Archit. Lett. 17(1): 88-91 (2018) - [c50]Mark Clark, Avinash Kodi, Razvan C. Bunescu, Ahmed Louri:
LEAD: learning-enabled energy-aware dynamic voltage/frequency scaling in NoCs. DAC 2018: 82:1-82:6 - [c49]Scott Van Winkle, Avinash Karanth Kodi, Razvan C. Bunescu, Ahmed Louri:
Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning. HPCA 2018: 480-491 - [c48]Yuechen Chen, Md Farhadur Reza, Ahmed Louri:
DEC-NoC: An Approximate Framework Based on Dynamic Error Control with Applications to Energy-Efficient NoCs. ICCD 2018: 480-487 - [c47]Talha Furkan Canan, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri:
10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETs. ICECS 2018: 577-580 - [c46]Avinash Kodi, Kyle Shifflet, Savas Kaya, Soumyasanta Laha, Ahmed Louri:
Scalable Power-Efficient Kilo-Core Photonic-Wireless NoC Architectures. IPDPS 2018: 1010-1019 - [c45]Yunus Kelestemur, Soumyasanta Laha, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri:
Sub-THz Tunable Push-Push Oscillators with FinFETs for Wireless NoCs. MWSCAS 2018: 332-335 - 2017
- [c44]Dominic DiTomaso, Md. Ashif I. Sikder, Avinash Karanth Kodi, Ahmed Louri:
Machine learning enabled power-aware Network-on-Chip design. DATE 2017: 1354-1359 - [c43]Talha Furkan Canan, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri:
Ultra-compact sub-10nm logic circuits based on ambipolar SB-FinFETs. MWSCAS 2017: 100-103 - 2016
- [j20]Wo-Tak Wu, Ahmed Louri:
A Methodology for Cognitive NoC Design. IEEE Comput. Archit. Lett. 15(1): 1-4 (2016) - [j19]Pavan Poluri, Ahmed Louri:
Shield: A Reliable Network-on-Chip Router Architecture for Chip Multiprocessors. IEEE Trans. Parallel Distributed Syst. 27(10): 3058-3070 (2016) - [c42]Dominic DiTomaso, Travis Boraten, Avinash Kodi, Ahmed Louri:
Dynamic error mitigation in NoCs using intelligent prediction techniques. MICRO 2016: 31:1-31:12 - [c41]Md. Ashif I. Sikder, Avinash Karanth Kodi, Ahmed Louri:
Reconfigurable Optical and Wireless (R-OWN) Network-on-Chip for High Performance Computing. NANOCOM 2016: 25:1-25:6 - [c40]Tzyy-Juin Kao, Ahmed Louri:
Design of high bandwidth photonic NoC architectures using optical multilevel signaling. NOCS 2016: 1-4 - 2015
- [j18]Pavan Poluri, Ahmed Louri:
A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems. IEEE Comput. Archit. Lett. 14(2): 107-110 (2015) - [j17]Dominic DiTomaso, Avinash Karanth Kodi, Ahmed Louri, Razvan C. Bunescu:
Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures. IEEE Trans. Computers 64(12): 3555-3568 (2015) - [c39]Md. Ashif I. Sikder, Avinash Karanth Kodi, Matthew Kennedy, Savas Kaya, Ahmed Louri:
OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures. Hot Interconnects 2015: 44-51 - 2014
- [j16]Jin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Roveda:
Workload assignment considering NBTI degradation in multicore systems. ACM J. Emerg. Technol. Comput. Syst. 10(1): 4:1-4:22 (2014) - [j15]Randy Morris, Avinash Karanth Kodi, Ahmed Louri, Ralph D. Whaley:
Three-Dimensional Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration. IEEE Trans. Computers 63(1): 243-255 (2014) - [c38]Dominic DiTomaso, Avinash Karanth Kodi, Ahmed Louri:
QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers. HPCA 2014: 320-331 - [c37]Pavan Poluri, Ahmed Louri:
An Improved Router Design for Reliable On-Chip Networks. IPDPS 2014: 283-292 - 2013
- [j14]Dominic DiTomaso, Randy Morris, Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri:
Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2141-2154 (2013) - [c36]Dominic DiTomaso, Randy Morris, Evan Jolley, Ashwini Sarathy, Ahmed Louri, Avinash Karanth Kodi:
Design of a Concentrated Torus Topology with Channel Buffers and Efficient Crossbars in NoCs. IPDPS Workshops 2013: 876-883 - [c35]Pavan Poluri, Ahmed Louri:
Tackling Permanent Faults in the Network-on-Chip Router Pipeline. SBAC-PAD 2013: 49-56 - [c34]Randy Morris, Avinash Karanth Kodi, Ahmed Louri:
Evaluating the scalability and performance of 3D stacked reconfigurable nanophotonic interconnects. SLIP 2013: 1 - 2012
- [c33]Randy Morris, Avinash Karanth Kodi, Ahmed Louri:
3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores. ICCD 2012: 413-418 - [c32]Randy Morris, Avinash Karanth Kodi, Ahmed Louri:
Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance. MICRO 2012: 282-293 - [c31]Dominic DiTomaso, Travis Boraten, Avinash Kodi, Ahmed Louri:
Evaluation of fault tolerant channel buffers for improving reliability in NoCs. MWSCAS 2012: 182-185 - 2011
- [j13]Ahmed Louri, Avinash Karanth Kodi:
Introduction to the special issue on Networks-on-Chip (NoC) of the Journal of Parallel and Distributed Computing (JPDC). J. Parallel Distributed Comput. 71(5): 623-624 (2011) - [c30]Avinash Karanth Kodi, Randy Morris, Dominic DiTomaso, Ashwini Sarathy, Ahmed Louri:
Co-design of channel buffers and crossbar organizations in NoCs architectures. ICCAD 2011: 219-226 - [c29]Jacques Henri Collet, Ahmed Louri, Vivek Tulsidas Bhat, Pavan Poluri:
ROBUST: a new self-healing fault-tolerant NoC router. NoCArc@MICRO 2011: 11-16 - 2010
- [j12]Ahmed Louri, Avinash Karanth Kodi:
Special Issue on Network-on-Chips (NoCs). J. Parallel Distributed Comput. 70(1): 69 (2010) - [c28]Jin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang:
Workload capacity considering NBTI degradation in multi-core systems. ASP-DAC 2010: 450-455 - [c27]Xiang Zhang, Ahmed Louri:
A multilayer nanophotonic interconnection network for on-chip many-core communications. DAC 2010: 156-161
2000 – 2009
- 2009
- [c26]Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri, Janet Meiling Wang:
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures. ASP-DAC 2009: 1-6 - [c25]Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang:
Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs). ISQED 2009: 826-832 - [c24]Jin Sun, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang:
NBTI aware workload balancing in multi-core systems. ISQED 2009: 833-838 - [c23]Avinash Karanth Kodi, Randy Morris, Ahmed Louri, Xiang Zhang:
On-Chip photonic interconnects for scalable multi-core architectures. NOCS 2009: 90 - 2008
- [j11]Avinash Karanth Kodi, Ahmed Louri:
Optisim: A System Simulation Methodology for Optically Interconnected HPC Systems. IEEE Micro 28(5): 22-36 (2008) - [j10]Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri:
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis. IEEE Trans. Computers 57(9): 1169-1181 (2008) - [c22]Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri:
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures. ISCA 2008: 241-250 - 2007
- [c21]Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri:
Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture. ANCS 2007: 47-56 - [c20]Chander Kochar, Avinash Karanth Kodi, Ahmed Louri:
Implementation of Dynamic Bandwidth Re-allocation in Optical Interconnects using Microring Resonators. Hot Interconnects 2007: 54-64 - [c19]Avinash Karanth Kodi, Ahmed Louri:
Power-Aware Bandwidth-Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems. IPDPS 2007: 1-10 - [c18]Avinash Karanth Kodi, Ahmed Louri:
Performance adaptive power-aware reconfigurable optical interconnects for high-performance computing (HPC) systems. SC 2007: 6 - 2006
- [c17]Avinash Karanth Kodi, Ahmed Louri:
A New Dynamic Bandwidth Re-Allocation Technique in Optically Interconnected High-Performance Computing Systems. Hot Interconnects 2006: 31-36 - 2005
- [j9]Avinash Karanth Kodi, Ahmed Louri:
Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors. IEEE Micro 25(1): 41-49 (2005) - 2004
- [j8]Ahmed Louri, Avinash Karanth Kodi:
An Optical Interconnection Network and a Modified Snooping Protocol for the Design of Large-Scale Symmetric Multiprocessors (SMPs). IEEE Trans. Parallel Distributed Syst. 15(12): 1093-1104 (2004) - [c16]Avinash Karanth Kodi, Ahmed Louri:
Design of a high-speed optical interconnect for scalable shared memory multiprocessors. Hot Interconnects 2004: 92-97 - [c15]Avinash Karanth Kodi, Ahmed Louri:
A Scalable Architecture for Distributed Shared Memory Multiprocessors Using Optical Interconnects. IPDPS 2004 - 2000
- [j7]Brian Webb, Ahmed Louri:
A Class of Highly Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) for Parallel Computing Systems. IEEE Trans. Parallel Distributed Syst. 11(5): 444-458 (2000) - [c14]Peng Yin Choo, Abram Detofsky, Ahmed Louri:
The Equivalency Processing Parallel Photonic Integrated Circuit (EP3IC), a Parallel Digital Equivalence Search Module. AIPR 2000: 64-70
1990 – 1999
- 1999
- [c13]Peng Yin Choo, Abram Detofsky, Ahmed Louri:
A Multi-Wavelength Optical Content-Addressable Parallel Processor (MW-OCAPP) for High-Speed Parallel Relational Database Processing: Architectural Concepts and Preliminary Experimental System. IPPS/SPDP Workshops 1999: 873-886 - 1998
- [j6]Ahmed Louri, Brent Weech, Costas Neocleous:
A Spanning Multichannel Linked Hypercube: A Gradually Scalable Optical Interconnection Network for Massively Parallel Computing. IEEE Trans. Parallel Distributed Syst. 9(5): 497-512 (1998) - [c12]Thomas S. Jones, Ahmed Louri:
Media Access Protocols For A Scalable Optical Interconnection Network. ICPP 1998: 304-312 - 1995
- [j5]Ahmed Louri, James A. Hatch Jr., Jongwhoa Na:
A constant-time parallel sorting algorithm and its optical implementation. IEEE Micro 15(3): 60-71 (1995) - 1994
- [j4]Ahmed Louri, Hongki Sung:
3D Optical Interconnects for High-Speed Interchip and Interboard Communications. Computer 27(10): 27-37 (1994) - [j3]Ahmed Louri, James A. Hatch Jr.:
An Optical Associative Parallel Processor for High-Speed Database Processing. Computer 27(11): 65-71 (1994) - 1993
- [j2]Bernard P. Zeigler, Ahmed Louri:
A Simulation Environment for Intelligent Machine Architectures. J. Parallel Distributed Comput. 18(1): 77-88 (1993) - [c11]Earl Hokens, Ahmed Louri:
Performance Considerations Relating to the Design of Interconnection Networks for Multiprocessing Systems. ICPP (1) 1993: 206-209 - 1992
- [c10]Ahmed Louri, Hongki Sung:
A Compiler Directed Cache Coherence Scheme with Fast and Parallel Explicit Invalidation. ICPP (1) 1992: 2-9 - [c9]Ahmed Louri, Jongwhoa Na:
Parallel electro-optical rule-based system for fast execution of expert systems. ISCA 1992: 427 - [c8]Ahmed Louri, Hongki Sung:
A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation. ISCA 1992: 428 - 1991
- [j1]Ahmed Louri:
Three-dimensional optical architecture and data-parallel algorithms for massively parallel computing. IEEE Micro 11(2): 24-27 (1991) - [c7]Sy-Yen Kuo, Ahmed Louri, Sheng-Chiech Liang:
Design and Evaluation of Fault-Tolerant Interleaved Memory Systems. ICPP (1) 1991: 188-195 - [c6]Ahmed Louri:
Design of an Optical Content-Addressable Parallel Processor with Applications to Fast Searching and Information Retrieval. IPPS 1991: 234-239 - [c5]Ahmed Louri:
An Optical Content-Adressable Parallel Processor for Fast Searching and Retrieving. PARLE (1) 1991: 338-354 - 1990
- [c4]Ahmed Louri:
A Symbolic Substitution Based Parallel Architecture and Algorithms for High-speed Parallel Processing. ACM Conference on Computer Science 1990: 173-179
1980 – 1989
- 1988
- [c3]Kai Hwang, Ahmed Louri:
Optical Arithmetic Using Signed-Digit Symbolic Substitution. ICPP (1) 1988: 55-64 - [c2]Ahmed Louri, Kai Hwang:
A Bit-Plane Architecture for Optical Computing with Two-Dimensional Symbolic Substitution. ISCA 1988: 18-27 - 1987
- [c1]Ahmed Louri, Kai Hwang:
A Parallel Architecture for Optical Computing. PP 1987: 414-418
Coauthor Index
[j50] [c76] [c74] [c70] [j43] [j40] [c67] [c64] [c63] [c62] [c60] [c59] [j31] [c57] [c56] [c55] [j27] [j26] [j23] [j22] [c53] [c51] [c50] [c49] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [j17] [c39] [j16] [j15] [c38] [j14] [c36] [c34] [c33] [c32] [c31] [j13] [c30] [j12] [c28] [c26] [c25] [c24] [c23] [j11] [j10] [c22] [c21] [c20] [c19] [c18] [c17] [j9] [j8] [c16] [c15]
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Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-11-13 23:51 CET by the dblp team
all metadata released as open data under CC0 1.0 license
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since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
