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ORCID35th ICCD 2017: Boston, MA, USA
- 2017 IEEE International Conference on Computer Design, ICCD 2017, Boston, MA, USA, November 5-8, 2017. IEEE Computer Society 2017, ISBN 978-1-5386-2254-4
Best Papers Session
- Benedikt Dietrich, Nadja Peters, Sangyoung Park
, Samarjit Chakraborty:
Estimating the Limits of CPU Power Management for Mobile Games. 1-8
Session 1A: Hardware Security I
- Huili Chen, Seetal Potluri, Farinaz Koushanfar:
BioChipWork: Reverse Engineering of Microfluidic Biochips. 9-16 - Sixing Lu, Roman Lysecky, Jerzy W. Rozenblit:
Subcomponent Timing-Based Detection of Malware in Embedded Systems. 17-24 - Jack Tang, Mohamed Ibrahim, Krishnendu Chakrabarty, Ramesh Karri:
Security Trade-Offs in Microfluidic Routing Fabrics. 25-32 - Mohammad Nasim Imtiaz Khan, Shivam Bhasin, Alex Yuan, Anupam Chattopadhyay, Swaroop Ghosh:
Side-Channel Attack on STTRAM Based Cache for Cryptographic Application. 33-40 - Abhishek Chakraborty, Yang Xie, Ankur Srivastava:
Template Attack Based Deobfuscation of Integrated Circuits. 41-44 - Yuntao Liu, Yang Xie, Ankur Srivastava:
Neural Trojans. 45-48
Session 1B: Read-Write Optimizations for Non-Volatile Memory
- Shengan Zheng, Hong Mei, Linpeng Huang, Yanyan Shen, Yanmin Zhu:
Adaptive Prefetching for Accelerating Read and Write in NVM-Based File Systems. 49-56 - Xiaoyi Zhang, Dan Feng, Yu Hua, Jianxi Chen:
A Cost-Efficient NVM-Based Journaling Scheme for File Systems. 57-64 - Tianyue Lu, Yuhang Liu, Haiyang Pan, Mingyu Chen:
TDV Cache: Organizing Off-Chip DRAM Cache of NVMM from a Fusion Perspective. 65-72 - Dennis Antony Varkey, Biswabandan Panda, Madhu Mutyam:
RCTP: Region Correlated Temporal Prefetcher. 73-80 - Tianming Yang, Haitao Wu, Ping Huang, Fei Zhang:
A Shingle-Aware Persistent Cache Management Scheme for DM-SMR Disks. 81-88
Session 2A: Stochastic, Approximate, and Unary Computing
- Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
Low-Power and High-Speed Approximate Multiplier Design with a Tree Compressor. 89-96 - Bingzhe Li, Yaobin Qin, Bo Yuan, David J. Lilja:
Neural Network Classifiers Using Stochastic Computing with a Hardware-Oriented Approximate Activation Function. 97-104 - Joonsang Yu, Kyounghoon Kim, Jongeun Lee, Kiyoung Choi:
Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks. 105-112 - Siyuan Xu, Benjamin Carrión Schäfer:
Approximate Reconfigurable Hardware Accelerator: Adapting the Micro-Architecture to Dynamic Workloads. 113-120 - Xiaoliang Chen, Ahmed M. Eltawil, Fadi J. Kurdahi:
Low Latency Approximate Adder for Highly Correlated Input Streams. 121-124 - M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan:
Power and Area Efficient Sorting Networks Using Unary Processing. 125-128
Session 2B: Energy-Efficiency through Heterogeneity
- Hossein Sayadi, Nisarg Patel, Avesta Sasan, Houman Homayoun:
Machine Learning-Based Approaches for Energy-Efficiency Prediction and Scheduling in Composite Cores Architectures. 129-136 - Samuel Steffl, Sherief Reda:
LACore: A Supercomputing-Like Linear Algebra Accelerator for SoC-Based Designs. 137-144 - Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Elliott Forbes, Randy Widialaksono, Zhenqian Zhang, Joshua Schabel, Sungkwan Ku, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon:
H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor. 145-152 - Ling Wang, Xiaohang Wang, Yadong Wang:
ABDTR: Approximation-Based Dynamic Traffic Regulation for Networks-on-Chip Systems. 153-160 - Diman Zad Tootaghaj, Farshid Farhat:
CAGE: A Contention-Aware Game-Theoretic Model for Heterogeneous Resource Assignment. 161-164 - Suhaimi Abd Ishak, Hui Wu, Umair Ullah Tariq:
Energy-Aware Task Scheduling on Heterogeneous NoC-Based MPSoCs. 165-168
Session 3A: Debugging and Validation
- Xiaobang Liu, Ranga Vemuri:
Effective Signal Restoration in Post-Silicon Validation. 169-176 - Yuting Cao, Hao Zheng, Hernan M. Palombo, Sandip Ray, Jin Yang:
A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug. 177-184 - Alif Ahmed, Prabhat Mishra:
QUEBS: Qualifying Event Based Search in Concolic Testing for Validation of RTL Models. 185-192 - Farimah Farahmandi, Prabhat Mishra:
Automated Debugging of Arithmetic Circuits Using Incremental Gröbner Basis Reduction. 193-200
Session 3B: Graph Processing and NoC Architectures
- Hamza Omar, Masab Ahmad, Omer Khan:
GraphTuner: An Input Dependence Aware Loop Perforation Scheme for Efficient Execution of Approximated Graph Algorithms. 201-208 - Jing Chen, Xue Liu:
A High-Performance Deeply Pipelined Architecture for Elementary Transcendental Function Evaluation. 209-216 - Peitian Pan, Chao Li:
Congra: Towards Efficient Processing of Concurrent Graph Queries on Shared-Memory Machines. 217-224 - Yuya Maruyama, Shinpei Kato, Takuya Azumi:
Exploring Scalable Data Allocation and Parallel Computing on NoC-Based Embedded Many Cores. 225-228 - Mourad Dridi, Stéphane Rubini, Mounir Lallali, Martha Johanna Sepúlveda Flórez, Frank Singhoff, Jean-Philippe Diguet:
DAS: An Efficient NoC Router for Mixed-Criticality Real-Time Systems. 229-232
Session 4A: EDA with Focus on Multicore, FPGAs, and 3D
- Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
Monolithic 3D-Enabled High Performance and Energy Efficient Network-on-Chip. 233-240 - Yuanwen Huang, Prabhat Mishra:
Vulnerability-Aware Energy Optimization Using Reconfigurable Caches in Multicore Systems. 241-248 - Minghua Shen, Nong Xiao, Guojie Luo:
Dependency-Aware Parallel Routing for Large-Scale FPGAs. 249-256 - Ke Liu, Mengying Zhao, Lei Ju, Zhiping Jia, Chun Jason Xue, Jingtong Hu:
Design Exploration for Multiple Level Cell Based Non-Volatile FPGAs. 257-264 - Mihai Lefter, George Razvan Voicu, Thomas Marconi, Valentin Savin, Sorin Dan Cotofana:
LDPC-Based Adaptive Multi-Error Correction for 3D Memories. 265-268 - Tuck-Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng:
ILP-Based Identification of Redundant Logic Insertions for Opportunistic Yield Improvement during Early Process Learning. 269-272
Session 4B: Hardware Acceleration for Neural Networks
- Chi Lo, Yu-Yi Su, Chun-Yi Lee, Shih-Chieh Chang:
A Dynamic Deep Neural Network Design for Efficient Workload Allocation in Edge Computing. 273-280 - Chengning Wang, Dan Feng, Jingning Liu, Wei Tong, Bing Wu, Yang Zhang:
DAWS: Exploiting Crossbar Characteristics for Improving Write Performance of High Density Resistive Memory. 281-288 - Ruizhe Cai, Ao Ren, Luhao Wang, Massoud Pedram, Yanzhi Wang:
Hardware Acceleration of Bayesian Neural Networks Using RAM Based Linear Feedback Gaussian Random Number Generators. 289-296 - Nick Iliev, Amit Ranjan Trivedi:
Low Power Spatial Localization of Mobile Sensors with Recurrent Neural Network. 297-300 - Abbas A. Fairouz, Sunil P. Khatri:
An FPGA-Based Coprocessor for Hash Unit Acceleration. 301-304
Session 5A: Hardware Security II
- Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang:
Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack. 305-312 - Farimah Farahmandi, Prabhat Mishra:
FSM Anomaly Detection Using Formal Analysis. 313-320 - Chenguang Wang, Yici Cai, Qiang Zhou:
Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans. 321-328 - Ahmed Waheed Khan, Tanya Wanchoo, Gokhan Mumcu, Selçuk Köse:
Implications of Distributed On-Chip Power Delivery on EM Side-Channel Attacks. 329-336 - Vinayaka Jyothi, Ashik Poojari, Richard Stern, Ramesh Karri:
Fingerprinting Field Programmable Gate Arrays. 337-340 - Qutaiba Alasad, Jiann-Shiun Yuan:
Logic Obfuscation against IC Reverse Engineering Attacks Using PLGs. 341-344
Session 5B: Memory and Cache Optimizations
- Newton, Sujit Kr Mahto, Suhit Pai, Virendra Singh:
DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching. 345-352 - Akshay Lahiry, David R. Kaeli:
Dual Dictionary Compression for the Last Level Cache. 353-360 - Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Derek R. Hower, Daniel J. Sorin:
Jenga: Efficient Fault Tolerance for Stacked DRAM. 361-368 - Jiajun Wang, Reena Panda, Lizy Kurian John:
SelSMaP: A Selective Stride Masking Prefetching Scheme. 369-372 - Sushant Kondguli, Michael C. Huang:
T2: A Highly Accurate and Energy Efficient Stride Prefetcher. 373-376
Session 6A: Verification and Fault Tolerance
- Mehran Goli, Jannis Stoppe, Rolf Drechsler:
Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata. 377-384 - Kimia Soleimani, Ahmad Patooghy, Nasim Soltani, Lake Bu, Michel A. Kinsy:
Crosstalk Free Coding Systems to Protect NoC Channels against Crosstalk Faults. 385-390 - Abhishek Das, Nur A. Touba:
Limited Magnitude Error Correction Using OLS Codes for Memories with Multilevel Cells. 391-394 - Jiangwei Zhang, Donald Kline Jr., Liang Fang, Rami G. Melhem, Alex K. Jones:
Yoda: Judge Me by My Size, Do You? 395-398 - Sonal Pinto, Michael S. Hsiao:
Fast Search-Based RTL Test Generation Using Control-Flow Path Guidance. 399-402
Session 6B: Lithography and Patterning
- Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, David Z. Pan:
DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node. 403-410 - Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay:
Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography. 411-414 - Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-Han Kim, Praveen Raghavan, David Z. Pan:
Patterning Aware Design Optimization of Selective Etching in N5 and Beyond. 415-418
Special Session 1: On How to Design and Manage Complex Heterogeneous Distributed Computing Systems
- Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser:
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. 419-422 - Lorenzo Di Tucci, Marco Rabozzi, Luca Stornaiuolo, Marco D. Santambrogio:
The Role of CAD Frameworks in Heterogeneous FPGA-Based Cloud Systems. 423-426 - Emanuele Del Sozzo, Riyadh Baghdadi, Saman P. Amarasinghe, Marco D. Santambrogio:
A Common Backend for Hardware Acceleration on FPGA. 427-430 - Alberto Scolari, Yunseong Lee, Markus Weimer, Matteo Interlandi:
Towards Accelerating Generic Machine Learning Prediction Pipelines. 431-434 - Nils Voss, Marco Bacis, Oskar Mencer, Georgi Gaydadjiev, Wayne Luk:
Convolutional Neural Networks on Dataflow Engines. 435-438
Session 7A: LCD with Focus on Emerging Technology
- Zhezhi He, Shaahin Angizi, Deliang Fan:
Exploring STT-MRAM Based In-Memory Computing Paradigm with Application of Image Edge Extraction. 439-446 - Julio Villalba-Moreno, Javier Hormigo:
Floating Point Square Root under HUB Format. 447-454 - Wen Wen, Youtao Zhang, Jun Yang:
Read Error Resilient MLC STT-MRAM Based Last Level Cache. 455-462 - Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi:
Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching. 463-468 - Aditya Dalakoti, Merritt Miller, Forrest Brewer:
Pulse Ring Oscillator Tuning via Pulse Dynamics. 469-472 - Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou:
DLL-Assisted Clock Synchronization Method for Multi-Die ICs. 473-476
Session 7B: Power-Performance Optimization of Multicore Architecture
- Christopher E. Giles, Mark A. Heinrich:
M2S-CGM: A Detailed Architectural Simulator for Coherent CPU-GPU Systems. 477-484 - Sudhanshu Shukla, Mainak Chaudhuri:
Sharing-Aware Efficient Private Caching in Many-Core Server Processors. 485-492 - Lei Mo, Angeliki Kritikakou, Olivier Sentieys:
Decomposed Task Mapping to Maximize QoS in Energy-Constrained Real-Time Multicores. 493-500 - Sabrina M. Neuman, Jason E. Miller, Daniel Sánchez, Srinivas Devadas:
Using Application-Level Thread Progress Information to Manage Power and Performance. 501-508 - Siyuan Xu, Benjamin Carrión Schäfer, Yidi Liu:
Configurable SoC In-Situ Hardware/Software Co-Design Design Space Exploration. 509-512 - Navid Farazmand, David R. Kaeli:
Quality of Service-Aware Dynamic Voltage and Frequency Scaling for Mobile 3D Graphics Applications. 513-516
Session 8A: Synthesis and Security
- Yue Yao, Shuyang Huang, Chen Wang, Yi Wu, Weikang Qian:
Approximate Disjoint Bi-Decomposition and Its Application to Approximate Logic Synthesis. 517-524 - Steven F. Hoover:
Timing-Abstract Circuit Design in Transaction-Level Verilog. 525-532 - Atieh Lotfi, Rajesh K. Gupta:
ReHLS: Resource-Aware Program Transformation Workflow for High-Level Synthesis. 533-536 - Samah Mohamed Saeed, Nithin Mahendran, Alwin Zulehner, Robert Wille, Ramesh Karri:
Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy Attacks. 537-540 - Pei Luo, Konstantinos Athanasiou, Liwei Zhang, Zhen Hang Jiang, Yunsi Fei, A. Adam Ding, Thomas Wahl:
Compiler-Assisted Threshold Implementation against Power Analysis Attacks. 541-544 - Vinayaka Jyothi, Prashanth Krishnamurthy, Farshad Khorrami, Ramesh Karri:
TAINT: Tool for Automated INsertion of Trojans. 545-548
Session 8B: Cloud and Storage Solutions
- Wonil Choi, Myoungsoo Jung, Mahmut T. Kandemir, Chita R. Das:
A Scale-Out Enterprise Storage Architecture. 549-556 - Tianwei Zhang, Yuan Xu, Yungang Bao, Ruby B. Lee:
CloudShelter: Protecting Virtual Machines' Memory Resource Availability in Clouds. 557-564 - Yazhi Feng, Dan Feng, Wei Tong, Yu Jiang, Chuanqi Liu:
Using Disturbance Compensation and Data Clustering (DC)2 to Improve Reliability and Performance of 3D MLC Flash Memory. 565-572 - Jie Xu, Dan Feng, Yu Hua, Wei Tong, Jingning Liu, Chunyan Li, Wen Zhou:
Improving Performance of TLC RRAM with Compression-Ratio-Aware Data Encoding. 573-580 - Jie Xu, Dan Feng, Wei Tong, Jingning Liu, Wen Zhou:
Encoding Separately: An Energy-Efficient Write Scheme for MLC STT-RAM. 581-584 - Mingzhe Zhang, Lunkai Zhang, Lei Jiang, Frederic T. Chong, Zhiyong Liu:
Quick-and-Dirty: Improving Performance of MLC PCM by Using Temporary Short Writes. 585-588
Special Session 2: Effective Voltage Scaling in Late CMOS Era
- Sreela Kodali, Patrick Hansen, Niamh Mulholland, Paul N. Whatmough, David M. Brooks, Gu-Yeon Wei:
Applications of Deep Neural Networks for Ultra Low Power IoT. 589-592 - Eric Cheng, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith A. Campbell, Deming Chen, Chen-Yong Cher, Hyungmin Cho, Binh Q. Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron, Mircea Stan, Lukasz G. Szafaryn, Christos Vezyrtzis, Subhasish Mitra:
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights. 593-596 - Alec Roelke, Runjie Zhang, Kaushik Mazumdar, Ke Wang, Kevin Skadron, Mircea R. Stan:
Pre-RTL Voltage and Power Optimization for Low-Cost, Thermally Challenged Multicore Chips. 597-600 - Ramon Bertran, Pradip Bose, David M. Brooks, Jeff Burns, Alper Buyuktosunoglu, Nandhini Chandramoorthy, Eric Cheng, Martin Cochet, Schuyler Eldridge, Daniel Friedman, Hans M. Jacobson, Rajiv V. Joshi, Subhasish Mitra, Robert K. Montoye, Arun Paidimarri, Pritish Parida, Kevin Skadron, Mircea Stan, Karthik Swaminathan, Augusto Vega, Swagath Venkataramani, Christos Vezyrtzis, Gu-Yeon Wei, John-David Wellman, Matthew M. Ziegler:
Very Low Voltage (VLV) Design. 601-604
Special Session 3: Spin-Computing: Lower the Barrier between Memory and Logic
- Yong Shim, Akhilesh Jaiswal, Kaushik Roy:
Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization. 605-608 - Deliang Fan, Shaahin Angizi:
Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM. 609-612 - Wang Kang, He Zhang, Peng Ouyang, Youguang Zhang, Weisheng Zhao:
Programmable Stateful In-Memory Computing Paradigm via a Single Resistive Device. 613-616
Session 9A: Architecture and Microarchitecture Optimizations
- Janibul Bashir, Smruti R. Sarangi:
NUPLet: A Photonic Based Multi-Chip NUCA Architecture. 617-624 - Armin Haj Aboutalebi, Lide Duan:
RAPS: Restore-Aware Policy Selection for STT-MRAM-Based Main Memory under Read Disturbance. 625-632 - Yuxi Liu, Xia Zhao, Zhibin Yu, Zhenlin Wang, Xiaolin Wang, Yingwei Luo, Lieven Eeckhout:
BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads. 633-640 - Alexandre Joannou, Jonathan Woodruff, Robert Kovacsics, Simon W. Moore, Alex Bradbury, Hongyan Xia, Robert N. M. Watson, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alfredo Mazzinghi, Alex Richardson, Stacey D. Son, A. Theodore Markettos:
Efficient Tagged Memory. 641-648 - Kramer Straube, Christopher Nitta, Raj Amirtharajah, Matthew K. Farrens, Venkatesh Akella:
Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing. 649-652 - Chaobing Zhou, Libo Huang, Tan Zhang, Yongwen Wang, Chengyi Zhang, Qiang Dou:
Effective Optimization of Branch Predictors through Lightweight Simulation. 653-656
Session 9B: Novel Architecture with 3D and Flash Memory
- Meng Zhang, Fei Wu, Yajuan Du, Chengmo Yang, Changsheng Xie, Jiguang Wan:
CooECC: A Cooperative Error Correction Scheme to Reduce LDPC Decoding Latency in NAND Flash. 657-664 - Andrew J. Douglass, Sunil P. Khatri:
Fast, Ring-Based Design of 3D Stacked DRAM. 665-672 - Nektarios Georgios Tsoutsos, Oleg Mazonka, Michail Maniatakos:
Memory-Bounded Randomness for Hardware-Constrained Encrypted Computation. 673-680 - Qiao Li, Liang Shi, Yejia Di, Yajuan Du, Chun Jason Xue, Edwin Hsing-Mean Sha:
Exploiting Process Variation for Read Performance Improvement on LDPC Based Flash Memory Storage Systems. 681-684 - Abhishek Koneru, Sukeshwar Kannan, Krishnendu Chakrabarty:
A Design-for-Test Solution for Monolithic 3D Integrated Circuits. 685-688
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