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2020 – today
- 2020
[j29]Chia-Hua Wu, Shi-Yu Huang
, Yung-Fa Chou, Ding-Ming Kwai:
Time-to-Digital Converter Compiler for On-Chip Instrumentation. IEEE Des. Test 37(4): 101-107 (2020)- [c54]Tsung-Fu Hsieh, Jin-Fu Li, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method. ITC-Asia 2020: 41-46
2010 – 2019
- 2018
- [c53]Kuan-Te Wu, Jin-Fu Li, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A channel-sharable built-in self-test scheme for multi-channel DRAMs. ASP-DAC 2018: 245-250 - 2017
- [c52]Wei-Hsun Liao, Chang-Tzu Lin, Sheng-Hsin Fang, Chien-Chia Huang, Hung-Ming Chen, Ding-Ming Kwai, Yung-Fa Chou:
Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization. ASP-DAC 2017: 549-553 - [c51]Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou:
DLL-Assisted Clock Synchronization Method for Multi-Die ICs. ICCD 2017: 473-476 - [c50]Tah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai, Zhe Wang, Wei Wu, Shigeki Tomishima, Patrick Stolt, Shih-Lien Lu:
23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. ISSCC 2017: 404-405 - [c49]Chia-Hua Wu, Shi-Yu Huang, Mason Chern, Yung-Fa Chou, Ding-Ming Kwai:
Resilient Cell-Based Architecture for Time-to-Digital Converter. ISVLSI 2017: 7-12 - [c48]Sheng-Hsin Fang, Chang-Tzu Lin, Wei-Hsun Liao, Chien-Chia Huang, Li-Chin Chen, Hung-Ming Chen, I-Hsuan Lee, Ding-Ming Kwai, Yung-Fa Chou:
On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC. ISVLSI 2017: 459-464 - [c47]Tsung-Fu Hsieh, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs. ITC-Asia 2017: 107-111 - 2016
- [c46]Tzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories. ATS 2016: 281-286 - [c45]Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. ITC 2016: 1-7 - 2015
- [j28]Che-Wei Chou, Jin-Fu Li, Yun-Chao Yu, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Hierarchical Test Integration Methodology for 3-D ICs. IEEE Des. Test 32(4): 59-70 (2015) - [c44]Hua-Cheng Fu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou:
Temperature-aware online testing of power-delivery TSVs. 3DIC 2015: TS10.3.1-TS10.3.6 - [c43]Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A hybrid built-in self-test scheme for DRAMs. VLSI-DAT 2015: 1-4 - [c42]Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu:
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. VLSIC 2015: 186- - 2014
- [j27]Cody Hao Yu, Chiao-Ling Lung, Yi-Lun Ho, Ruei-Siang Hsu, Ding-Ming Kwai, Shih-Chieh Chang:
Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(5): 763-773 (2014) - [j26]Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu:
DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1356-1369 (2014) - [j25]Yen-Lin Peng, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 207-219 (2014) - [c41]Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. ATS 2014: 1-6 - [c40]Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo:
Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs. ATS 2014: 143-148 - [c39]Chia-Chi Huang, Chang-Tzu Lin, Wei-Syun Liao, Chieh-Jui Lee, Hung-Ming Chen, Chia-Hsin Lee, Ding-Ming Kwai:
Improving power delivery network design by practical methodologies. ICCD 2014: 237-242 - [c38]Tsu-Wei Tseng, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai:
A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage. VLSI-DAT 2014: 1-4 - 2013
- [j24]Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai:
Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 737-747 (2013) - [j23]Ji-Wei Ker, Shi-Yu Huang, Chao-Wen Tzeng, Ding-Ming Kwai, Yung-Fa Chou:
Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(4): 908-917 (2013) - [j22]Yung-Fa Chou, Ding-Ming Kwai, Ming-Der Shieh, Cheng-Wen Wu:
Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9): 2343-2351 (2013) - [j21]Jhih-Wei You, Shi-Yu Huang, Yu-Hsiang Lin, Meng-Hsiu Tsai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 443-453 (2013) - [j20]Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting Cheng, Cheng-Wen Wu:
Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 465-474 (2013) - [c37]Chi-Wen Pan, Yu-Min Lee, Pei-Yu Huang, Chi-Ping Yang, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai:
I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs. ASP-DAC 2013: 151-156 - [c36]Pei-Wen Luo, Chun Zhang, Yung-Tai Chang, Liang-Chia Cheng, Hung-Hsie Lee, Bih-Lan Sheu, Yu-Shih Su, Ding-Ming Kwai, Yiyu Shi:
Benchmarking for research in power delivery networks of three-dimensional integrated circuits. ISPD 2013: 17-24 - [c35]Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
An FPGA-based test platform for analyzing data retention time distribution of DRAMs. VLSI-DAT 2013: 1-4 - [c34]Hsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai:
A case study: 3-D stacked memory system architecture exploration by ESL virtual platform. VLSI-DAT 2013: 1-4 - [c33]Chen-Hsiang Hsu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou:
Worst-case IR-drop monitoring with 1GHz sampling rate. VLSI-DAT 2013: 1-4 - [c32]Chang-Tzu Lin, Tsu-Wei Tseng, Yung-Fa Chou, Chia-Hsin Lee, Ding-Ming Kwai:
Enabling inter-die co-optimization in 3-D IC with TSVs. VLSI-DAT 2013: 1-4 - [c31]Jin-Fu Li, Cheng-Wen Wu, Masahiro Aoyagi, Meng-Fan Marvin Chang, Ding-Ming Kwai:
Special session 4C: Hot topic 3D-IC design and test. VTS 2013: 1 - [c30]Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. VTS 2013: 1-6 - 2012
- [j19]Xuan-Lun Huang, Jiun-Lang Huang, Hung-I Chen, Chang-Yu Chen, Tseng Kuo-Tsai, Ming-Feng Huang, Yung-Fa Chou, Ding-Ming Kwai:
An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration. J. Electron. Test. 28(5): 705-722 (2012) - [c29]Tao Wang, Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai, Yiyu Shi:
Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction. ASP-DAC 2012: 640-645 - [c28]Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai:
Small delay testing for TSVs in 3-D ICs. DAC 2012: 1031-1036 - [c27]Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A built-in self-test scheme for 3D RAMs. ITC 2012: 1-9 - [c26]Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu, Yu-Tsao Hsing, Li-Ming Denq, Tsung-Hsiang Lin:
3D-IC BISR for stacked memories using cross-die spares. VLSI-DAT 2012: 1-4 - [c25]Chang-Tzu Lin, Chia-Hsin Lee, Tsu-Wei Tseng, Ding-Ming Kwai, Yung-Fa Chou:
3-D centric technology and realization with TSV. VLSI-DAT 2012: 1-4 - [c24]Jiun-Lang Huang, X.-L. Huang, Yung-Fa Chou, Ding-Ming Kwai:
A SAR ADC missing-decision level detection and removal technique. VTS 2012: 31-36 - 2011
- [j18]Yung-Fa Chou, Ding-Ming Kwai, Cheng-Wen Wu:
Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1346-1356 (2011) - [c23]Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu:
A self-testing and calibration method for embedded successive approximation register ADC. ASP-DAC 2011: 713-718 - [c22]Chiao-Ling Lung, Yi-Lun Ho, Ding-Ming Kwai, Shih-Chieh Chang:
Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization. DATE 2011: 8-13 - [c21]Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai:
A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. ETS 2011: 39-44 - [c20]Ding-Ming Kwai, Ka-Yi Yeh:
Developing through-silicon stacking process using 3-D CMOS imager as a test vehicle. ISOCC 2011: 124-126 - [c19]Ding-Ming Kwai, Chang-Tzu Lin:
3D Stacked IC layout considering bond pad density and doubling for manufacturing yield improvement. ISQED 2011: 129-134 - [c18]Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. VTS 2011: 20-25 - 2010
- [c17]Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu:
CAD reference flow for 3D via-last integrated circuits. ASP-DAC 2010: 187-192 - [c16]Ding-Ming Kwai:
Homogeneous integration for 3D IC with TSV. ASP-DAC 2010: 546-547 - [c15]Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A Test Integration Methodology for 3D Integrated Circuits. Asian Test Symposium 2010: 377-382 - [c14]Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
Performance Characterization of TSV in 3D IC via Sensitivity Analysis. Asian Test Symposium 2010: 389-394 - [c13]Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu:
An error tolerance scheme for 3D CMOS imagers. DAC 2010: 917-922 - [c12]Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai:
On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding. VTS 2010: 263-268
2000 – 2009
- 2009
- [c11]Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai:
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification. Asian Test Symposium 2009: 450-455 - 2006
- [c10]Ding-Ming Kwai, Yung-Fa Chou, Meng-Fan Chang, Su-Meng Yang, Ding-Sheng Chen, Min-Chung Hsu, Yu-Zhen Liao, Shiao-Yi Lin, Yu-Ling Sung, Chia-Hsin Lee, Hsin-Kun Hsu:
FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment. MTDT 2006: 28-33 - [c9]Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, Chi-Hsien Chuang, Min-Chung Hsu, Yi-Chun Chen, Yu-Ling Sung, Hsien-Yu Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou:
SRAM Cell Current in Low Leakage Design. MTDT 2006: 65-70 - 2005
- [c8]Meng-Fan Chang, Kuei-Ann Wen, Ding-Ming Kwai:
Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique. MTDT 2005: 16-21 - [c7]Ching-Hua Hsiao, Ding-Ming Kwai:
Measurement and characterization of 6T SRAM cell current. MTDT 2005: 140-145 - 2004
- [j17]Behrooz Parhami, Ding-Ming Kwai:
Incomplete k-ary n-cube and its derivatives. J. Parallel Distributed Comput. 64(2): 183-190 (2004) - [j16]Behrooz Parhami, Ding-Ming Kwai:
Comparing four classes of torus-based parallel architectures: Networkparameters and communication performance. Math. Comput. Model. 40(7-8): 701-720 (2004) - [c6]Meng-Fan Chang, Kuei-Ann Wen, Ding-Ming Kwai:
Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory Designs. ISQED 2004: 297-302 - 2003
- [j15]Behrooz Parhami, Ding-Ming Kwai:
Parallel Architectures and Adaptation Algorithms for Programmable FIR Digital Filters With Fully Pipelined Data and Control Flows. J. Inf. Sci. Eng. 19(1): 59-74 (2003) - [j14]Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu, Ding-Ming Kwai:
Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems. IEEE Trans. Circuits Syst. II Express Briefs 50(9): 553-566 (2003) - 2001
- [j13]Behrooz Parhami, Ding-Ming Kwai:
A Unified Formulation of Honeycomb and Diamond Networks. IEEE Trans. Parallel Distributed Syst. 12(1): 74-80 (2001) - [j12]Ding-Ming Kwai, Behrooz Parhami:
Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization. J. VLSI Signal Process. 28(3): 235-243 (2001) - 2000
- [c5]Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou:
etection of SRAM cell stability by lowering array supply voltage. Asian Test Symposium 2000: 268-273 - [c4]Ding-Ming Kwai, Behrooz Parhami:
Characterization and Generalization of Honeycomb and Diamond Networks. PDPTA 2000
1990 – 1999
- 1999
- [j11]Behrooz Parhami, Ding-Ming Kwai:
Data-Driven Control Scheme for Linear Arrays: Application to a Stable Insertion Sorter. IEEE Trans. Parallel Distributed Syst. 10(1): 23-28 (1999) - [j10]Behrooz Parhami, Ding-Ming Kwai:
Periodically Regular Chordal Rings. IEEE Trans. Parallel Distributed Syst. 10(6): 658-672 (1999) - [j9]Behrooz Parhami, Ding-Ming Kwai:
Correction to 'Periodically Regular Chordal Rings'. IEEE Trans. Parallel Distributed Syst. 10(7): 767-768 (1999) - [j8]Ding-Ming Kwai, Behrooz Parhami:
Scalability of Programmable FIR Digital Filters. J. VLSI Signal Process. 21(1): 31-35 (1999) - 1998
- [j7]Ding-Ming Kwai, Behrooz Parhami:
Tight Bounds on the Diameter of Gaussian Cubes. Comput. J. 41(1): 52-56 (1998) - [j6]Ding-Ming Kwai, Behrooz Parhami:
Pruned Three-Dimensional Toroidal Networks. Inf. Process. Lett. 68(4): 179-183 (1998) - 1997
- [j5]Ding-Ming Kwai, Behrooz Parhami:
An on-line fault diagnosis scheme for linear processor arrays. Microprocess. Microsystems 20(7): 423-428 (1997) - [c3]Ding-Ming Kwai, Behrooz Parhami:
A Class of Fixed-Degree Cayley-Graph Interconnection Networks Derived by Pruning k-ary n-cubes. ICPP 1997: 92-95 - 1996
- [j4]Ding-Ming Kwai, Behrooz Parhami:
A Generalization of Hypercubic Networks Based on their Chordal Ring Structures. Parallel Process. Lett. 6(4): 469-477 (1996) - [j3]Ding-Ming Kwai, Behrooz Parhami:
FFT computation with linear processor arrays using a data-driven control scheme. J. VLSI Signal Process. 13(1): 57-66 (1996) - [c2]Ding-Ming Kwai, Behrooz Parhami:
Comparing the Performance Parameters of Two Network Structures for Scalable Massively Parallel Processors. MASCOTS 1996: 273-277 - [c1]Ding-Ming Kwai, Behrooz Parhami:
Periodically regular chordal rings: generality, scalability, and VLSI layout. SPDP 1996: 148-151 - 1992
- [j2]Chein-Wei Jen, Ding-Ming Kwai:
Data Flow Representation of Iterative Algorithms for Systolic Arrays. IEEE Trans. Computers 41(3): 351-355 (1992)
1980 – 1989
- 1989
- [j1]Chein-Wei Jen, Ding-Ming Kwai:
Multi-dimensional parallel computing structures for regular iterative algorithms. Integr. 8(3): 331-340 (1989)
Coauthor Index
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