Digital Integrated

Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic

The Wire
July 30, 2002
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 The Wire

transmitters receivers

schematics physical

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 Interconnect Impact on Chip

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 Wire Models

All-inclusive model Capacitance-only

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 Impact of Interconnect Parasitics
 Interconnect parasitics
 reduce reliability
 affect performance and power
consumption
 Classes of parasitics
 Capacitive
 Resistive
 Inductive

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Nature of Interconnect

Local Interconnect Pentium Pro (R)

Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II

Global Interconnect
(Log Scale)
No of nets

SGlobal = SDie
SLocal = STechnology

Source: Intel
10 100 1,000 10,000 100,000
Length (u)
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 INTERCONNECT

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Capacitance of Wire Interconnect
VDD VDD

M2
Cdb2 Cg4 M4
Cgd12
Vin Vout Vout2

Cdb1 Cw Cg3
M1 M3
Interconnect

Fanout
Vin Vout
Simplified
Model CL

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Capacitance: The Parallel Plate Model

Current flow

W Electrical-field lines

tdi Dielectric

Substrate

 di S 1
cint  WL SCwire  
t di S S L S L
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 Permittivity

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Fringing Capacitance

(a)

H W - H/2

(b)
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Fringing versus Parallel Plate

(from [Bakoglu89])
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Interwire Capacitance

fringing parallel

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Impact of Interwire Capacitance

(from [Bakoglu89])

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 Wiring Capacitances (0.25 m CMOS)

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 INTERCONNECT

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Wire Resistance

R= L
HW

L Sheet Resistance
H Ro

R1 R2
W

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Interconnect Resistance

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 Dealing with Resistance
 SelectiveTechnology Scaling
 Use Better Interconnect Materials
 reduce average wire-length
 e.g. copper, silicides
 More Interconnect Layers
 reduce average wire-length

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Polycide Gate MOSFET
Silicide

PolySilicon

SiO2

n+ n+
p

Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi

Conductivity: 8-10 times better than Poly

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 Sheet Resistance

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 Modern Interconnect

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 Example: Intel 0.25 micron Process

5 metal layers
Ti/Al - Cu/Ti/TiN
Polysilicon dielectric

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 INTERCONNECT

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 Interconnect
Modeling

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 The Lumped Model

Vo ut

cwi re
Driver

Rdriver
Vout

Vin
Clum pe d

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 The Lumped RC-Model
The Elmore Delay

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 The Ellmore Delay
RC Chain

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 Wire Model

Assume: Wire modeled by N equal-length segments

For large values of N:

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The Distributed RC-line

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 Step-response of RC wire as a
function of time and space
2.5

x= L/10
2

x = L/4
1.5
voltage (V)

x = L/2
1
x= L

0.5

0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
time (nsec)

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 RC-Models

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 Driving an RC-line
Rs
(r w,cw,L)
Vo ut

Vi n

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 Design Rules of Thumb
 rc delays should only be considered when tpRC
>> tpgate of the driving gate
Lcrit >>  tpgate/0.38rc
 rc delays should only be considered when the
rise (fall) time at the line input is smaller than
RC, the rise (fall) time of the line
trise < RC
 when not met, the change in the signal is slower
than the propagation delay of the wire

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