SIMPLE IMPLEMENTATION
SCHEME
SIMPLE IMPLEMENTATION
Simple implementation covers
Load word (lw), store word (sw),
Branch equal (beq),
Arithmetic-logical instructions
add, sub, AND, OR, and set on less than (slt)
ALU CONTROL
For load word and store word instructions
ALU is used to compute the memory address by addition
For R-type instructions
ALU perform one of the five actions
AND, OR, subtract, add, or set on less than
Depends on the value of 6‑bit function field in the instruction
For branch equal, the ALU must perform a subtraction
4‑bit ALU control input generated using a small control unit
Inputs of the control unit
Function field of the instruction
2‑bit control field (ALUOp)
ALU CONTROL (2)
ALUOp indicates the operation to be performed
add (00) for loads and stores,
subtract (01) for beq, or
Determined by the operation encoded in the funct field (10)
The output of the ALU control unit is a 4 ‑bit signal
Controls the ALU by generating one of the 4 ‑bit combinations
ALU control inputs based on the 2‑bit ALUOp control and the 6 ‑bit
function code
MULTIPLE LEVELS OF DECODING
The main control unit generates the ALUOp bits
ALUOp bits are used as input to the ALU control
ALU control generates the actual signals to control the ALU unit
Multiple levels of control can reduce the size of the main control
unit
Smaller control units potentially increase the speed of the
control unit
Such optimizations are important, since the speed of the control
unit is often critical to clock cycle time
THE TRUTH TABLE FOR THE 4 ALU
CONTROL BITS
Only the truth table entries for which the ALU control must have
a specific value are shown
Don’t-care term indicates that the output does not depend on the
value of the input corresponding to that column
MAIN CONTROL UNIT DESIGN
Instruction format
INSTRUCTION FORMAT (2)
(a) R-format instructions
Have an opcode of 0. Three register operands: rs, rt, and rd
Fields rs and rt are sources, and rd is the destination
ALU function is in funct field, decoded by ALU control design
Implement add, sub, AND, OR, and slt
The shamt field is used only for shifts
(b) I-format instructions
load (opcode = 3510) and store (opcode = 4310)
The register rs is the base register added to the 16‑bit address field
to form the memory address
For loads, rt is the destination register for the loaded value
For stores, rt is the source register whose value stored into memory
INSTRUCTION FORMAT (3)
(c) J-format
Instruction format for branch equal (opcode = 4)
The registers rs and rt source registers compared for equality
The 16‑bit address field is sign-extended, shifted, and added to the
PC+4 to compute the branch target address
Observations on instruction format
The op field (opcode), is always contained in bits 31:26 referred as
Op[5:0]
The two registers to be read are always specified by the rs and rt fields,
at positions 25:21 and 20:16
This is true for the R-type instructions, branch equal, and store
The base register for load and store instructions is always in bit
positions 25:21 (rs).
OBSERVATIONS ON INSTRUCTION FORMAT
CONT’D
The 16‑bit offset for branch equal, load, and store is always in
positions 15:0.
The destination register is in one of two places
For a load it is in bit positions 20:16 (rt)
For an R-type instruction it is in bit positions 15:11 (rd)
Need to add a multiplexor to select field of the instruction used
to indicate the register number to be written
Instruction labels and extra multiplexor (for the Write register
number input of the register file) added to the simple datapath
DATAPATH WITH ALL NECESSARY
MULTIPLEXORS AND ALL CONTROL
LINES IDENTIFIED
THE EFFECT OF EACH OF THE SEVEN
CONTROL SIGNALS
SETTING OF CONTROL SIGNAL
The control unit can set all control signals based solely on the
opcode field of the instruction
Except PCSrc control line
PCSrc control line should be asserted if the instruction is branch
on equal and the Zero output of the ALU, is asserted
To generate the PCSrc signal, we need to AND together a signal
from the control unit (Branch) with the Zero signal out of ALU
Nine control signals (seven single bit control lines and one 2-bit
ALUOp) can now be set on the basis of six input signals to the
control unit (opcode bits 31 to 26)
DATAPATH WITH CONTROL UNIT AND
CONTROL SIGNALS
CONTROL SIGNAL
R-type instruction writes a register (RegWrite = 1), but neither reads
nor writes data memory
When the Branch control signal is 0, the PC is unconditionally
replaced with PC + 4; otherwise, the PC is replaced by the branch
target if the Zero output of the ALU is also high
The ALUOp field for R‑type instructions is set to 10 to indicate that
the ALU control should be generated from the funct field
For lw and sw ALUSrc is set to perform the address calculation.
ALUOp fields are 00
CONTROL SIGNAL CONT’D
The MemRead and MemWrite are set to perform the memory access
RegDst and RegWrite are set for a load to cause the result to be stored
into the rt register
The branch instruction is similar to an R-format operation, since it
sends the rs and rt registers to the ALU
The ALUOp field for branch is set for a subtract (ALU control = 01),
which is used to test for equality
Notice that the MemtoReg field is irrelevant when the RegWrite signal
is 0:
since the register is not being written, the value of the data on the
register data write port is not used
Entry MemtoReg in the last two rows of the table is replaced with X
for don’t care
Don’t cares can also be added to RegDst when RegWrite is 0
