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• Create your directory in explorer
For Example D:\SiMS
• Open Max Plus II from the ICON in the Desktop.
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ALTERA Max + plus II Main Tool Window
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File ->Project->Name
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SELLECT YOUR DIRECTORIES :SIMS
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WRITE THE PROJECT NAME E.G.VLSI
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Your project VLSI is created in your specified directory(SiMS)
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FILE -> NEW:SELECT Text Editor FOR WRITING HDL CODE
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Select ‘Text Editor file’ Radio Button -> Ok
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WRITE code IN TEXT EDITOR
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SAVE THE FILE
File ->Save
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Note: Your Entity Name & file name should be same with extension
(*.vhd)
e.g. and_2. vhd 14
Reserved words will be highlighted after saving the file
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File ->Project ->Set Project To Current File
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NOTE:-During compilation the design will be compiled &
implemented to the default device:-MAX7000 in one execution
MAX+plus -> Compiler
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Design Flow Window
Click Start
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NOTE:-BY DEFAULT IT’S TIMING SIMULATION
Error MessageWindow 19
SIMULATION FOR THE
DESIGN
FUNCTION AND TIMING
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Select The waveform Editor for simulation
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SIMULATION :-DEFAULT TIMING
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Right Click Here & Select The Nodes From SNF
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CLICK ON THE LIST & TRANSFER THE DATA USING SYMBOL
SYMBOL List
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Ok
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NOTE:-SAVE THE FILE ONLY ONCE
File name will be Entity name by default
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Ok 27
We will apply the Stimulus value to the node from the menu bar
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We will apply predefined clock to node a
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MAX + plus -> Simulator
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CLICK ON START TIMING SIMULATION BY DEFAULT
Start 31
RESULT OF YOUR DESIGN
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FUNCTIONAL SUMULATION:GO TO COMPILER
WINDOW,CLICK ON PROCESSING SELECT THE FUNCTIONAL
EXTRACTOR BELOW
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COMPILE THE DESIGN AGAIN
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MAX + plus -> Simulator
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CLICK ON START& OPEN SCF :VERIFY THE DESIGN
Start 36
FOR OTHER FOMAT ,SELECT THE MENU AND COMPILE
AGAIN
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MAX + plus II Floorplan View Of Your Design in Selected
Editor Device
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FLOORPLAN VIEW
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PROGRAMMING TO THE TARGET DEVICE(UVLSI)
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SELLECT THE TARGET DEVICE
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Down Loading the DESIGN to the device
You need to connect
hardware board
MAX + plus II -> Programmer 52
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Follow the steps given in slides 4-9
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CHOOSE RADIO BUTTON ‘GRAPHICAL EDITOR FILE’
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DOUBLE CLICK ON THE PAGE
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ENTER THE SYMBOL/LOGIC
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WRITE THE SYMBOL NAME E.G. AND2 -> OK
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NOTE :BUFFERS(I/0) TO CONNECT TO ALL THE INPUT &
OUT PUT
AND gate symbol with 2 inputs
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COPY THE INPUT BUFFER & PASTE IT .DOUBLE CLICK FOR
SELLECTINGLOGIC
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Now we will join the pads with the ports
F3
Click F3 to select the line type.Drag from input
pads to the port of AND gate as shown 61
Completed Graphical view of AND gate
Note : No .of pads = no of Inputs + No. of
Outputs
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Save the Graphical Editor File.
File ->Save
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Give the file name e.g. and2.gdf 64
AND Gate view after saving with .gdf extension 65
Give Port name (a,b,c)by double clicking on the pad.
File -> save 66
Set the the project to current file
File -> Project -> Set Project to Current file 67
Compile the file.
Max+plus II -> Compiler 68
In the mid way of compilation of current file.
Click on Start 69
File has been compiled.
After compilation click -> OK 70
You have complied the design.If
you wanted to see the VHDL code
for the same .Then follow the steps
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Max+ plus II -> Compiler
Interface -> VHDL Netlist
Writer 72
VHDL Netlist Writer is Added
Click On Start 73
You will get the VHDL Netlist generated file
‘and2.vho’
Double Click on VHDL Netlist Writer (*.vho)
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