EEE440

Computer Architecture
Pipelined Processor Design Handling

Sidra Saleem
Outline of this Lecture
 Stalls due to data hazards
 Control to introduce stalls cycles
 Detecting data hazard conditions
 Data forwarding paths
 Data forwarding control
 Stalls with data forwarding
Pipelined Datapath
ID Ex Mem WB
0
0 IF
1
1
4 IF/D ID/Ex Ex/Mem Mem/WB
+
+

+
+
22
SS
rdad1

PC ad rdad2
rddata1

ALU
inst adrs rddata

ALU
rddata2 0
0 0
0
write
IM wrdata
1 1
wrdata RF 1 1
DM
X
S

0
0

1
1
 Pipelined Datapath and Control
0
0

1
1

Control
Control
4
+
+

+
+
22
SS
rdad1
rdad2
PC ad
rddata1

ALU
inst rddata

ALU
adrs 0
0
write
rddata2 0
0
IM wrdata 1
1
1
1
wrdata RF
DM
SX

control
control
0
0 ALU
ALU

1
1
Stalls due to data hazards
I: lw $t1,…
add $s1,$t1,
…
I IM RF DM RF

ALU
ALU
 I+1 IM IM IM RF RF

ALU
DM

ALU

I+1 IM RF RF RF RF

ALU
DM

ALU
Stalls due to data hazards
Stage Wise View
I: lw $t1,…
t IM RF add $s1,
DM RF

ALU
ALU
$t1,…

I I-1 I-2 I-3 I-4

IM RF DM RF

ALU
ALU
t+1

I+1 I nop1 I-2 I-3

t+2 IM RF DM RF
ALU
ALU

I+2 I+1 nop nop I-2

2 1
IM RF DM RF
ALU
ALU

t+3

I+3 I+2 I+1 nop2 nop1

Stalls due to data hazards
Instruction view again
I: lw $t1,…
add $s1,
$t1,…
I IM RF DM RF

ALU
ALU
nop1 RF

ALU
DM

ALU
RF

ALU
DM

ALU
nop2

I+1 IM RF RF RF RF

ALU
DM

ALU
IM IM IM RF

ALU
DM

ALU
I+2
 Control for data hazard Stalls
IF/ID
0
0

1
1 bubble

Control
0

Control
4 0 1
1
+
+

+
+
22
SS
rdad1
rdad2
PC ad
rddata1

ALU
inst rddata

ALU
adrs 0
0
write
rddata2 0
0
IM wrdata 1
1
1
1
PCw wrdata RF
DM
PCw =0 SX

control
control
IF/ID =0

ALU
ALU
Bubble =1
0
0

1
1
Detecting Data hazards
 Condition to be checked:
◦ Instruction in RF stage reads from a register in which
instruction in ALU stage or DM stage is going to write.
 ID/Ex.RW and
◦ (IF/D .rs=ID/EX.rd or IF/ID.rt=ID/EX.rd )
 EX/DM.RW and

◦ (IF/D.rs=EX/DM.rd
or
IF/ID.rt=EX/DM.rd)
◦ We need to ensure that instruction in RF actually reads
rs and/or rt (not taken care here)
 Note: rd is the RF designation after multiplexing
Data Forwarding path P1
I: add $t1,…
add $s1,
$t1,…
I IM RF DM RF

ALU
ALU
I+1 IM RF DM RF

ALU
ALU
Data Forwarding path P2
I: lw $t1,…
add $s1,
$t1,…
I IM RF DM RF

ALU
ALU
I+1 IM IM RF RF

ALU
DM

ALU
Data Forwarding path P3
I: add $t1,…
sw $t1,…
I IM RF DM RF

ALU
ALU
I+1 IM RF RF

ALU
DM

ALU
Data Forwarding path P4
I: add $t1,…
sw $t1,…
I IM RF DM RF

ALU
ALU
I+1 IM RF RF

ALU
DM

ALU
Data forwarding path List
 P1
◦ From ALU out (EX/DM) to ALU in 1/2
 P2
◦ From DM/ALU out (DM/WB) to ALU in 1/2
 P3/P4
◦ From DM/ALU out (DM/WB) to DM in
Actual Forwarding Path
Ex Mem WB
ID/Ex Ex/Mem Mem/WB

FwdA

0
0
1
1
2
2
ALU
ALU adrs rddata
0
0
0
0
1 0
0 0
0
1 wrdata
1
1 1
1 1
1
2
2 DM
FwdC

FwdB
Dataforwarding control –
P1/P2
 P1: from ALU out (EX/DM) to ALU in 1/2
 P2: from DM/ALU out (DM/WB) to ALU in 1/2

 fwdA = 1 if EX/DM.RW and EX/DM.rd≠0 and

EX/DM.rd = ID/EX.rs
 fwdA = 1 if DM/WB.RW and DM/WB.rd≠0 and

EX/DM.rd ≠ ID/EX.rs
DM/WB.rd = ID/EX.rs
 For fwdB replace rs with rt
Dataforwarding control –
P3/P4
 P3/P4: from DM/ALU out (DM/WB) to DM in

 fwdC = 1 if DM/WB.RW and DM/WB.rd≠0 and

DM/WB.rd = EX/DM.rt
Summary
 Data hazards and stalls seen in different
views.
 Control Signals for stalling instructions and

inserting nops.
 Checking hazards conditions.
 Three types of forwarding paths.
 Control for data forwarding.
 Inserting stalls with data forwarding.