FPGA Architecture Sulochana

Introduction to
FPGA Architectures
Vemu Sulochana
Project Engineer-II
C-DAC, Mohali
Lecture Outline
FPGA overview
Design Flow
Architecture Details
The Design Warriors Guide to FPGAs

vemus@cdac.in C-DAC, Mohali Devices, Tools, and Flows. ISBN 0750676043
Copyright 2004 Mentor Graphics Corp. (www.mentor.com)
What are FPGAs?
Field Programmable Gate Arrays

Integrated Circuits(ICs)
Configurable(Programmable)
Configurable components of FPGA are
Logic Blocks
Interconnects
Filed Programmble Device function can be

Modified(configured or programmed) at the site where the
device is installed

What are FPGAs?
Inexpensive, easy realization platform of logic networks in
hardware, as simple as software
Hardware of FPGA contains
PLDs
Logic Gates
RAM
Others
FPGA contains Layout of an unit repeated in matrix form
User can configure
The function of each logic block
I/O Ports
Interconnections between the Logic Blocks and the I/Os

Family of FPGAs
Xilinx
Actel
Altera
DIFFERENCE
Physical means for implementing programmability
Interconnection arrangements
Basic Functionality Logic Blocks

The basic elements of the FPGA structure
Logic blocks
Based on memories (LUT Lookup Table) Xilinx
Based on multiplexers (Multiplexers) Actel
Based on PAL/PLA (PAL - Programmable Array Logic, PLA
Programmable Logic Array) Altera
Interconnection Resources
Symmetrical FPGA-s
Row-based FPGA-s
Sea-of-gates type of FPGA-s
Hierarchical FPGA-s (CPLD)
Input-output cells (I/O Cell)
Possibilities for programming :
Input
Output
Bidirectional
Basic FPGA Architecture

Example: LUT
Digital Logic Function Product AND (&)

Sum OR (|)
3 Inputs
SUM of PRODUCTS
Black Box Truth Table
(Look Up Table LUT)

Example: LUT

Sum OR (|)
3 Inputs
SUM of PRODUCTS
(Look Up Table LUT)

Example: LUT

Sum OR (|)
3 Inputs
SUM of PRODUCTS
(Look Up Table LUT)

Logic Blocks
Logic Functions implemented in Look Up Table LUTs.

Flip-Flops. Registers. Clocked Storage elements.
Multiplexers (select 1 of N inputs)
16-bit SR
16x1 RAM
a 4-input
LUT
b
y
c
mux
d flip-flop
q
e
clock
clock enable
set/reset
FPGA Fabric Logic Block

Look Up Tables LUTs
LUT contains Memory Cells to implement small logic functions

Each cell holds 0 or 1 .
Programmed with outputs of Truth Table
Inputs select content of one of the cells as output
3 Inputs LUT -> 8 Memory Cells
16-bit SR
16x1 RAM
a 4-input
LUT
3 6 Inputs b
c
y
mux
d flip-flop
q
e
clock
clock enable
set/reset SRAM
Static Random Access Memory

SRAM
SRAM cells
Multiplexer MUX
Look Up Tables LUTs
LUT contains Memory Cells to implement small logic functions
Each cell holds 0 or 1 .
Programmed with outputs of Truth Table
Inputs select content of one of the cells as output
Configured by re-programmable SRAM memory cells
3 Inputs LUT -> 8 Memory Cells
16-bit SR
16x1 RAM
a 4-input
LUT
3 6 Inputs b
c
y
mux
d flip-flop
q
e
clock
clock enable
set/reset SRAM
Static Random Access Memory

SRAM
SRAM cells
Multiplexer MUX
Logic Blocks
Larger Logic Functions built up by connecting many Logic

Blocks together

Logic Blocks
Larger Logic Functions built up by connecting many Logic

Blocks together
Determined by SRAM cells
SRAM
SRAM cells

Input Output I/O Getting data in and out
1 0
2 7
Up to > 1,000 I/O pins (several 100 MHz)

General-purpose I/O
banks 0 through 7
3 6 Special I/O SERIALISERS

~ 10 Gbps transfer rates
4 5 Transceiver block
Differential pairs
FPGA

Designing Logic with FPGAs
Design Capture.
High level Description of Logic Design.
Graphical descriptions
Hardware Description Language(Textual)
Graphical State Diagram Textual HDL
When clock rises

If (s == 0)
then y = (a & b) | c;
else y = c & !(d ^ e);
Top-level
block-level
schematic
Graphical Flowchart Block-level schematic

Design Capture.
High level Description of Logic Design.
Graphical descriptions
Hardware Description Language (Textual)
Graphical State Diagram Textual HDL
When clock rises

If (s == 0)
then y = (a & b) | c;
else y = c & !(d ^ e);
Top-level
block-level
schematic
Graphical Flowchart Block-level schematic

High level Description of Logic Design
Hardware Description Language (Textual)
Compile (Synthesis) into NETLIST.

Boolean Logic Gates. Schematic Gate-level
capture netlist
BEGIN CIRCUIT=TEST
INPUT SET_A, SET-B,
DATA, CLOCK,
CLEAR_A, CLEAR_B;
OUTPUT Q, N_Q;
WIRE SET, N_DATA, CLEAR;
GATE G1=NAND (IN1=SET_A,
Target FPGA Device

IN2=SET_B,
OUT1=SET);
GATE G2=NOT (IN1=DATA,
OUT1=N_DATA);
GATE G3=OR (IN1=CLEAR_A,
IN2=CLEAR_B,
OUT1=CLEAR);
GATE G4=DFF (IN1=SET, IN2=N_DATA,
IN3=CLOCK, IN4=CLEAR,
OUT1=Q, OUT2=N_Q);
END CIRCUIT=TEST;
Mapping Mapping
Routing Packing
Bit File for FPGA Place-and-

Route Timing analysis
and timing report
Commercial CAE Tools Fully-routed physical

(CLB-level) netlist
Gate-level netlist
for simulation
(Complex & Expensive) SDF (timing info)
for simulation
Logic Simulation Design Flow

Taxonomy of FPGAs
FPGA
SRAM EPROM
Programmed Antifuse Programmed Programmed
channeled Array
Island Cellular

Programmability in FPGA
Vary from vendor to vendor. All share the common property:

Configurable in one of the two positions ON or OFF
Three programming methods

SRAM Based- Xilinx, Altera
Antifuse Technology Actel, Quciklogic
EPROM/EEPROM
Desired properties:
Minimum area consumption
Low on resistance; High off resistance
Low parasitic capacitance to the attached wire
Reliability in volume production

SRAM Programming Technology
Employs SRAM (Static RAM) cells to

control pass transistors and/or
transmission gates
SRAM cells control the configuration

of logic block as well
Volatile
Needs an external storage
Needs a power-on configuration
mechanism
In-circuit re-programmable
Lesser configuration time
Occupies relatively larger area
SRAM Based Programming
SRAM Cells -> Single Shift Registers
When we Implement a logic into a FPGA device it generates
configuration/bit file. These bit streams are serially loaded into
these SRAM cells.
Millions of SRAM cells holding LUTs and Interconnect Routing
Volatile Memory. Lose configuration when board power is turned
off. JTAG Port
Configuration takes ~ secs Configuration data in

Configuration data out
= I/O pin/pad
= SRAM cell

Anti-fuse Programming Technology
Antifuse: Links in configurable paths

In an unprogrammed state uses materials which normally resides in
high impedance state hence it models as an open ckt.
Applying high voltage to antifuse a connection build between two

metals i.e. nonconducting silicon becomes conducting

Anti-fuse Programming Technology
Very low ON Resistance (Faster implementation of circuits)

Limited size of anti-fuse elements; Interconnects occupy relatively
lesser area
Offset : Larger transistors needed for programming
One Time Programmable
Cannot be re-programmed
(Design changes are not possible) Ex: Dedicated
FPGAS(Glue Logic)
Retain configuration after power off

EPROM, EEPROM or Flash Based
Programming Technology
EPROM Programming Technology

Two gates: Floating and Select
Normal mode:
No charge on floating gate
Transistor behaves as normal n-channel transistor
Floating gate charged by applying high voltage
Threshold of transistor (as seen by gate) increases
Transistor turned off permanently
Re-programmable by exposing to UV radiation
Xilinx Products
The most elementary programmable logic element in a Xilinx

device is called a logic cell, and is composed by a LUT, a MUX
and a FF, with external inputs (5 typically), clock, clock enable,
set/reset and two outputs.
Further up in the hierarchy is a Slice that puts together 2 (or more)

LCs. Each LC in a slice shares the control inputs. Finally, multiple
slices (2 or 4) are grouped in one configurable
logic block (CLB).
Each CLB is an elementary block for routing purposes: the global

interconnect tries to connect together different CLBs, while
internal to a CLB connections are facilitated. This organization is
called island architecture
Xilinx Products

Spartan3 Architecture
Configurable Logic Blocks (CLBs)
RAM-based Look-Up Tables (LUTs) for logic
Storage elements configured as flip flops or latches
Input/Output Blocks (IOBs)
Control data flow between I/O pins and internal logic
Various signal standards/terminations
Programmable Interconnects(PI)
RAM Blocks
Data storage in 18k-bit dual-port blocks
Multipliers
2 18-bit binary inputs, 36 bit output
Digital Clock Manager (DCM)
Distribute, multiply, divide, or shift clock
Programmable Interconnect
Interconnect architecture is a trade-o between the necessity of
flexible and abundant connectivity with the cost (in area and delay)
of large interconnect
Too little interconnect results in routability problems for all but
the simplest designs
Too much reduces the performance and increases the cost
dramatically
The trade-off is normally that of providing various types of
connections for local or global signals, and to limit the flexibility
of connects (not all signals are connected to all signals)
In the case of island-based architectures, a typical organization

uses Switch boxes that allow routing a signal in different directions
and forking it.
Fast Carry chain
In order to facilitate arithmetic operations (fundamental for
DSP!!), most FPGAs provide Fast Carry Chains: dedicated logic
that can propagate and generate carries more quickly than passing
through a cascade of LUTs.
In practice, each LC contains carry logic that is connected through

dedicated wires to the carry logic of other LCs in the same slice,
between slices and between CLBs. Adders and counters can
therefore implemented much more efficiently.

Embedded (or Block) RAMs
On top of the distributed RAMs, most FPGAs have extra chunks of
RAM positioned in specific areas (periphery, scattered or in
columns) that can be used for larger memory requirements.
Up to Mbit capacity are available in larger devices. Such e-RAMs

can be used independently or together to form functional RAMs
(single or dual-ported) as well as FIFOs, state machines...

Embedded Arithmetic/DSP blocks
To overcome the bottleneck of complex arithmetic operations such
as multiplications, most FPGAs offer embedded multipliers,
MACs, or other DSP-friendly functions, scattered around the
layout as the e-RAMS.

Embedded Cores
Finally, some devices can embed entire processor cores, either
physically (hard cores) or via configuration (soft cores). The first
ones are obviously faster but also less flexible.

Clock Managers
Many FPGA design (DSP especially!) need to use different rates
for different parts. For this reason modern FPGAs provide blocks
that help generating and distributing clock to various domains.
Clock Trees: Make sure that clocks are distributed evenly across
the chip, avoiding skew. It uses special tracks and should use
special input pins to make sure that the distribution is correct.
Clock Managers: generate derived clocks out of a clock input,

controlling jitter and synthesizing multiples or submultiples of
frequency, guaranteeing a fixed phase relation. A feedback
connection is used to control skew between master and derived
clocks.
Clock Managers
IOs: FPGAs IOs are just as flexibly configurable (typically in
banks) as their logic blocks: they can use a number of I/O
standards (in voltage, differential signaling, with automatic
termination, fanout...).
As different IO can use different voltage levels, typically power
supply has both core voltage and I/O voltages, one for each bank.
Transceivers: To enable very fast data rate, some FPGAs embed

transceiver blocks that allow fast differential signaling (at Gigabit
rates).

Product FPGA vs ASIC
Comparison:
FPGA benefits vs ASICs:
- Design time: 9 month design cycle vs 2-3 years
- Cost: No $3-5 M upfront (NRE) design cost.
No $100-500K mask-set cost
- Volume: High initial ASIC cost recovered only in very high volume
products
Due to Moores law, many ASIC market requirements now met by FPGAs
Fast Turnaround Designs
Re-Programmability, Flexibility
Resulting Market Shift:

Dramatic decline in number of ASIC design starts:
FPGAs (or programmable logic) is the fastest growing segment of the semiconductor
industry!!

Q&A
Thank YOU


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Introduction to

The Design Warriors Guide to FPGAs

Field Programmable Gate Arrays

Filed Programmble Device function can be

The Design Warriors Guide to FPGAs

The Design Warriors Guide to FPGAs

The Design Warriors Guide to FPGAs

The Design Warriors Guide to FPGAs

Digital Logic Function Product AND (&)

The Design Warriors Guide to FPGAs

Digital Logic Function Product AND (&)

The Design Warriors Guide to FPGAs

Digital Logic Function Product AND (&)

The Design Warriors Guide to FPGAs

Logic Functions implemented in Look Up Table LUTs.

FPGA Fabric Logic Block

The Design Warriors Guide to FPGAs

LUT contains Memory Cells to implement small logic functions

3 Inputs LUT -> 8 Memory Cells

Static Random Access Memory

3 Inputs LUT -> 8 Memory Cells

Static Random Access Memory

Larger Logic Functions built up by connecting many Logic

The Design Warriors Guide to FPGAs

Larger Logic Functions built up by connecting many Logic

The Design Warriors Guide to FPGAs

Up to > 1,000 I/O pins (several 100 MHz)

3 6 Special I/O SERIALISERS

The Design Warriors Guide to FPGAs

When clock rises

Graphical Flowchart Block-level schematic

The Design Warriors Guide to FPGAs

Graphical State Diagram Textual HDL

When clock rises

Graphical Flowchart Block-level schematic

The Design Warriors Guide to FPGAs

Compile (Synthesis) into NETLIST.

GATE G1=NAND (IN1=SET_A,

Target FPGA Device

Bit File for FPGA Place-and-

Commercial CAE Tools Fully-routed physical

Logic Simulation Design Flow

The Design Warriors Guide to FPGAs

The Design Warriors Guide to FPGAs

Vary from vendor to vendor. All share the common property:

Three programming methods

The Design Warriors Guide to FPGAs

Employs SRAM (Static RAM) cells to

SRAM cells control the configuration

Configuration takes ~ secs Configuration data in

The Design Warriors Guide to FPGAs

Antifuse: Links in configurable paths

Applying high voltage to antifuse a connection build between two

The Design Warriors Guide to FPGAs

Very low ON Resistance (Faster implementation of circuits)

The Design Warriors Guide to FPGAs

EPROM Programming Technology

The most elementary programmable logic element in a Xilinx