CMOS Technology
Modern CMOS Technology
A modern CMOS process flow is
discussed.
In the simplest CMOS technologies, we
need to integrate simply NMOS and PMOS
transistors for circuits .
Typical
CMOS
technologies
in
manufacturing today add additional steps
to implement multiple device VTH, TFT
devices for loads in SRAMs, capacitors for
DRAMs etc.
Process described here will require 16
masks (through metal 2) and > 100
process steps.
Examples of Simple CMOS Circuits
+V
+V
IN1
PMOS
IN2
OUTPUT
OUTPUT
INPUT
NMOS
GND
An Inverter
GND
A NOR Gate
CMOS Process Flow
D
G
Sub
Sub
P+
N+
P+
NWellPMOSSubstrate
N+
PWellNMOSSubstrate
Final result of the process flow we will consider.
CMOS Process Flow
Photoresist
Si3N4
SiO2
Si,(100),PType,550cm
Substrate selection: moderately high resistivity, (100)
orientation, P type.
Wafer cleaning, thermal oxidation ( 40 nm), nitride
LPCVD deposition ( 80 nm), photoresist spinning and
baking ( 0.5 - 1.0 m).
CMOS Process Flow
Mask #1 patterns the active areas.
The nitride is dry etched: Si3N4+12F3SiF4+2N2
PR is stripped.
CMOS Process Flow
Field oxide is grown using a LOCOS process.
Typically 90 min @ 1000 C in H2O grows 0.5 m.
Si3N4 is then stripped
Process options: STI
Process Option for device Isolation- Shallow Trench
Isolation
Si trench etching
Bromine based plasma chemistry
Filling of trenches with deposited
oxide
High Density Plasma
Thermally grown SiO2 liner
High Temp.:1100C oxidation
CMP to produce planar surface
CMOS Process Flow
Boron
PImplant
Mask #2 blocks a B+ implant to form the wells for the
NMOS devices. Typically 1013 cm-2 @ 150-200 KeV.
CMOS Process Flow
Phosphorus
NImplant
PImplant
Mask #3 blocks a P+ implant to form the wells for the
PMOS devices. Typically 1013 cm-2 @ 300+ KeV. (why P)
CMOS Process Flow
NWell
PWell
A high temperature drive-in produces the final well
depths and repairs implant damage. Typically 4-6 hours @
1000 C - 1100 C or equivalent Dt : (2-3 um)
Process Options: Field Implant/Buried & Epi Layer
Process Options for Active Region
Field Implant
Dose:1013 cm-2 at 50keV
LOCOS
Low energy P+
and N+ at 50keV
Option for active
region formation
Buried and Epitaxial Layers
N+ Buried layer
As implant
Dose:1015 cm-2 50keV
Drive-in in oxidizing ambient
P+ implant: B 1014cm-2 50keV
Continued..
P+ & N+ drive in
Si Epi growth
Process options incorporating buried and epitaxial layer
CMOS Process Flow
Boron
NWell
PWell
Mask #4 is used to mask the PMOS devices. A VTH adjust
implant is done on the NMOS devices, typically a 1-5 x 1012
cm-2 B implant @ 50 - 75 KeV.[NMOS:+ve,PMOS:-ve]
CMOS Process Flow
Arsenic
NWell
PWell
Mask #5 is used to mask the NMOS devices. A VTH adjust
implant is done on the PMOS devices, typically 1-5 x 1012
cm-2 As+ implant @ 75 - 100 KeV.
CMOS Process Flow
N
NWell
PWell
The thin oxide over the active regions is stripped and a
new gate oxide grown, typically 3 - 5 nm, which could be
grown in 0.5 - 1 hrs @ 800 C in O2.
CMOS Process Flow
Polysilicon is deposited by LPCVD ( 0.5 m).
An
unmasked P+ or As+ implant dopes the poly (typically 5 x
1015 cm-2). [ In-situ doping]
CMOS Process Flow
NWell
PWell
Mask #6 is used to protect the MOS gates. The poly is
plasma etched using chlorine or bromine based plasma
chemistry. (Selectivity & Degree of anisotropic etching)
CMOS Process Flow
Phosphorus
NImplant
NWell
PWell
Mask #7 protects the PMOS devices. A P+ implant forms
the LDD regions in the NMOS devices (typically 5 x 1013
cm-2 @ 50 KeV).
CMOS Process Flow
Boron
PImplant
NImplant
NWell
PWell
Mask #8 protects the NMOS devices. A B+ implant forms
the LDD regions in the PMOS devices (typically 5 x 1013 cm-2
@ 50 KeV).
CMOS Process Flow
PImplant
NImplant
NWell
PWell
Conformal layer of SiO2 is deposited (typically 0.5 m).
CMOS Process Flow
PImplant
NImplant
NWell
PWell
Anisotropic etching leaves sidewall spacers along the
edges of the poly gates.
CMOS Process Flow
Arsenic
P
N+Implant
NWell
PWell
Mask #9 protects the PMOS devices, An As+ implant forms
the NMOS source and drain regions (typically 2-4 x 1015 cm-2
@ 75 KeV).
(Channeling)
CMOS Process Flow
Boron
P+Implant
N+Implant
NWell
PWell
Mask #10 protects the NMOS devices, A B+ implant forms
the PMOS source and drain regions (typically 1-3 x 1015 cm-2
@ 50 KeV).
CMOS Process Flow
P+
N+
P+
NWell
N+
PWell
A final high temperature anneal drives-in the junctions
and repairs implant damage (typically 30 min @ 900C or 1
min RTA @ 1000C.
(TED)
CMOS Process Flow
P+
P+
N+
NWell
N+
PWell
Ti is deposited by sputtering (typically 100 nm).
CMOS Process Flow
P+
P+
N+
NWell
N+
PWell
The Ti is reacted in an N2 ambient, forming TiSi2 and TiN
(typically 1 min @ 600 - 700 C). Role of sidewall spacer
CMOS Process Flow
P+
P+
N+
NWell
N+
PWell
Mask #11 is used to etch the TiN, forming local
interconnects. Annealing at 800C in Ar to reduce resistivity
to 10 ohm/Sq and 1 ohm/Sq.
CMOS Process Flow
P+
P+
N+
NWell
N+
PWell
A conformal layer of doped SiO2 (PSG/BPSG)is deposited by
LPCVD (typically 1 m).
CMOS Process Flow
P+
P+
N+
NWell
N+
PWell
PR coating+ blanket etching or CMP is used to planarize
the wafer surface.
CMOS Process Flow
P+
P+
N+
NWell
PWell
Mask #12 is used to define the contact holes.
The SiO2 is etched.
N+
CMOS Process Flow
TiN
P+
P+
N+
NWell
N+
PWell
A thin TiN barrier layer is deposited by sputtering (typically
a few tens of nm), followed by W CVD deposition.
CMOS Process Flow
CMP is used to planarize the wafer surface, completing the
damascene process.
CMOS Process Flow
P+
P+
N+
NWell
N+
PWell
Al/Si/Cu is deposited on the wafer by sputtering. Mask #13 is
used to pattern the Al and plasma etching is used to etch it.
CMOS Process Flow
P+
P+
N+
NWell
N+
PWell
Intermetal dielectric and second level metal are
deposited and defined in the same way as level #1.
Mask #14 is used to define contact vias and Mask
#15 is used to define metal 2. A final passivation
layer of Si3N4 is deposited by PECVD and patterned
Summary of Key Ideas
An initial discussion on the CMOS process flow
provides an introduction to the modern VLSI
technology.
It provides a perspective on how individual
technologies like oxidation and ion implantation
are actually used.
There are many variations on CMOS process flows
used in the industry.
The process described here is intended to be
representative, although it is simplified compared
to many current process flows.
Summary of Key Ideas
Perhaps the most important point is that while
individual process steps like oxidation and ion
implantation are usually studied as isolated
technologies, their actual use is very much
complicated by the fact that IC manufacturing
consists of many sequential steps, each of which
must integrate together to make the whole process
flow work in manufacturing.
CMOS Process Flow
P+
P+
N+
NWell
N+
PWell
An unmasked oxide etch allows contacts to Si and poly
regions.
