CMOS (Complimentary Metal Oxide Silicon) FET

Inverter PMOSFET NMOSFET

+V Source Gate Drain

PMOS

Output
Input
NMOS
P+ P+ N+ N+
GND
N-well P-well

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Modules of CMOS Fabrication
Isolation

Well Formation
Front-end
Gate Stack Formation

Source/Drain formation

Silicidation/Contact

Metallization Back-end

Passivation

Packaging

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 CMOS Process Flow (1)

• Substrate selection: moderately high resistivity, (100) orientation, p-type.

• Wafer cleaning (piranha cleaning)
• Thermal oxidation (Pad Oxide, ∼ 400 Å), nitride LPCVD deposition (∼ 800 Å)
• photoresist spinning and baking (∼ 0.5 - 1.0 μm).

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 CMOS Process Flow (2)

• Mask #1 patterns the active areas. The nitride is dry etched.

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 CMOS Process Flow (3)

• Field oxide is grown using a LOCOS process.

Typically 90 min @ 1000°C in a wet ambient grows
oxide » 0.5 μm.
Note: In modern CMOS processing, STI (Shallow Trench Isolation) process is used.
We will cover the STI later

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 CMOS Process Flow (4)

• Mask #2 blocks a B+ implant to form the wells for the NMOS

devices. Typical dose and energy : ~1013 cm-2 and 150-200 KeV.

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 CMOS Process Flow (5)

• Mask #3 blocks a P+ implant to form the wells for the

PMOS devices. Typically 1013 cm-2 @ 300+ KeV.

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 CMOS Process Flow (6)

N-well P-well

• A high temperature drive-in produces the “final” well depths. Typically 4-10
hours @ 1000 °C - 1100 °C

Note: In modern CMOS processing, this high temperature drive-in is no more

popular. Instead, high energy ion implantation process is widely used.

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 CMOS Process Flow (7)

• Mask #4 is used to mask the PMOS devices. A VTH adjust implant is done on the
NMOS devices, typically a 1-5 x 1012 cm-2 B+ implant @ 50-75 KeV.

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 CMOS Process Flow (8)

• Mask #5 is used to mask the NMOS devices. A VTH adjust implant is

done on the PMOS devices, typically 1-5 x 1012 cm-2 As+ implant
@ 75 - 100 KeV.

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 CMOS Process Flow (9)

• The thin oxide over the active regions is stripped in HF solution and
a new gate oxide grown, typically 50 - 100 Å, which could be grown in
1 - 2 hrs @ 800 °C in O2.

Note: in modern devices, thin sacrificial oxidation (50-80 Å) and wet clean is
done prior to the gate oxide growth to remove the damaged silicon surface.
Gate oxide thickness is also reduced, down to ~ 10 Å to support device scaling.
In order to grow such a thin oxide, process temperature is much reduced
(<700°C) and diluted gas is being used.

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 CMOS Process Flow (10)

• Polysilicon is deposited by LPCVD ( ~ 0.5 μm).

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CMOS Process Flow (11)

• Mask #6 is used to protect the MOS gates. The poly is

plasma etched using an anisotropic etch. Thin gate oxide
is acting as an etch stop layer during the anisotropic
plasma etch

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 CMOS Process Flow (12)

• Mask #7 protects the PMOS devices. A P+ implant forms the LDD

regions in the NMOS devices (typically 5 x 1013 cm-2 @ 50 KeV).

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 CMOS Process Flow (13)

• Mask #8 protects the NMOS devices. A B+ implant forms the LDD

regions in the PMOS devices (typically 5 x 1013 cm-2 @ 50 KeV).

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 CMOS Process Flow (14)

• A conformal layer of SiO2 is deposited (typically 0.5 μm).

Note: in modern devices, a conformal layer of Si3N4 is deposited as a spacer material,

typically < 300A. Oxide spacer film can be easily removed during subsequent mid-section
processes, not providing accurate spacer dimension for Source/Drain junction formation.
Gate to gate spacing and short channel effect control should be considered when you
decide the spacer thickness.

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 CMOS Process Flow (15)

• Anisotropic etching leaves “sidewall spacers” along the edges

of the poly gates.

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 CMOS Process Flow (16)

• Mask #9 protects the PMOS devices, An As+ implant forms the NMOS source
and drain regions (typically 2-4 x 1015 cm-2 @ 75 KeV).

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 CMOS Process Flow (17)

• Mask #10 protects the NMOS devices, A B+ implant forms the PMOS
source and drain regions (typically 1-3 x 1015 cm-2 @ 50 KeV).

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 CMOS Process Flow (18)

• A final high temperature anneal activates the junctions and repairs

implant damage (typically a few seconds RTA @ 1000 °C).

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 CMOS Process Flow (19)

• An unmasked oxide etch allows contacts to Si and poly regions.

This is often called “Source/Drain clean”, done in HF or buffered
oxide etch solutions.

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 CMOS Process Flow (20)

• Ti is deposited by sputtering (typically 1000 Å).

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 CMOS Process Flow (21)

• The Ti is reacted in an N2 ambient, forming TiSi2 and TiN (typically

1 min @ 600 °C). After the formation anneal, un-reacted metal is
etched with sulfuric acid clean.

Note: in modern logic devices, RTA is commonly used for the silicide formation anneal.
Temperature is carefully chosen to complete the phase formation.

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 CMOS Process Flow (22)

• SiO2 is deposited for electrical isolation.

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CMOS Process Flow (23)

• CMP is used to planarize the wafer surface.

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 CMOS Process Flow (24)

• Mask #11 is used to define the contact holes. The SiO2 is etched.

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 CMOS Process Flow (25)

• A thin Ti/TiN barrier layer is deposited by sputtering (Ti) and CVD

(TiN) (typically a few hundred Å), followed by W CVD deposition.

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 CMOS Process Flow (26)

• CMP is used to planarize the wafer surface.

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 CMOS Process Flow (27)

• Al is deposited on the wafer by sputtering. Mask #12 is used to

pattern the Al and plasma etching is used to etch it.

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 CMOS Process Flow (28)

• Second level metal is deposited and defined in the same way as Al level #1.
• Mask #13 is used to define contact vias and Mask #14 is used to define metal 2.
• A final passivation layer of Si3N4 is deposited by PECVD
• This completes the CMOS structure. The processing details and some process
options are described in Chapter 2 in the text.

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