An Introduction To PIC Microcontrollers: Unit 2: Microcontroller Architecture
An Introduction To PIC Microcontrollers: Unit 2: Microcontroller Architecture
An Introduction To PIC Microcontrollers: Unit 2: Microcontroller Architecture
UNIT 2 : MICROCONTROLLER
ARCHITECTURE:
Introduction to PIC microcontrollers, Architecture
and pipelining, program memory considerations,
Addressing modes, CPU registers, Instruction set,
simple operations.
04/07/08 Institute of Technology and Management, Gurgaon 1
Introduction
These four clocks make up one instruction cycle (also called machine
cycle) during which one instruction is executed.
Decoding and execution of instruction are done between the next Q1 and
Q4 cycles. On the following diagram we can see the relationship between
instruction cycle and clock of the oscillator (OSC1) as well as that of
internal clocks Q1-Q4. Program counter (PC) holds information about the
address of the next instruction.
• PIC16F84 has two separate memory blocks, one for data and the other for
program. EEPROM memory with GPR and SFR registers in RAM memory
make up the data block, while FLASH memory makes up the program
block.
• Program memory
Program memory has been carried out in FLASH technology which makes
it possible to program a microcontroller many times before it's installed
into a device, and even after its installment if eventual changes in program
or process parameters should occur. The size of program memory is 1024
locations with 14 bits width where locations zero and four are reserved for
reset and interrupt vector.
• Locations of RAM memory are also called GPR registers which is an abbreviation
for General Purpose Registers. GPR registers can be accessed regardless of which
bank is selected at the moment.
• Stack
PIC16F84 has a 13-bit stack with 8 levels, or in other words, a group of 8 memory locations, 13 bits wide,
with special purpose. Its basic role is to keep the value of program counter after a jump from the main
program to an address of a subprogram . In order for a program to know how to go back to the point where
it started from, it has to return the value of a program counter from a stack. When moving from a program
to a subprogram, program counter is being pushed onto a stack (example of this is CALL instruction).
When executing instructions such as RETURN, RETLW or RETFIE which were executed at the end of a
subprogram, program counter was taken from a stack so that program could continue where was stopped
before it was interrupted. These operations of placing on and taking off from a program counter stack are
called PUSH and POP, and are named according to similar instructions on some bigger microcontrollers.
• Indirect unlike direct addressing does not take an address from an instruction but derives it
from IRP bit of STATUS and FSR registers. Addressed location is accessed via INDF register
which in fact holds the address indicated by a FSR. In other words, any instruction which uses
INDF as its register in reality accesses data indicated by a FSR register. Let's say, for instance,
that one general purpose register (GPR) at address 0Fh contains a value of 20. By writing a
value of 0Fh in FSR register we will get a register indicator at address 0Fh, and by reading
from INDF register, we will get a value of 20, which means that we have read from the first
register its value without accessing it directly (but via FSR and INDF). It appears that this type
of addressing does not have any advantages over direct addressing, but certain needs do exist
during programming which can be solved smoothly only through indirect addressing.
• Indirect addressing is very convenient for manipulating data arrays located in GPR registers.
In this case, it is necessary to initialize FSR register with a starting address of the array, and
the rest of the data can be accessed by incrementing the FSR register.
• INTCON Register
• Bit 7 GIE (Global Interrupt Enable bit) Bit which enables or disables all interrupts.
1 = all interrupts are enabled
0 = all interrupts are disabled
• Bit 6 EEIE (EEPROM Write Complete Interrupt Enable bit) Bit which enables an interrupt at the end
of a writing routine to EEPROM
1 = interrupt enabled
0 = interrupt disabled
If EEIE and EEIF (which is in EECON1 register) are set simultaneously , an interrupt will occur
• bit 0 RBIF (RB Port Change Interrupt Flag bit) Bit which informs about
changes on pins 4, 5, 6 and 7 of port B.
1 = at least one pin has changed its status
0 = no change occurred on any of the pins
Bit has to be cleared in an interrupt subroutine to be able to detect further
interrupts.