System Verilog

System Verilog
System Verilog is a language that was based on the description language of
Hardware Verilog 95 and for this reason it encompasses most of the design aspects of
system and the testbench that Verilog offers.

Meanwhile, System Verilog is proposed to offer more possibilities in order to.

to support that some advanced VHDL functions are also included.
 System Verilog

In addition, System Verilog aims to be both a HDL and HVL, that is, suitable for
coding (project) as well as verification.. This requires other functionalities that still
they were not available in Verilog or VHDL, but in E or Open Vera. System Verilog was
very influenced by Open Vera and for this reason resembles this HVL more.

The complete language:

2. Types

Edelweis Helena Garcez Ritt 2006

 System Verilog Page 3

System Verilog has the following data types:

Int and short int 2 states (0 and 1)
integer 4 states (0, 1, Z, and X)

long int 64 bits

signed and unsigned int
bit 2 states
byte 8 bits signed
logic 4 states
string
Enum

Declaration: <type> <object>;

Packed arrays are what we know in VHDL as bit_vector.

Enumeration

The enumeration type is similar to C.

Edelweis Garcez Ritt

 System Verilog

2.2. Arrays

System Verilog supports Arrays, as well as the known HDLs. There is the concept of
packed and unpacked array.

2.3. Dynamic Arrays

Dynamic arrays are also possible in System Verilog, logically for the
verification part.
Example of code:
int memory[];
memory=new[64];
memory = new[128](memory); // preserves the content of the array of 64
int size = size(memory); //returns the current size
[Link]; // deletes the dynamic array
We can index arrays using different types.
int vetor1[0];
int vetor2["hi"];

2.4. Rows

System Verilog also offers queues that increase and decrease in time.
for execution and accept commands to enqueue and dequeue.
You can place elements either at the beginning or at the end, and 0 indicates the first element, 1
the second and so on, while $ represents the last.
An important point is that semantics requires constant access time.
Examples of queues with limited or unlimited size:
int canal[$]; //list of integers
byte data[$] = { 2h'00, 2h'FF}; //byte list with initialization
int restricted_queue[$:16]; //queue with a maximum of 16 elements
Examples of operations that can be performed with queues and are already provided in System
Verilog:

Edelweis Helena Garcez Ritt 2006

 System Verilog Page5

int e, pos;
int canal2[$]; // another queue without limit
e=canal[0]; //gets the first (leftmost) element of the queue
canal2=canal; // copia uma fila completa
canal[0]=e; // writes in the first position of the queue
canal=canal[1:$]; // copies the list to itself without the first element, that is, deletes the first one
canal2={e, canal}; // builds a list with the element e concatenated with the channel list
canal={}; // esvazia a fila
canal = {canal{0:pos},e,canal{pos+1:$}}; // insert the element e at position pos

Functions that exist for queues:

function int size(); //returns the size
function void delete(); // empties the queue
function void insert(); //places the element e in position i, usage: <name>.insert(I,e)
function queue_type pop_front(); //remove the first element
function queue_type pop_back(); //remove the last element
function queue_type push_front(); //inserts a first element and, usage: <name>.push_front(e)
function queue_type push_back(); // inserts an element at the end and use: <name>.push_back(e)

2.5. Interfaces

An interface groups and encapsulates a set of wires just like a struct does.
with variables. It facilitates access and use.

Interfaces are instantiated and save us from having to define signals that are output in
a module and input in another.

Edelweis Garcez Ritt

 System Verilog

Example without the use of interfaces:

An example using interfaces:

2.6. Structs

Very similar to structs in C or C++.

typedef struct {
byte data;
bit valid;
structure;

2.7. Casting

Edelweis Helena Garcez Ritt 2006

 System Verilog Page7

Types can be changed using a casting operator, as in VHDL or C.

Int' (2.0 * 3.0) // converts the result to int

2.8. Definition of types

Similar to C

3. Scope
System Verilog also allows the declaration of global and local signals and variables.

Int max = 10;

Int n;
module topo;
int n;
initial begin
automatic int i; // local variable like in C
n = 2;
end
initial begin: my block
n=1
$root.n = n; // $root.n é a variável global e n é aqui a local
end
endmodule

4. Operators
Among the various types, there are operators that can be used:
& e ~& And not-e
| e ~| Either or neither

^ e ~^
== e !== Equality and inequality

Edelweis Garcez Ritt

 System Verilog

e shifts

4.1. Operator Overloading

System Verilog supports overloading. Example:

typedef struct {
int A;
real B
} mixed_structure;

mixed_structure X,Y,Z;
bind + function mixed_structure fadds(mixed_structure, mixed_structure);
bind + function mixed_structure faddi(mixed_structure, integer);

assign X = Y + 2; // will call the faddi function

assign Y += Z; // will call the fadds function
Note that for each call, the function would have to be defined. The example lacked the definition.
using mixed and real structure, for example.

5. Literals
Literals work similarly to Verilog.
reg [31:0] a, b;
reg [15:0] c,d;
...
a = 32'hf0ab;
c = 16'hFFFF;
a = '0; // fills an array packed with 0s

There are besides these time literals

#10 a<= 1;
#5ns b <= !b;

6. Describe hardware
Naturally, as an HDL, System Verilog must allow for the description of hardware.
This is done by defining hardware modules. Let's see an example:

Edelweis Helena Garcez Ritt 2006

 System Verilog Page 9

module generate_clock (output type clk);

parameter logic initial_value=0;
parameter type tipo = bit;
parameter time atraso = 100;

initial clk <= initial_value;

always #delay clk <= !clk;

endmodule

module topo;
logic clk;

gera_clock #(.initial_value(1'b1), .delay(50), .type(int)) c clk; //clock generator instance

always @clk $display ("Clock= %b", clk);

initial
begin
repeat(10) on the positive edge of clk;

$finish(0);
end
endmodule

7. Describe Verification
In System Verilog, the DUT and the testbench code are separated. This is provided.
through language.
In System Verilog, all the automation that had to be done manually using the
normal verification languages can be automated within the language.
Example:

virtual class EnvBaseClass;

virtual task pre_test();
virtual task start_test();
virtual task main_test();
virtual task stop_test();
virtual task post_test();
virtual task finish_test();
endclass

Edelweis Garcez Ritt

 System Verilog

class EnvClass extends EnvBaseClass;

task main();
pre_test();
start_test();
endtask
task pre_test();
blabla //define the pre_test as you wish preparing what is necessary
andtask
and here are the other tasks to redefine if needed
endmodule

program My_estbench(interface dut_if);

EnvClass My_Environment = new;
initial
begin
fork
My_environment.main();
join_none
end
final
begin
My_environment.finish_test();
$finish;
end
end program

8. Classes
System Verilog offers classes, as it is an object-oriented language.
therefore it offers encapsulation, inheritance, and polymorphism.

System Verilog offers Methods in the same way as any language.

object-oriented does, in addition to functions and tasks. The main difference
It is between functions and tasks that tasks can be blocked and functions cannot.
In addition, we have handles and instances for the objects. Note that System Verilog does not
there are no other types of pointers like in C or C++.
Example:
class pacote;
Blabla;
cnd class;

Edelweiss Helena Garcez Ritt 2006

 System Verilog Page 11

package package1; // pointer to a structure pointing to nothing

package package2=new; // creates the pointer and already allocates an area

The word this is used to identify the local version.

Class my_class;
Int a;
property(int a)
this.a=a; // to avoid ambiguity
end task
end class
In these cases, it might be best to use different names, but this is part of the style.

8.1. Constructors

Just like object-oriented languages, System Verilog has constructors.

some are already built-in like new or delete and those for specific application. Can't be called
builders' tasks.

8.2. Scope

Just like Verilog, System Verilog allows observing all signals giving
the complete path within the hierarchy, which is not possible using VHDL.

9. Program Blocks
It is a way to encapsulate what is used in the testbench of your DUT. This
barrier naturally exists if we are using HDL and HVL, but in the case of System
Verilog could mix things up and so there is a need for this separation.
In addition, program blocks help with portability and reuse. It is a way
methodological approach to isolating the transactors.

Features: it has a single initialization block; executes events in a phase of

synchronized verification to simulation events; can use the $exit task that terminates the
simulation after all program blocks have finished executing.

10. Interfaces
Interfaces represent the ports that communicate the modules. In fact, they serve
as a way to define bundles of types and reuse them. Interfaces do not have direction and
this avoids defining a port on one side as output and on the other as input like
you know in VHDL.

Edelweis Garcez Ritt

 System Verilog

11. Clocking Blocks

System Verilog offers clocking blocks that are declared using the word
clocking and endclocking. This construction serves to identify the different domains of
clock, and contains information about the clock signal, the timing and synchronization of the blocks in
which clock is used. Using clock domains in the testbench allows for the methodology
based on cycles instead of event-based. This makes it easier to avoid race conditions.
do testbench in relation to the DUT.

12. Randomizing the Verification

As we have seen in the testbench and verification lesson, it is difficult to decide which data
They should be used for the 'questions' we ask the system, and there we have already seen the possibility
to use random data, that is, random data, in each round of the regression
we are testing something different or we can run the check with random data until
to achieve a code coverage that is acceptable for us.
class randomica;
rand int field1;
rand int rand2;
function new();
int status;
status=randomize();
end function;
end class;

12.1. pre- and post-randomize

Edelweis Helena Garcez Ritt 2006
 System Verilog Page 13

Two empty classes that are there to be rewritten with things that need to be.
done before or after randomization.
Srand(seed) can initialize the seed of the randomization function.

[Link] of randomization

Verilog already contained the random function, which generates a random value within a
interval of values. System Verilog offers, in addition to random, cyclic random, which generates
deterministic data if the same seed is used.
Randcase: One can also randomize which type of function will be called:
Class lala;
task main();
pre_test();
start_test();
random case
5: main_test(); //25%
5: stress_tes(); //25%
1: error_teste(); //5%
9: normal_test(); //45%
end case;
stop_test();
end task;

12.3. Restrictions

Since we want random data, but there is data that does not interest us,
It is possible to restrict the random data that is generated.
class base;
rand int y;
rand int x;
constraint R {y > x;} //boolean expression
End class

Também é possível dar probabilidades para dados em um intervalo ou valor

to happen.

12.3.1. Interactive Restrictions

One feature that System Verilog also offers is the ability to generate
interactive restrictions.
class C;
rand byte A[];

Edelweis Garcez Ritt

 System Verilog

constraint C1{foreach {A[i]} A[i] inside {2,4,8,16}; }

constraint C2{foreach{A[j]} A[j]>2 *j; }
endclass

13. Abstraction and reuse

The use of abstraction and reuse is very important for the efficiency of the verification team.
Many of the constructions that are offered are related to object-oriented programming
objects. It is known that we need to reuse the verification code to increase the
team efficiency and reuse. The verification code must be portable and OOP helps with this.
aspect.

Inheritance

Inheritance is a concept that exists in OOP and serves us for verification.

And it offers a similar inheritance, that is, similar.

class BasePacket
int id;
byte Payload[];
task send(bit data[]);
end task
endclass
class ATMPacket extends BasePacket;
byte header[0:4];
function new; // redefine the function
[Link](); // calls the parent constructor
payload = new[48];
.....
end function;
task send(bit data[]); // overrides the parent method
....
endtask
endclass
System Verilog does not support multiple inheritance, but it is not extremely necessary.
for the purposes of verification. Super. is used to redefine the parent method.
It is also possible to completely rewrite a method:
class my_base;
virtual task method_a();
blabla
endtask

Edelweiss Helena Garcez Ritt 2006

 System Verilog Page 15

endclass

class my_class extends my_base;

task method_a();
bla bla
endtask
endclass
you rewrite parts and reuse (inherit) others.
More complete example:

This example is nothing exceptional, just define the writing and reading on
dam. But note that we can now use this superior class to create a class
understood, for example, that writes incorrectly, to see how the system behaves
with errors. In general, the erroneous behavior is quite similar, having only a CRC error.
or a wrong bit or a different byte. So let's take a look at a type of extension that writes
but using the most significant bit corrupted by writing 0 in it.

Or use writing to "store" my value for comparison somewhere.

posterior.
Another possibility would be to define another method and use super. to "inherit" it.
that already exists. It's another way to implement.

[Link] Classes

Edelweis Garcez Ritt

 System Verilog

Abstract classes are used as a template for new classes. They serve for reuse.
the idea is to partition the functionality into basic classes and derived classes which helps the
reuse, but note that this must be planned.

virtual class BasePacket;

int id;
virtual task send(bit [0:47] data);
end task
endclass

class ATMPacket extends BasePacket;

byte header[0:4];
task send(bit[0:47]); //implementation of the new task
.....
End task
endclass

[Link]

Polymorphism is the principle by which two or more classes derived from a

the same superclass can invoke methods that have the same identifier (signature), but
distinct behaviors, specialized for each derived class, using therefore a
reference to an object of the superclass type
For example, we simply defined the sending of data (packet) as 31 bits.
virtual class package;
bit [31:0] data;
virtual task send;
endtask
endclass
But suppose we have more than one type of package, with different fields. Thus,
class package_ATM extends package;
bit [55:0] data;
send task;
bla bla
endtask
endclass
class packageToken extends package;
bit [127:0] data;
send task;
bla bla
endtask
endclass

Edelweis Helena Garcez Ritt 2006

 System Verilog Page 17

Two different classes are defined, but they send data packets, each having
your differentiated shipping task.
package ListOfPackages[100]
ATM package pa = new; // creates an ATM package
packageToken pt = new; //creates a Token package
ListadPacotes[0]=pa;
ListadePacotes[1]=pt;
...
ListadePacotes[0].send; // knows that it should use the send from the ATM package
PackageList[1].send; //knows that it should use the send of packets of type Token.

[Link]

System Verilog offers the same type of package as VHDL. The declaration is made in
package file.
package ClassesBasicas;
virtual class Base;
int id;
virtual task status;
end task
end class
…
endpackage
Then it is used in the main program:
program BFM;
import BasicClasses::Base;

class CPUEnv extends Base;

task status;
...
endtask
endclass
....
endprogram

14. Code Coverage

The System Verilog language has constructs to aid in coverage metrics.
There are two types of code coverage: one that is automatically extracted from the code and
which was seen in a specific class, and another that is specified by the user and serves to
correlate the verification environment with the required functionality (spec).

Edelweis Garcez Ritt

 System Verilog

The constructions presented here serve for the second case, also called
of functional coverage.
Functional coverage is a metric that indicates how much of the spec has been verified.
used to relate to the verification environment the corner cases, the invariants of
specification and some other conditions.
Since this type of coverage has to be defined by the user, we need to
A way to specify in the language, and SystemVerilog offers this possibility.
Example

How many times has a been equal to 1? Once if we are doing a check
randomly it may happen that the data is not being used once we run it
few times our simulation.

Cross coverage: how many times a was equal to 1 and b was equal to 2.
Thus in System Verilog we can define a covergroup a group that must be
covered and points in this cover points.

[Link]

Bins are containers that can be created for values within a range.
true when we define a data type we know that the range is greater than the
values that will really happen, so I can define 'buckets' to put my values
using for the functional coverage the values that interest me the most

15. Communication and Automation

Edelweis Helena Garcez Ritt 2006

 System Verilog Página19

System Verilog is an event-driven language. Events are disposed of.

automatically like what happens in a sensitivity list. System Verilog also allows
start events manually.
Example:

One can use .triggered to indicate the condition of an event being triggered.

[Link] lights

System Verilog offers infrastructure for semaphores

Imagine the situation of a BFM that can only read or write, that is, a
mutual exclusion situation. Thus, one can define the semaphore in_use in such a way that only
one of the processes will be triggered.

In this way, we can use the same bus.

Edelweis Garcez Ritt

 System Verilog

[Link]

Mailboxes allow asynchronous communication between modules. All the problems

that exist, like FIFO, etc., is automatically made available.

Assertions
As asserções não serão tratadas aqui, pois farão parte de uma aula exclusiva para elas
together with PSL.

17. Using System Verilog as a language for

Verification in VHDL environments

Considerations:
Architecture: The top is System Verilog or VHDL
How we connect the DUT in VHDL in a Testbench in System Verilog

I would have to use a tool that allows you to see (for example, SignalSpy from
mentor).

Edelweis Helena Garcez Ritt 2006

 System Verilog Page21

Edelweis Garcez Ritt