Lecture 8
Combinational Logic with Verilog
Tzung-Je Lee
Fall, 2021
1
Lab: example1 (Gate-Level Code)
◼ Gate-level code
◼ Description the connection of logic gates
◼ The orders of each sentences do not affect the final results.
example1 module example1 (x1, x2, x3, f);
input x1, x2, x3;
x1 g output f;
x2
and (g, x1, x2);
f not (k, x2);
k and (h, k, x3);
h
x3 or (f, g, h);
endmodule
Figure 2.37
Lab: example2 (Gate-Level Code)
◼ example2
example2
x1 z1 module example2 (x1, x2, x3, x4, f, g, h);
x3 input x1, x2, x3, x4;
output f, g, h;
g
x2 and (z1, x1, x3);
z2
x4 and (z2, x2, x4);
or (g, z1, z2);
f
or (z3, x1, ~x3);
z3
or (z4, ~x2, x4);
~x3 and (h, z3, z4);
h or (f, g, h);
~x2
z4 endmodule
Figure 2.38
Exercise 1
◼ Please complete the Verilog code for the following circuit with module
name, problem3_1.
◼ The hand-in word file must include
◼ 1. the Verilog code, and
Problem3_1
x1
x2
x3
Three Way Light Control
◼ Assume that a large room has three doors and that a switch
near each door controls a light in the room. It has to be
possible to turn on or off by changing the state of any one of
the switches.
Sum-of-products:
f = m1 + m2 + m4 + m7
= x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3
Product-of-sums:
f = M0 + M3 + M5 + M6
( )( )(
= (x1 + x2 + x3 ) x1 + x2 + x3 x1 + x2 + x3 x1 + x2 + x3 )
5
Three Way Light Control
◼ Gate-Level module L3_sop (f, x1, x2, x3);
◼ Sum-of-products (SOP) realization input x1, x2, x3;
output f;
L3_sop.v
wire f, x1, x2, x3, w1, w2, w3, w4, w5,
w4
w6, w7;
w1 w5
not(w1, x1);
w2 not(w2, x2);
w3 not(w3, x3);
w6
and(w4, w1, w2, x3);
w7
and(w5, w1, w3, x2);
and(w6, w2, w3, x1);
and(w7, x1, x2, x3);
or(f, w4, w5, w6, w7);
endmodule
6
Three Way Light Control
◼ Gate-Level module L3_pos (f, x1, x2, x3);
◼ Product-of-sums (POS) realization input x1, x2, x3;
output f;
L3_pos.v wire f, x1, x2, x3, w1, w2, w3, w4, w5,
w6, w7;
not(w1, x1);
not(w2, x2);
not(w3, x3);
or(w4, x1, x2, x3);
or(w5, w1, w2, x3);
or(w6, w1, x2, w3);
or(w7, x1, w2, w3);
and(f, w4, w5, w6, w7);
endmodule
7
2-to-1 Multiplexer
◼ A circuit that produces an output that has the same value as
either x1 or x2, dependent on the value of a selection control
signal s.
x1 s
s x1 x2 f (s, x1, x2)
000 0 x1
f 0
001 0 f
s x2 1
010 1
x2
011 1
(b) Circuit (c) Graphical symbol
100 0
101 1 f (s, x1, x2)
s
110 0
0 x1
111 1
1 x2
(a)Truth table
(d) More compact truth-table representation
8
2-to-1 Multiplexer (Gate-Level)
◼ Gate-level code
module Mux21_gate(f, s, x1, x2);
Mux21_gate.v output f;
x1 input s, x1, x2;
wire f, s, x1, x2, x3, w1, w2, w3;
f
s not(w1, s);
x2
and(w2, x1, w1);
(b) Circuit
and(w3, s, x2);
or(f, w2, w3);
endmodule
Figure 2.37
9
2-to-1 Multiplexer (Continuous Assignment)
module Mux21_assign(f, s, x1, x2);
Mux21_assign.v
input x1, x2, s;
x1
output f;
f
s assign f = (x1 & ~s) | (s & x2);
x2
(b) Circuit
endmodule
Figure 2.40
10
2-to-1 Multiplexer
module mux2to1 (w0, w1, s, f);
input w0, w1, s;
output f;
assign f = s ? w1 : w0;
s f
0 w0 endmodule
1 w1
(b) Truth table
Figure 4.23. A 2-to-1 multiplexer specified
using the conditional operator.
11
2-to-1 Multiplexer
◼ always block
◼ All of the input of a combination module mux2to1 (w0, w1, s, f);
circuit should be list in the sensitive input w0, w1, s;
list of the always block. output reg f;
◼ The output in the always block should
always @(w0, w1, s)
be declared to be reg.
f = s ? w1 : w0;
◼ In the always block, the verilog code
execute in order. endmodule
s f
0 w0
Figure 4.24. An alternative specification of a 2-
1 w1
to-1 multiplexer using the conditional operator.
(b) Truth table
12
2-to-1 Multiplexer
module mux2to1 (w0, w1, s, f);
input w0, w1, s;
output reg f;
s f
0 w0 always @(w0, w1, s)
1 w1 if (s==0)
f = w0;
(b) Truth table else
f = w1;
endmodule
Figure 4.26. Code for a 2-to-1 multiplexer using the if-else statement.
13
4-to-1 Multiplexer
s0
s1
w0 00
w1 01 s0
w2 f
10 w0
w3 11 s1
(a) Graphic symbol w1
w2
s 1 s0 f
0 0 w0
0 1 w1
w3
1 0 w2
1 1 w3
(c) Circuit
(b) Truth table
Figure 4.2. A 4-to-1 multiplexer.
14
4-to-1 Multiplexer
module mux4to1 (w0, w1, w2, w3, S, f);
s 1 s0 f
input w0, w1, w2, w3;
0 0 w0
w1
input [1:0] S;
0 1
1 0 w2 output f;
1 1 w3
assign f = S[1] ? (S[0] ? w3 : w2) : (S[0] ? w1 : w0);
(b) Truth table
endmodule
Figure 4.25. A 4-to-1 multiplexer specified using the conditional operator.
15
4-to-1 Multiplexer
module mux4to1 (w0, w1, w2, w3, S, f);
input w0, w1, w2, w3;
input [1:0] S;
s 1 s0 f
output reg f;
0 0 w0
0 1 w1 always @(*)
1 0 w2 if (S == 2'b00)
1 1 w3
f = w0;
(b) Truth table else if (S == 2'b01)
f = w1;
else if (S == 2'b10)
f = w2;
else if (S == 2'b11)
f = w3;
endmodule
Figure 4.27. Code for a 4-to-1 multiplexer using the if-else statement.
16
4-to-1 Multiplexer
module mux4to1 (W, S, f);
input [0:3] W;
input [1:0] S;
output reg f;
s 1 s0 f always @(W, S)
0 0 w0 if (S == 0)
0 1 w1
1 0 w2 f = W[0];
1 1 w3 else if (S == 1)
(b) Truth table
f = W[1];
else if (S == 2)
f = W[2];
else if (S == 3)
f = W[3];
endmodule
Figure 4.28. Alternative specification of a 4-to-1 multiplexer. 17
4-to-1 Multiplexer
module mux4to1 (W, S, f);
input [0:3] W;
input [1:0] S;
output reg f;
always @(W, S)
s 1 s0 f
case (S)
0 0 w0
0 1 w1
0: f = W[0];
1 0 w2 1: f = W[1];
1 1 w3 2: f = W[2];
3: f = W[3];
(b) Truth table
endcase
endmodule
Figure 4.30. A 4-to-1 multiplexer defined using the case statement. 18
16-to-1 Multiplexer
s0
s1
w0
module mux16to1 (W, S, f);
w3
input [0:15] W;
input [3:0] S;
output f;
w4 s2
s3 wire [0:3] M;
w7
mux4to1 Mux1 (W[0:3], S[1:0], M[0]);
f mux4to1 Mux2 (W[4:7], S[1:0], M[1]);
w8
mux4to1 Mux3 (W[8:11], S[1:0], M[2]);
mux4to1 Mux4 (W[12:15], S[1:0], M[3]);
w11 mux4to1 Mux5 (M[0:3], S[3:2], f);
endmodule
w12
w15
Figure 4.4. A 16-to-1 Figure 4.29. Hierarchical code for a
16-to-1 multiplexer. 19
multiplexer.
Exercise
◼ Please complete the 4-to-1 s1
multiplexer using Verilog, s0
which is composed of 3 2-to-1
multiplexer, as shown in Fig. 4.3. w0 0
w1 1
◼ Notably, the Verilog code of the
0
2-to-1 multiplexer must be f
1
compile successful firstly.
w2 0
w3 1
Figure 4.3. Using 2-to-1
multiplexers to build a 4-to-1
multiplexer.
20
21
22
