Chapter 4

Combinational-Circuit
Building Blocks
 s
s f
w0 0 w0
f 0
w1 1 1 w1

(a) Graphical symbol (b) Truth table

w0 w0

s f s

w1 w1 f

(c) Sum-of-products circuit (d) Circuit with transmission gates

Figure 4.1. A 2-to-1 multiplexer.

 s0
s1 s1 s0 f
w0 00 0 0 w0
w1 01 w1
f 0 1
w2 10 w2
1 0
w3 11
1 1 w3

(a) Graphic symbol (b) Truth table

s0
w0
s1

w1

w2

w3

(c) Circuit

Figure 4.2. A 4-to-1 multiplexer.

 s1
s0

w0 0
w1 1

0
f
1

w2 0
w3 1

Figure 4.3. Using 2-to-1 multiplexers to build a 4-to-1 multiplexer.

 s0
s1

w0

w3

w4 s2
s3
w7

w8

w11

w12

w15

Figure 4.4. A 16-to-1 multiplexer.

 s

x1 y1

x2 y2

(a) A 2x2 crossbar switch

x1 0
y1
1

x2 0
y2
1

(b) Implementation using multiplexers

Figure 4.5. A practical application of multiplexers.

 w2
w1 w2 f
w1
0 0 0
0
0 1 1
1
1 f
1 0 1
1 1 0 0

(a) Implementation using a 4-to-1 multiplexer

w1 w2 f
w1 f
w1
0 0 0 w2
0
0 1 1
1 w2 w2
1 0 1 f
1 1 0

(b) Modified truth table (c) Circuit

Figure 4.6. Synthesis of a logic function using multiplexers.

 w1 w2 w3 f
w1 w2 f
0 0 0 0
0 0 0
0 0 1 0 w3
0 1
0 1 0 0 1 0 w3
0 1 1 1 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

(a) Modified truth table

w2
w1

0
w3
f
1
(b) Circuit

Figure 4.7. Implementation of the three-input majority function

using a 4-to-1 multiplexer.
w1 w2 w3 f

0 0 0 0
0 0 1 1 w2
w2 ⊕ w3
0 1 0 1 w1
0 1 1 0 w3
1 0 0 1 f
1 0 1 0
w2 ⊕ w3
1 1 0 0
1 1 1 1

(a) Truth table (b) Circuit

Figure 4.8. Three-input XOR implemented with

2-to-1 multiplexers.
 w1 w2 w3 f

0 0 0 0
w3
0 0 1 1 w2
w1
0 1 0 1
w3
0 1 1 0 w3
1 0 0 1 f
w3
1 0 1 0
1 1 0 0
w3
1 1 1 1

(a) Truth table (b) Circuit

Figure 4.9. Three-input XOR function implemented with

a 4-to-1 multiplexer.
 w1 w2 w3 f

0 0 0 0 w1 f
0 0 1 0 w2w3
0
0 1 0 0
1 w2 + w3
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

(b) Truth table

w1
w2
w3
f

(b) Circuit

Figure 4.10. The three-input majority function implemented

using a 2-to-1 multiplexer.
 w1

f
w3
w2

(a) Using a 2-to-1 multiplexer

w2
w1
w3
f
1

(b) Using a 4-to-1 multiplexer

Figure 4.11. The circuits synthesized in Example 4.5.

 w2 w1

0
w3

Figure 4.12. The circuit synthesized in Example 4.6.

Figure 4.13. A 2-to-4 decoder.
Figure 4.14. Binary decoder.
 w0 w0 y0 y0
w1 w1 y1 y1
y2 y2
w2
En y3 y3

En w0 y0 y4
w1 y1 y5
y2 y6
En y3 y7

Figure 4.15. A 3-to-8 decoder using two 2-to-4 decoders.

 w0 w0 y0 y0
w1 w1 y1 y1
y2 y2
En y3 y3

w0 y0 y4
w1 y1 y5
y2 y6
w2 w0 y0 y3 y7
En
w3 w1 y1
y2
En En y3 w0 y0 y8
w1 y1 y9
y2 y10
En y3 y11

w0 y0 y12
w1 y1 y13
y2 y14
En y3 y15

Figure 4.16. A 4-to-16 decoder built using a decoder tree.

 w0

w1
s0 w0 y0
s1 w1 y1 f
y2 w2
1 En y3

w3

Figure 4.17. A 4-to-1 multiplexer built using a decoder.

 w0
y0
2n n
inputs outputs
yn – 1
w2n – 1

Figure 4.18. A 2n-to-n binary encoder.

 w3 w2 w1 w0 y1 y0

0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

(a) Truth table

w0

w1
y0

w2

y1
w3

(b) Circuit

Figure 4.19. A 4-to-2 binary encoder.

 w3 w2 w1 w0 y1 y0 z

0 0 0 0 d d 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1

Figure 4.20. Truth table for a 4-to-2 priority encoder.

Figure 4.21. A hex-to-7-segment display code converter.
Figure 4.22. A four-bit comparator circuit.
 module mux2to1 (w0, w1, s, f);
input w0, w1, s;
output f;

assign f = s ? w1 : w0;

endmodule

Figure 4.23. A 2-to-1 multiplexer specified using the conditional operator.

 module mux2to1 (w0, w1, s, f);
input w0, w1, s;
output reg f;

always @(w0, w1, s)

f = s ? w1 : w0;

endmodule

Figure 4.24. An alternative specification of a 2-to-1 multiplexer

using the conditional operator.
 module mux4to1 (w0, w1, w2, w3, S, f);
input w0, w1, w2, w3;
input [1:0] S;
output f;

assign f = S[1] ? (S[0] ? w3 : w2) : (S[0] ? w1 : w0);

endmodule

Figure 4.25. A 4-to-1 multiplexer specified using the conditional operator.

 module mux2to1 (w0, w1, s, f);
input w0, w1, s;
output reg f;

always @(w0, w1, s)

if (s==0)
f = w0;
else
f = w1;

endmodule

Figure 4.26. Code for a 2-to-1 multiplexer using the if-else statement.
 module mux4to1 (w0, w1, w2, w3, S, f);
input w0, w1, w2, w3;
input [1:0] S;
output reg f;

always @(*)
if (S == 2'b00)
f = w0;
else if (S == 2'b01)
f = w1;
else if (S == 2'b10)
f = w2;
else if (S == 2'b11)
f = w3;

endmodule

Figure 4.27. Code for a 4-to-1 multiplexer using the if-else statement.
 module mux4to1 (W, S, f);
input [0:3] W;
input [1:0] S;
output reg f;

always @(W, S)
if (S == 0)
f = W[0];
else if (S == 1)
f = W[1];
else if (S == 2)
f = W[2];
else if (S == 3)
f = W[3];

endmodule

Figure 4.28. Alternative specification of a 4-to-1 multiplexer.

 module mux16to1 (W, S, f);
input [0:15] W;
input [3:0] S;
output f;
wire [0:3] M;

mux4to1 Mux1 (W[0:3], S[1:0], M[0]);

mux4to1 Mux2 (W[4:7], S[1:0], M[1]);
mux4to1 Mux3 (W[8:11], S[1:0], M[2]);
mux4to1 Mux4 (W[12:15], S[1:0], M[3]);
mux4to1 Mux5 (M[0:3], S[3:2], f);

endmodule

Figure 4.29. Hierarchical code for a 16-to-1 multiplexer.

 module mux4to1 (W, S, f);
input [0:3] W;
input [1:0] S;
output reg f;

always @(W, S)
case (S)
0: f = W[0];
1: f = W[1];
2: f = W[2];
3: f = W[3];
endcase

endmodule

Figure 4.30. A 4-to-1 multiplexer defined using the case statement.

 module dec2to4 (W, En, Y);
input [1:0] W;
input En;
output reg [0:3] Y;

always @(W, En)

case ({En, W})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase

endmodule

Figure 4.31. Verilog code for a 2-to-4 binary decoder.

 module dec2to4 (W, En, Y);
input [1:0] W;
input En;
output reg [0:3] Y;

always @(W, En)

begin
if (En == 0)
Y = 4'b0000;
else
case (W)
0: Y = 4'b1000;
1: Y = 4'b0100;
2: Y = 4'b0010;
3: Y = 4'b0001;
endcase
end

endmodule

Figure 4.32. Alternative code for a 2-to4 binary decoder.

module dec4to16 (W, En, Y);
input [3:0] W;
input En;
output [0:15] Y;
wire [0:3] M;

dec2to4 Dec1 (W[3:2], M[0:3], En);

dec2to4 Dec2 (W[1:0], Y[0:3], M[0]);
dec2to4 Dec3 (W[1:0], Y[4:7], M[1]);
dec2to4 Dec4 (W[1:0], Y[8:11], M[2]);
dec2to4 Dec5 (W[1:0], Y[12:15], M[3]);

endmodule

Figure 4.33. Verilog code for a 4-to-16 decoder.

Figure 4.34. Code for a hex-to-7-segment decoder.
Table 4.1. The functionality of the 74381 ALU.
 // 74381 ALU
module alu(s, A, B, F);
input [2:0] S;
input [3:0] A, B;
output reg [3:0] F;

always @(S, A, B)
case (S)
0: F = 4'b0000;
1: F = B - A;
2: F = A - B;
3: F = A + B;
4: F = A ^ B;
5: F = A | B;
6: F = A & B;
7: F = 4'b1111;
endcase

endmodule

Figure 4.35. Code that represents the functionality of the 74381 ALU chip.
 module priority (W, Y, z);
input [3:0] W;
output reg [1:0] Y;
output reg z;

always @(W)
begin
z = 1;
casex (W)
4'b1xxx: Y = 3;
4'b01xx: Y = 2;
4'b001x: Y = 1;
4'b0001: Y = 0;
default: begin
z = 0;
Y = 2'bx;
end
endcase
end

endmodule

Figure 4.36. Verilog code for a priority encoder.

 module dec2to4 (W, En, Y);
input [1:0] W;
input En;
output reg [0:3] Y;
integer k;

always @(W, En)

for (k = 0; k <= 3; k = k+1)
if ((W == k) && (En == 1))
Y[k] = 1;
else
Y[k] = 0;

endmodule

Figure 4.37. A 2-to-4 binary decoder specified using the for loop.
 module priority (W, Y, z);
input [3:0] W;
output reg [1:0] Y;
output reg z;
integer k;

always @(W)
begin
Y = 2'bx;
z = 0;
for (k = 0; k < 4; k = k+1)
if (W[k])
begin
Y = k;
z = 1;
end
end

endmodule

Figure 4.38. A priority encoder specified using the for loop.

& 0 1 x j 0 1 x

0 0 0 0 0 0 1 x
1 0 1 x 1 1 1 1
x 0 x x x x 1 x

^ 0 1 x ~^ 0 1 x

0 0 1 x 0 1 0 x
1 1 0 x 1 0 1 x
x x x x x x x x

Figure 4.39. Truth tables for bitwise operators.

 module compare (A, B, AeqB, AgtB, AltB);
input [3:0] A, B;
output reg AeqB, AgtB, AltB;

always @(A, B)
begin
AeqB = 0;
AgtB = 0;
AltB = 0;
if(A == B)
AeqB = 1;
else if (A > B)
AgtB = 1;
else
AltB = 1;
end

endmodule

Figure 4.40. Verilog code for a four-bit comparator.

Table 4.3. Precedence of Verilog operators.
 module addern (carryin, X, Y, S, carryout);
parameter n=32;
input carryin;
input [n-1:0] X, Y;
output [n-1:0] S;
output carryout;
wire [n:0] C;

genvar k;
assign C[0] = carryin;
assign carryout = C[n];
generate
for (k = 0; k < n; k = k+1)
begin: fulladd_stage
wire z1, z2, z3; //wires within full-adder
xor (S[k], X[k], Y[k], C[k]);
and (z1, X[k], Y[k]);
and (z2, X[k], C[k]);
and (z3, Y[k], C[k]);
or (C[k+1], z1, z2, z3);
end
endgenerate

endmodule

Figure 4.41. Using the generate loop to define an n-bit ripple-carry adder.
Figure 4.42. Use of a task in Verilog code.
Figure 4.43. The code from Figure 4.42 using a function.
w3 w0 y0
w2 w1 y1
w1 w2 y2
y3
y4
y5
y6
1 En y7

Figure 4.44. Circuit for Example 4.24.

Figure 4.45. Truth table for an 8-to-3 binary encoder.
Figure 4.46. Circuit for Example 4.26.
Figure 4.47. Binary to Gray code conversion.
Figure 4.48.
Circuits for Example 4.28.
Figure 4.49.
Circuits for Example 4.29.
Figure 4.50. A shifter circuit.
Figure 4.51. A barrel shifter circuit.
module mux4to1 (W, S, f);
input [0:3] W;
input [1:0] S;
output f;
wire [0:3] Y;

dec2to4 decoder (S, 1, Y);

assign f = |(W & Y);
endmodule

module dec2to4 (W, En, Y);

input [1:0] W;
input En;
output reg [0:3] Y;

always @(W, En)

case ({En, W})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
endmodule
Figure 4.52. Verilog code for Example 4.32.
 module shifter (W, Shift, Y , k);
input [3:0] W;
input Shift;
output reg [3:0] Y;
output reg k;

always @(W, Shift)

begin
if (Shift)
begin
Y[3] = 0;
Y[2:0] = W[3:1];
k = W[0];
end
else
begin
Y = W;
k = 0;
end
end

endmodule

Figure 4.53. Verilog code for the circuit in Figure 4.50.

 module shifter (W, Shift, Y , k);
input [3:0] W;
input Shift;
output reg [3:0] Y;
output reg k;

always @(W, Shift)

begin
if (Shift)
begin
Y = W >> 1;
k = W[0];
end
else
begin
Y = W;
k = 0;
end
end

endmodule

Figure 4.54. Alternative Verilog code for the circuit in Figure 4.50.
 module barrel (W, S, Y);
input [3:0] W;
input [1:0] S;
output [3:0] Y;
wire [3:0] T;

assign {T, Y} = {W, W} >> S;

endmodule

Figure 4.55. Verilog code for the barrel shifter.

 module parity (X, Y);
input [7:0] X;
output [7:0] Y;

assign Y = {^X[6:0], X[6:0]};

endmodule

Figure 4.56. Verilog code for Example 4.35.

 i1
i2
3
i

i4
i5

i6 f

i7
i8

Figure P4.1. A multiplexer-based circuit.

module problem4_18 (W, En, y0, y1, y2, y3) ;
input [1:0] W;
input En;
output reg y0, y1, y2, y3;

always @ (W, En)

begin
y0 = 0;
y1 = 0;
y2 = 0;
y3 = 0;
if (En)
if (W = = 0) y 0 = 1;
else if (W = = 1) y1 = 1;
else if (W = = 2) y2 = 1;
else y3 = 1;
end

endmodule

Figure P4.2. Code for Problem 4.18.

module dec2to4(W, En, Y);
input [1:0] W;
input En;
output reg [0:3] Y;
integer k;

always @(W, En)

for (k = 0; k <= 3; k = k+1)
if (W == k)
Y[k] = En;

endmodule

Figure P4.3. Code for problem 4.22.