The document describes designing, simulating, and implementing various digital logic circuits using Verilog HDL and FPGA. It includes tasks to simulate and synthesize a 4-bit 4x1 multiplexer, 2-bit 4x1 multiplexer, 1-bit 8-way demultiplexer, 3x8 decoder, and a 4x16 decoder using two 3x8 decoders and additional enable logic. The tasks provide Verilog code, testbenches, simulation waveforms, and screenshots of the implemented designs on FPGA.
The document describes designing, simulating, and implementing various digital logic circuits using Verilog HDL and FPGA. It includes tasks to simulate and synthesize a 4-bit 4x1 multiplexer, 2-bit 4x1 multiplexer, 1-bit 8-way demultiplexer, 3x8 decoder, and a 4x16 decoder using two 3x8 decoders and additional enable logic. The tasks provide Verilog code, testbenches, simulation waveforms, and screenshots of the implemented designs on FPGA.
The document describes designing, simulating, and implementing various digital logic circuits using Verilog HDL and FPGA. It includes tasks to simulate and synthesize a 4-bit 4x1 multiplexer, 2-bit 4x1 multiplexer, 1-bit 8-way demultiplexer, 3x8 decoder, and a 4x16 decoder using two 3x8 decoders and additional enable logic. The tasks provide Verilog code, testbenches, simulation waveforms, and screenshots of the implemented designs on FPGA.
The document describes designing, simulating, and implementing various digital logic circuits using Verilog HDL and FPGA. It includes tasks to simulate and synthesize a 4-bit 4x1 multiplexer, 2-bit 4x1 multiplexer, 1-bit 8-way demultiplexer, 3x8 decoder, and a 4x16 decoder using two 3x8 decoders and additional enable logic. The tasks provide Verilog code, testbenches, simulation waveforms, and screenshots of the implemented designs on FPGA.
Dated; 18/07/2023 Objective: Designing, Simulating and Implementing the HDL code for 4-bit 4x1 Mux, 2-bit 4x1 Mux, 1-bit 1x8 Demultiplexer, 3x8 Decoder, and 4x16 decoder using two 3x8 decoder and additional logic (Enable)
Procedure: 1. Writing the Source Code of module and simulating it 2. Opening Elaborated Design 3. Setting Constraints 4. Running Synthesis 5. After Successful Synthesis Running Implementation 6. After Successful Implementation Generating Bit Stream 7. Downloading Bit Stream to FPGA kit using Hardware Manager Apparatus List: • Verilog HDL • FPGA Development Board • Xilinx Vivado or any other Verilog simulation and synthesis tool
TASK 1: Verilog Code for 4-bit 4x1 Mux and simulate it only.
• A 4-bit 4x1 mux will have 4 inputs, 4-bit each, and a 4- bit output with 2 bits select line. Mux will select 1 of 4 inputs on the basis of select line.
• 2-bit 4x1 mux will have 4 inputs, 2-bit each, and a 2-bit output and with 2 bits select line. Mux will select 1 of 4 inputs because of select line. Results are verified through implementation on FPGA Kit.
• One common input line of 1x8 demux will be switched to one of the 8 output lines according to select bits. Results are verified on FPGA Kit.
• 3x8 decoder works on the basis of 3 inputs which are used to select one of 8 outputs. • When two 3 to 8 Decoder circuits are combined to make a 4x16 decoder, the enable pin acts as the input for both the decoders. When enable pin is high at one 3 to 8 decoder circuits then it is low at another 3 to 8 decoder circuit. Results are verified on Kit.
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