HDL LAB (18ECL58)

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HDL LAB (18ECL58)

1. a) Write Verilog program for 2 to 4 decoder and realize using NAND gates only
(structural model). Write a test bench to verify the design.

//Main module
module dec(a,b,e,D);
input a,b;
output [3:0]D;
input e;
wire w1,w2,w3,w4,w5,w6;
nand2 n1(a,a,ac);
nand2 ///////////////////////
//////////////////////////////////
//////////////////////////////////
//////////////////////////////////
//////////////////////////
6n2(b,b,w2); nand3
n3(w1,w2,e,w3); nand3
n4(w1,b,e,w4);
nand3 n5(a,w2,e,w5);
nand3 n6(a,b,e,w6);
nand2 n7(w3,w3,D[0]);
nand2 n8(w4,w4,D[1]);
nand2 n9(w5,w5,D[2]);
nand2 n10(w6,w6,D[3]);
endmodule

//2-input nand gate

module nand2(a,b,c);
input a,b;
output c;
wire y;
and(y,a,b);
not(c,y);
endmodule

//3-input nand gate module

module nand3(a,b,c,d);
input a,b,c;
output d;
wire y;
and(y,a,b,c);
not(d,y);
endmodule

// Test bench module

module stimulus();
reg a,b,e;
wire [3:0]D;

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HDL LAB (18ECL58)

dec dl(a,b,e,D);
initial
begin
a=1'b0;b=1'b0;e=1'b0;#10 a=1'b0;b=1'b0;e=1'b1;
#10 a=1'b0;b=1'b1;e=1'b1;#10 a=1'b1;b=1'b0;e=1'b1;

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HDL LAB (18ECL58)

#10 a=1'b1;b=1'b1;e=1'b1;#10 a=1'b1;b=1'b1;e=1'b0;

#10 $finish;
end
endmodule

Block Diagram: RTL Schematic:

Truth Table:

ENABLE INPUT LINES OUTPUT LINES

e A B D[3] D[2] D[1] D[0]
0 0 0 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

Waveform

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HDL LAB (18ECL58)

1. b) Write Verilog program 8 to 3 encoder without priority (behavioral model). Write a test
bench to verify the design.

// Main module
module encoder8_3(A, Y);
input [7:0] A;
output [2:0] Y;
reg [2:0] Y;
always @(A)
begin
case (A)
8'b10000000:Y=3'd7;
8'b01000000:Y=3'd6;
8'b00100000:Y=3'd5;
8'b00010000:Y=3'd4;
8'b00001000:Y=3'd3;
8'b00000100:Y=3'd2;
8'b00000010:Y=3'd1;
8'b00000001:Y=3'd0;
default:Y=3'bXXX;
endcase
end
endmodule

// Test bench module

module stimulus();
reg [7:0]A;
wire [2:0]Y;
encoder8_3 e1(A,Y);
initial
begin
A=8'b00000000;
#10 A=8'b00000001;
#10 A=8'b00000010;
#10 A=8'b00000100;
#10 A=8'b00001000;
#10 A=8'b00010000;
#10 A=8'b00100000;
#10 A=8'b01000000;
#10 A=8'b10000000;
#10 $finish;
end
endmodule

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HDL LAB (18ECL58)

Block Diagram: RTL Schematic:

A[7:0] 8:3 Encoder Y[2:0]

Truth Table:
INPUTS OUTPUTS
A7 A6 A5 A4 A3 A2 A1 A0 Y2 Y1 Y0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
0 0 0 0 0 0 0 0 X X X

Waveform:

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HDL LAB (18ECL58)

Write Verilog program 8 to 3 encoder with priority (behavioral model). Write a test bench to
verify the design.

// Main module
module enco_p_8_3(A, valid, y);
input [7:0] A;
output valid;
output [2:0]y;
reg valid;
reg [2:0]y;
always @(A)
begin
valid = 1;
if (A[7] ==1)y = 3'd7;
else if (A[6] ==1)y = 3'd6;
else if (A[5] ==1)y = 3'd5;
else if (A[4] ==1)y = 3'd4;
else if (A[3] ==1)y = 3'd3;
else if (A[2] ==1)y = 3'd2;
else if (A[1] ==1)y = 3'd1;
else if (A[0] ==1)y = 3'd0;
else
begin
valid = 0;
y = 3'bXXX;
end
end
endmodule

// Test bench module

module stimulus();
reg [7:0]A;
wire valid;
wire [2:0]Y;
enco_p_8_3 e1(A,valid,Y);
initial
begin
A=8'b00000000;
#10 A=8'b00000001;
#10 A=8'b0000001X;
#10 A=8'b000001XX;
#10 A=8'b00001XXX;
#10 A=8'b0001XXXX;
#10 A=8'b001XXXXX;
#10 A=8'b01XXXXXX;
#10 A=8'b1XXXXXXX;
#10 A=8'b011XXXXX;
#10 $finish;
end
endmodule

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HDL LAB (18ECL58)

Block Diagram: RTL Schematic:

Truth Table:

INPUTS OUTPUTS
A7 A6 A5 A4 A3 A2 A1 A0 Y2 Y1 Y0 Valid
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 X 0 0 1 1
0 0 0 0 0 1 X X 0 1 0 1
0 0 0 0 1 X X X 0 1 1 1
0 0 0 1 X X X X 1 0 0 1
0 0 1 X X X X X 1 0 1 1
0 1 X X X X X X 1 1 0 1
1 X X X X X X X 1 1 1 1
0 0 0 0 0 0 0 0 X X X 0

Waveform:

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HDL LAB (18ECL58)

1. c) Write Verilog program for 8 to 1 multiplexer using case statement. Write a test
bench to verify the design.

// Main module

module mux8_1(sel,a,muxout);
input [2:0] sel;
input [7:0] a;
output muxout;
reg muxout;
always @(sel,a)
begin
case(sel)
3'd0: muxout = a[0];
3'd1: muxout = a[1];
3'd2: muxout = a[2];
3'd3: muxout = a[3];
3'd4: muxout = a[4];
3'd5: muxout = a[5];
3'd6: muxout = a[6];
3'd7: muxout = a[7];
default:;
endcase
end
endmodule

// Test bench module

module stimulus();
reg [2:0]sel;
reg [7:0]a;
wire muxout;
mux8_1 m1 (sel,a,muxout);
initial
begin
a=8'b00000000;
#10 a=8'b00000001;sel=3'b000;
#10 a=8'b00000010;sel=3'b001;
#10 a=8'b00000100;sel=3'b010;
#10 a=8'b00001000;sel=3'b011;
#10 a=8'b00010000;sel=3'b100;
#10 a=8'b00100000;sel=3'b101;
#10 a=8'b01000000;sel=3'b110;
#10 a=8'b10000000;sel=3'b111;
#10 $finish;
end

endmodule

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HDL LAB (18ECL58)

Block Diagram: RTL Schematic:

a[7:0] muxout
8:1 MUX

sel0 sel1 sel2

Truth Table:

SELECT DATA INPUTS OUTPUTS

sel2 sel1 sel0 muxout
0 0 0 a
0 0 1 b
0 1 0 c
0 1 1 d
1 0 0 e
1 0 1 f
1 1 0 g
1 1 1 h

Waveform:

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HDL LAB (18ECL58)

Write Verilog program for 8 to 1 multiplexer using if statement. Write a test bench to verify
the design.

// Main module
module mux(A,s1,s2,s3,,y);
input [7:0] A;
input s1,s2,s3;
output y;
reg y;
always @(A,s1,s2,s3)
begin
if ((s1 ==0)&&(s2==0)&&(s3==0))y = A[0];
else if ((s1 ==1)&&(s2==0)&&(s3==0))y =
A[1]; else if ((s1 ==0)&&(s2==1)&&(s3==0))y =
A[2]; else if ((s1 ==1)&&(s2==1)&&(s3==0))y =
A[3]; else if ((s1 ==0)&&(s2==0)&&(s3==1))y =
A[4]; else if ((s1 ==1)&&(s2==0)&&(s3==1))y =
A[5]; else if ((s1 ==0)&&(s2==1)&&(s3==1))y =
A[6]; else if ((s1 ==1)&&(s2==1)&&(s3==1))y =
A[7]; else
begin
d = 1’bz;
end
end
endmodule

// Test bench module

module stimulus();
reg s1,s2,s3;
reg [7:0]a;
wire y;
mux m1 ( a,s1,s2,s3,y);
initial
begin
a=8'b00000000;
#10 a=8'b00000001; {s3,s2,s1}=3'b000;
//#10 a=8’b00000000; {s3,s2,s1}=3’b000;
#10 a=8'b00000010; {s3,s2,s1}= 3'b001;
//#10 a=8’b00000000; {s3,s2,s1}=3’b001;
#10 a=8'b00000100; {s3,s2,s1}=3'b010;
#10 a=8'b00001000; {s3,s2,s1}= 3'b011;
#10 a=8'b00010000; {s3,s2,s1}= 3'b100;
#10 a=8'b00100000; {s3,s2,s1}= 3'b101;
#10 a=8'b01000000; {s3,s2,s1}= 3'b110;
#10 a=8'b10000000; {s3,s2,s1}= 3'b111;
#10 $finish;
end
endmodule

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HDL LAB (18ECL58)

1.d) Write Verilog program for 4-bit binary to gray converter using 1-bit gray to binary
converter 1-bit adder and Subtractor. Write a test bench to verify the design.

//Main module
module BG(B,G);
output [3:0]G;
input [3:0]B;
assign G[3]=B[3];
Gray_bin_1 x1(G[2],G[3],B[2]);
Fulladder_1 x2(G[1], ,1'b0,B[2],B[1]);
Subtractor_1 x3(G[0], ,1'b0,B[1], B[0]);
endmodule

//Module for 1 bit G 2 B

module Gray_bin_1(b0,g1,g0);
output b0;
input g0,g1;
assign b0= g0 ^ g1;
endmodule

//Module for 1 bit Adder

module Fulladder_1 (sum,cout, a, b, c);
output sum, cout;
input a, b,c;
assign sum= a ^ b ^ c;
assign cout= (a & b) | (b & c) | (c & a);
endmodule

//Module for 1 bit Subtractor

module Subtractor_1 (diff,bout, a, b, c);
output diff, bout;
input a, b,c;
assign diff= a ^ b ^ c;
assign bout= ((~a) & b) | ((((~a) | b)) & c);
endmodule

//Test Bench module

module stimulus();
reg[3:0]B;
wire[3:0]G;
BG bg(B,G);
initial
begin
B=4'h0;
#10 B=4'h1; #10B=4'h3;
#10 B=4'h7; #10B=4'h9;
#10 B=4'hf; #10B=4'ha;
#10 $finish;

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HDL LAB (18ECL58)

end
endmodule

Block Diagram: RTL Schematic:

Truth Table:
BINARY GRAY
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Waveform

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HDL LAB (18ECL58)

2. Model in Verilog for a full adder and add functionality to perform logical operations of
XOR, XNOR, AND and OR gates. Write test bench with appropriate input patterns to
verify the modeled behaviour.

// Main module
module fulladd(sum,cout,yxor,yxnor,yand,yor,a,b,c);
output sum,cout,yxor,yxnor,yand,yor;
input a,b,c;
assign sum = a^b^c;
assign cout = (a&b)|(b&c)|(c&a);
assign yxor = a^b^c;
assign yxnor = ~(a^b^c);
assign yand = a&b&c;
assign yor = a|b|c;
endmodule

// Test bench module

module stimulus();
wire sum,cout,yxor,yxnor,yand,yor;
reg a,b,c;
fulladd g(sum,cout,yxor,yxnor,yand,yor,a,b,c);
task display;
begin
$display (" a= ",a," b= ",b, "c=",c,"sum = " ,sum, "cout =", cout,
" yxor= ",yxor," yxnor= ",yxnor, "yand = ",yand, " yor = ",yor);
end
endtask
initial
begin
a=1'b0;b=1'b0;c=1'b0;#5;display;
a=1'b0;b=1'b0;c=1'b1;#5;display;
a=1'b1;b=1'b1;c=1'b0;#5;display;
a=1'b1;b=1'b1;c=1'b1;#5;display;
a=1'b1;b=1'b0;c=1'b0;#5;display;
a=1'b1;b=1'b0;c=1'b1;#5;display;
a=1'b1;b=1'b1;c=1'b0;#5;display;
a=1'b1;b=1'b1;c=1'b1;#5;display;
end
endmodule

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HDL LAB (18ECL58)

Block Diagram: RTL Schematic:

Truth Table:
INPUTS OUTPUTS
A B C ANDG ORG XORG XNORG SUM COUT
0 0 0 0 0 0 1 0 0
0 0 1 0 1 1 0 1 0
`0 1 0 0 1 1 0 1 0
0 1 1 0 1 1 0 1 1
1 0 0 0 1 1 0 1 0
1 0 1 0 1 1 0 0 1
1 1 0 0 1 1 0 0 1
1 1 1 1 1 0 1 1 1

Waveform:

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HDL LAB (18ECL58)

3. Verilog 32-bit ALU shown in figure below and verify the functionality of ALU by
selecting appropriate test patterns. The functionality of the ALU is presented in Table-1.

a. Write test bench to verify the functionality of the ALU considering

all possible input patterns
b. The enable signal will set the output to required functions
if enabled, if disabled all the outputs are set to tri-state
c. The acknowledge signal is set high after every operation is
completed

Op code ALU
Operation Remarks
(2:0)
Addition of two Both A and B are in two’s
000 A+B
numbers complement format

001 A–B Subtraction of two numbers

A is in two’s
010 A+1 Increment Accumulator by 1 complement format
Decrement accumulator by
011 A-1
1
Inputs can be in any
100 A True format
101 A Complement Complement

110 A OR B Logical OR

111 A AND B Logical AND

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HDL LAB (18ECL58)

// Main module
module alu(Result, A, B, opcode, Enable);
output [7:0] Result;
input signed[3:0] A, B;
input [2:0] opcode;
input Enable;
reg [7:0] Result;
always@(opcode,A,B,Enable)
begi
n if (Enable==0)

begin Result=8'bx;

end

else
begin
case(opcode)
3'b000: begin Result=A+B; end
3'b001: begin Result=A-B; end
3'b010: begin Result=A+1; end
3'b011: begin Result=A-1; end
3'b100: begin Result=!A; end
3'b101: begin Result=~A; end
3'b110: begin Result=A|B; end
3'b111: begin Result=A&B; end
endcase
end
end
endmodule

// Test bench module

module stimulus();
reg [2:0]opcode;
reg [3:0] a,b;
reg Enable;
wire [7:0]Result;
alu m1 (Result, a, b, opcode, Enable);
initial
begin
a=4'b0000; b=4'b0000; Enable =1'b0;
#10 Enable=1'b1; a=4'b1000; b=4'b1111; opcode=3'b000;
#10 Enable=1'b1; a=4'b1000; b=4'b1111; opcode=3'b001;
#10 Enable=1'b1; a=4'b1000; b=4'b1111; opcode=3'b010;
#10 Enable=1'b1; a=4'b1000; b=4'b1111; opcode=3'b011;
#10 Enable=1'b1; a=4'b1000; b=4'b1111; opcode=3'b100;
#10 Enable=1'b1; a=4'b1000; b=4'b1111; opcode=3'b101;
#10 Enable=1'b1; a=4'b1000; b=4'b1111; opcode=3'b110;
#10 Enable=1'b1; a=4'b1000; b=4'b1111; opcode=3'b111;
#10 $finish;
end
endmodule

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HDL LAB (18ECL58)

Block Diagram: RTL Schematic:

Truth Table:

Operation sel a b y
a+b 000 1111 0000 00001111
a-b 001 1110 0010 00001100
a or b 010 1111 1000 00001111
a and b 011 1001 1000 00001000
not a 100 1111 0000 11110000
a*b 101 1111 1111 11100001
a nand b 110 1111 0010 11111101
a xor b 111 0000 0100 00000100

Waveform:

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HDL LAB (18ECL58)

4. Write a Verilog code to simulate and synthesize D flip-flop and demonstrate the
operation.

// Main module
module dff( d, clk,rst, q, q_bar);
input d, clk, rst;
output reg q, q_bar;

always @ (posedge clk or negedge rst)

begin
if(!rst)
begin
q <= 1'b0;
q_bar<=1'b1;
end
else
begin
q <= d;
q_bar <= !d;
end
end
endmodule

//Test bench module

module dff_test;
reg d,rst,clk;
wire q,qbar;

// Instantiate the D-flipflop

dff d1 (.d(d),.clk(clk),.rst(rst), .q(q), .q_bar(q_bar));

task display;
begin
$display("time=%0d",$time,"ns",
" n_rst=",rst," din=",d," q=",q," q_bar=",q_bar);
end
endtask
initial
begin
d = 0;
clk = 0;
end
// Generating clock signal
always
#5 clk = ~clk;

// Add stimulus here

initial
begin
rst=1'b0;d=1'b1;#10;display;
rst=1'b1;d=1'b1;#10;display;
d=1'b0;#10;display;
d=1'b1;#10;display;
rst=1'b0;d=1'b1;#10; display;

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HDL LAB (18ECL58)

rst=1'b1;d=1'b1;#10;display;
end
endmodule

Block Diagram: RTL Schematic:

Truth Table:

Inputs Outputs
CLK RESET D Q Ǭb
1 1 1 1 0
1 1 0 0 1
X 0 X 0 1

Waveform:

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HDL LAB (18ECL58)

5. Write a Verilog code to simulate and synthesize SR flip-flop and Demonstrate the
operation.

//Main module
module srff(q,qbar,s,r,clk,rst);
output q,qbar;
input clk,rst,s,r;
reg q;
always @(posedge clk or negedge rst)
begin
if (!rst)
q <= 1'b0;

else if (s == 1'b0 && r == 1'b0)

q <= q;
else if (s == 1'b0 && r == 1'b1)
q <= 1'b0;
else if (s == 1'b1 && r == 1'b0)
q <= 1'b1;
else if (s == 1'b1 && r == 1'b1)
q <= 1'bx;
end
assign q = tq;
assign qbar = ~q;
endmodule

// Testbench module
module sr_ff_test;
reg clk,rst,s,r;
wire q,qbar;

srff sr1(q,qbar,s,r,clk,rst);

task display;
begin
$display("time=%0d",$time,"ns"," rst=",rst," s=",s," r=",r," q=",q," qbar=",qbar);
end
endtask

initial
clk = 1'b0;
always
#5 clk = ~clk;

initial
begin
rst=0;s=1;r=0;#10;display;
rst=1;s=1;r=0;#10;display;
s=0;r=0;#10;display;
s=0;r=1;#10;display;
s=1;r=1;#10;display;
end
initial
#70 $finish;
endmodule

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HDL LAB (18ECL58)

Block Diagram: RTL Schematic:

Truth Table:

Inputs Outputs
CLK RESET S R Q Ǭb
X 0 X X 0 1
X 1 X X 1 0
1 1 0 0 Q Qb
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 X X

Waveform:

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 HDL LAB (18ECL58)

6. Write a Verilog code to simulate and synthesize JK flip-flop and demonstrate the
operation.

// Main module
module jkff(q,qbar,clk,rst,j,k);
input clk,rst,j,k;
output q,qbar;
reg q;
always @(posedge clk or negedge rst)
begi
n if (!rst)
begin
q <= 1'b0;
end
else begin
if (j == 1'b1 && k == 1'b0)
begin
q <=1'b1;
end
else if (j == 1'b0 && k == 1'b1)
begin
q <=1'b0 ;
end
else if (j == 1'b1 && k == 1'b1)
begin
q <=~q;
end
end
end
assign qbar=~q;
endmodule

// Testbench module
module jk_ff_test;
reg clk,rst,j,k;
wire q,qbar;
jkff inst(q,qbar,clk,rst,j,k);
task display;
begin
$display("time=%0d",$time,"ns"," rst=",rst," j=",j," k=",k," q=",q," qbar=",qbar);
end
endtask
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
rst=0;j=1;k=0;#10; display;
rst=1;j=1;k=0;#10; display;
j=0;k=0;#10; display;
j=0;k=1;#10; display;
j=1;k=1;#10; display;
j=1;k=1;#10; display;
#10;
Dept. of ECE, Govt. SKSJTI Page 23
HDL LAB (18ECL58)

end
initial
#70 $finish;
endmodule

Block Diagram: RTL Schematic:

Truth Table:
Inputs Outputs
CLK RESET J K Q Qb
X 0 X X Previous State
1 1 0 0 Q NC
1 1 0 1 0 Reset
1 1 1 0 1 Set
1 1 1 1 Toggle

Waveform:

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HDL LAB (18ECL58)

7. Write a Verilog code to simulate and synthesize Binary Counter with Synchronous reset
and demonstrate the operation.

//Main module

module sync(count,reset,clk);
input wire reset, clk;
output reg [3:0] count;
always @(posedge clk)
if (reset)
count <= 4'b0000;
else
count <= count + 4'b0001;
endmodule

// Test bench module

module sycounter_t ;
wire [3:0] count;
reg reset,clk;
sync m1 ( count,reset,clk);
initial
clk = 1'b0;

always
#5 clk = ~clk;

initial
begin
#10; reset = 1'b1 ;
#10; reset = 1'b0 ;
#10; reset = 1'b1 ;
#10; reset = 1'b0 ;
#200 $finish;
end

initial
$monitor ($time, "Output count = %d ",count );

endmodule

Dept. of ECE, Govt. SKSJTI Page 25

HDL LAB (18ECL58)

Block Diagram: RTL Schematic:

Truth Table:

Clock Pulse Reset Q3 Q2 Q1 Q0

X 1 0 0 0 0
1 0 0 0 0 1
1 0 0 0 1 0
1 0 0 0 1 1
1 0 0 1 0 0
1 0 0 1 0 1
1 0 0 1 1 0
1 0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 0 1
1 0 1 0 1 0
1 0 1 0 1 1
1 0 1 1 0 0
1 0 1 1 0 1
1 0 1 1 1 0
1 0 1 1 1 1

Waveform:

Dept. of ECE, Govt. SKSJTI Page 26

HDL LAB (18ECL58)

8. Write a Verilog code to simulate and synthesize 4 Bit BCD Counter and demonstrate the
operation.

// Main module
module BCD(count,reset,clk);
input wire reset, clk;
output reg [3:0] count;
initial
count[3:0]=4'b0000;
always @(posedge clk)
begin
if ((reset ==1)|(count==4'b1001))
count =4'b0000;
else
count = count + 4'b0001;
end
endmodule

// Test bench module

module BCD_t ;
wire [3:0] count;
reg reset,clk;
BCD m1 ( count,reset,clk);
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
#10; reset = 1'b1 ;
#10; reset = 1'b0 ;
#10; reset = 1'b1 ;
#10; reset = 1'b0 ;
#200 $finish;
end
initial
$monitor ($time, "Output count = %d ",count );
endmodule

Dept. of ECE, Govt. SKSJTI Page 27

HDL LAB (18ECL58)

Block Diagram: RTL Schematic:

Truth Table:

Clock Pulse Reset Q3 Q2 Q1 Q0

X 1 0 0 0 0
1 0 0 0 0 1
2 0 0 0 1 0
3 0 0 0 1 1
4 0 0 1 0 0
5 0 0 1 0 1
6 0 0 1 1 0
7 0 0 1 1 1
8 0 1 0 0 0
9 0 1 0 0 1
10 0 0 0 0 0

Waveform:

Dept. of ECE, Govt. SKSJTI Page 28

HDL LAB (18ECL58)

9. Write Verilog code for counter with given input clock and check whether it works as
clock divider performing division of clock by 2, 4, 8 and 16. Verify the functionality of the
code.

// Main module
module freq_div(clk_2,clk_4,clk_8,clk_16,reset,clk);
input wire reset, clk;
output reg clk_2,clk_4,clk_8,clk_16;
reg [3:0]count;
initial
count[3:0]=4'b0000;
always @(posedge clk)
begin
if (reset ==1)
begin count =4'b0000; end
else
begin count = count + 4'b0001;end

clk_2=count[0];
clk_4=count[1];
clk_8=count[2];
clk_16=count[3];
end
endmodule

// Test bench module

module freq_div_test ;
wire clk_2,clk_4,clk_8,clk_16;
reg reset,clk;
freq_div m1 ( clk_2,clk_4,clk_8,clk_16,reset,clk);
initial
clk = 1'b0;
always
#5 clk = ~clk;

initial
begin
#10; reset = 1'b1 ;
#10; reset = 1'b0 ;
#10; reset = 1'b1 ;
#10; reset = 1'b0 ;
#200 $finish;
end
initial
$monitor ($time, "Output clk_2=%d ",clk_2,"Output clk_4=%d ",clk_4,"Output clk_8=%d
",clk_8,"Output clk_16=%d ",clk_16 );
endmodule

Dept. of ECE, Govt. SKSJTI Page 29

HDL LAB (18ECL58)

Block Diagram:

Truth Table:

Clock Pulse Reset Q3 Q2 Q1 Q0

X 1 0 0 0 0
1 0 0 0 0 1
1 0 0 0 1 0
1 0 0 0 1 1
1 0 0 1 0 0
1 0 0 1 0 1
1 0 0 1 1 0
1 0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 0 1
1 0 1 0 1 0
1 0 1 0 1 1
1 0 1 1 0 0
1 0 1 1 0 1
1 0 1 1 1 0
1 0 1 1 1 1

Waveform:

Dept. of ECE, Govt. SKSJTI Page 30

HDL LAB (18ECL58)

For Synthesis of sequential circuits (Flip-flop and Counters) use Clock

divider

//Main module

module bin_count(clk,rst, qout);

input clk,rst;
output[3:0]qout;
reg[3:0]qout;

//Use the following code for synthesis of Flip-flop and Counters

reg[2:0]clk_signal; //For synthesis use [20:0]clk_signal;

reg clk_1;

initial
clk_signal=3'b000;

always@(posedge clk)

begin
clk_signal=clk_signal+1;
clk_1=clk_signal[1]; // For synthesis use clk_signal[16];
end

always@(posedge clk_1)
begin
if(rst)
qout=4'b0000;
else

qout=qout+1;
end

endmodule

Dept. of ECE, Govt. SKSJTI Page 31

HDL LAB (18ECL58)

10. Interface a DAC to FPGA and write Verilog code to generate Sine wave.

// Main module

module sine_wave(clk, data_out);

//declare input and output
input Clk;
output [7:0] data_out;
//declare the sine ROM - 30 registers each 8 bit wide.
reg [7:0] sine [0:63];
//Internal signals
integer i;
reg [7:0] data_out;
//Initialize the sine rom with samples.
initial
begin
i = 0;
sine[0] = 135; //77;
sine[1] =150; //93 ;
sine[2] = 164; //108;
sine[3] = 177; //122;
sine[4] = 189; //135;
sine[5] = 200; //147;
sine[6] = 210; //158;
sine[7] = 219; //168;
sine[8] = 227;
sine[9] = 234;
sine[10] =240;
sine[11] =245;
sine[12] =249;
sine[13] =252;
sine[14] =254;
sine[15] =255;
sine[16] =255;
sine[17] =254;
sine[18] =252;
sine[19] =249;
sine[20] =245;
sine[21] =240;
sine[22] =234;
sine[23] = 227;
sine[24] = 219;
sine[25] =210;
sine[26] =200;
sine[27] =189;
sine[28] =177;
sine[29] =164;
sine[30] =150;
sine[31] =135;
sine[32]=119 ;

Dept. of ECE, Govt. SKSJTI Page 32

 HDL LAB (18ECL58)

sine[33]=104 ;
sine[34] = 90;
sine[35] = 77;
sine[36] =65 ;
sine[37] = 54;
sine[38] = 44;
sine[39] = 35;
sine[40] = 27;
sine[41] = 20;
sine[42] =14;
sine[43] =9;
sine[44] =5;
sine[45] =2;
sine[46] =0;
sine[47] =0;
sine[48] =2;
sine[49] =5;
sine[50] =9;
sine[51] =14;
sine[52] =20;
sine[53] =27;
sine[54] =35;
sine[55] = 44;
sine[56] = 54;
sine[57] =65;
sine[58] =77;
sine[59] =90;
sine[60] =104;
sine[61] =119;
sine[62] =135;
sine[63] =150;
end

//At every positive edge of the clock, output a sine wave sample.
always@ (posedge(Clk))
begin
data_out = sine[i];
i = i+ 1;
if(i == 63)
i = 0;
end
endmodule

Dept. of ECE, Govt. SKSJTI Page 33

HDL LAB (18ECL58)

Waveform:

#PINLOCK_BEGIN

NET "clk" LOC = P2; ---> Connect to 100K Clock Pin

NET "rst" LOC = P3;

NET "op<0>" LOC = P4; -> To Pin 21 of DAC

NET "op<1>" LOC = P5; -> To Pin 22 of DAC
NET "op<2>" LOC = P7; -> To Pin 19 of DAC
NET "op<3>" LOC = P9; -> To Pin 20 of DAC
NET "op<4>" LOC = P10; ->To Pin 17 of DAC
NET "op<5>" LOC = P11; ->To Pin 18 of DAC
NET "op<6>" LOC = P12; ->To Pin 15 of DAC
NET "op<7>" LOC = P13; ->To Pin 16 of DAC
Connect Pin 26 of DAC to GND Pin
#PINLOCK_END

BLOCK DIAGRAM OF RAMP / TRIANGULAR / SQUARE WAVEFORM

FPGA OP DAC
CLK CRO

RST

Dept. of ECE, Govt. SKSJTI Page 34

HDL LAB (18ECL58)

11. Write a Verilog code to interface DAC and generate a Triangular Waveform.
//Main module

module tri_dac (clk,rst,op);

input clk;
input rst;
output [7:0] op;

wire [7:0] op;

reg [7:0] q;
reg ud;

initial
begin
ud = 1'b 0;
end

always @(posedge clk or negedge rst)

begin
if (rst == 1'b 0)
q = 8'b 0;
else
begin

if (ud == 1'b 0)
q = q + 1;

else if (ud == 1'b 1 )

q = q - 1;

end
end

assign op = q;

always @(posedge clk)

begin

if (q == 8'b 11111110)

ud <= 1'b 1;

else if (q == 8'b 00000001 )

ud <= 1'b 0;
end
endmodule

Dept. of ECE, Govt. SKSJTI Page 35

HDL LAB (18ECL58)

Waveform:

#PINLOCK_BEGIN

NET "clk" LOC = P2; ---> Connect to 100K Clock Pin

NET "rst" LOC = P3;

NET "op<0>" LOC = P4; -> To Pin 21 of DAC

NET "op<1>" LOC = P5; -> To Pin 22 of DAC
NET "op<2>" LOC = P7; -> To Pin 19 of DAC
NET "op<3>" LOC = P9; -> To Pin 20 of DAC
NET "op<4>" LOC = P10; ->To Pin 17 of DAC
NET "op<5>" LOC = P11; ->To Pin 18 of DAC
NET "op<6>" LOC = P12; ->To Pin 15 of DAC
NET "op<7>" LOC = P13; ->To Pin 16 of DAC
Connect Pin 26 of DAC to GND Pin
#PINLOCK_END

BLOCK DIAGRAM OF RAMP / TRIANGULAR / SQUARE WAVEFORM

FPGA OP DAC
CLK CRO

RST

Dept. of ECE, Govt. SKSJTI Page 36

HDL LAB (18ECL58)

12. Write a Verilog code to interface DAC and generate a Square Waveform.

//Main module

module squarewave(clk,rst,op);
input clk,rst;
output [7:0] op;
wire [7:0] op;
reg [7:0] temp;
reg [7:0] q;

always@(posedge clk)

begin

if(~rst)
q=8'b0;
else
q=q+1;
end

always@(q)
begin

if(q<=127)
temp=8'b00000000;
else
temp=8'b11111111;
end

assign op = temp;

endmodule

Dept. of ECE, Govt. SKSJTI Page 37

HDL LAB (18ECL58)

Waveform:

#PINLOCK_BEGIN

NET "clk" LOC = P2; ---> Connect to 100K Clock Pin

NET "rst" LOC = P3;

NET "op<0>" LOC = P4; -> To Pin 21 of DAC

NET "op<1>" LOC = P5; -> To Pin 22 of DAC
NET "op<2>" LOC = P7; -> To Pin 19 of DAC
NET "op<3>" LOC = P9; -> To Pin 20 of DAC
NET "op<4>" LOC = P10; ->To Pin 17 of DAC
NET "op<5>" LOC = P11; ->To Pin 18 of DAC
NET "op<6>" LOC = P12; ->To Pin 15 of DAC
NET "op<7>" LOC = P13; ->To Pin 16 of DAC
Connect Pin 26 of DAC to GND Pin
#PINLOCK_END

BLOCK DIAGRAM OF RAMP / TRIANGULAR / SQUARE WAVEFORM

FPGA OP DAC CRO

CLK

RST

Dept. of ECE, Govt. SKSJTI Page 38

HDL LAB (18ECL58)

13. Interface a DC motor to FPGA and write Verilog code to change its speed and direction

//Main module
module dcmotor (psw, pdcm, clk,dir_in,dir_out);
input [2:0] psw;
output pdcm;
input clk;
input dir_in;
output dir_out;
reg dir_out;
reg pdcm;
reg [11:0] sclkdiv;

// count upto 3000 rpm

reg vdcm;
always @(posedge clk)
begin
sclkdiv <= sclkdiv + 1;
end
always @ (psw or sclkdiv)
begin
if(dir_in == 1'b0)
dir_out = 1'b 0;
else
dir_out=1'b 1;
end
always @(psw or sclkdiv)
begin
if (sclkdiv == 12'b 000000000000)
begin
vdcm = 1'b 1;
end

// 1f4, 320, 44c, 578, 6a4, 7d0, 8fc, 9c4

if (psw == 3'b 000 & sclkdiv == 12'b 000111110100)

begin
vdcm = 1'b 0;
end
else if (psw == 3'b 001 & sclkdiv == 12'b 001100100000 )
begin
vdcm = 1'b 0;
end
else if (psw == 3'b 010 & sclkdiv == 12'b 010001001100 )
begin
vdcm = 1'b 0;
end
else if (psw == 3'b 011 & sclkdiv == 12'b 010101111000 )
begin
vdcm = 1'b 0;
Dept. of ECE, Govt. SKSJTI Page 39
HDL LAB (18ECL58)

end
else if (psw == 3'b 100 & sclkdiv == 12'b 011010100100 )
begin
vdcm = 1'b 0;
end
else if (psw == 3'b 101 & sclkdiv == 12'b 011111010000 )
begin
vdcm = 1'b 0;
end
else if (psw == 3'b 110 & sclkdiv == 12'b 100011111100 )
begin
vdcm = 1'b 0;
end
else if (psw == 3'b 111 & sclkdiv == 12'b 100111000100 )
begin
vdcm = 1'b 0;
end
if (vdcm == 1'b 1)
begin
pdcm <= 1'b 1;
end
else
begin
pdcm <= 1'b 0;
end
en
d
endmodule

#PINLOCK_BEGIN

NET "clk" LOC = P2;

NET "psw<1>" LOC = P10;
NET "psw<2>" LOC = P11;
NET "pdcm" LOC = P3;
NET "dir_in" LOC = P4;
NET "dir_out" LOC = P5
NET "pdcm" LOC = P9; - Connect to Pin No. 4 of DCMOTOR

#PINLOCK_END

BLOCK DIAGRAM OF DC MOTOR

psw
I/P pdc
FPGA DC MOTOR
CLK m

out

Dept. of ECE, Govt. SKSJTI Page 40

HDL LAB (18ECL58)

14. Interface a Stepper motor to FPGA and write Verilog code to control the Stepper motor.

//Main module
module stepm(clk,rst,dir,step_ctrl,dout);
input clk,rst,dir;
input [1:0] step_ctrl;
output [3:0] dout;

reg [3:0] dout;

reg [20:0] dclk;
reg div_clk;

always@(posedge clk)
begin
dclk=dclk+1;
end

always@(posedge clk)
begin
case(step_ctrl)
2'b00:div_clk=dclk[20];
2'b01:div_clk=dclk[18];
2'b10:div_clk=dclk[16];
2'b11:div_clk=dclk[14];
endcase
end

always@(posedge div_clk)
begin

if(!rst)
dout=4'b1001;

else

case(dir)
1'b0:dout={dout[0],dout[3:1]};
1'b1:dout={dout[2:0],dout[3]};
endcase
end

endmodule

Dept. of ECE, Govt. SKSJTI Page 41

HDL LAB (18ECL58)

#PINLOCK_BEGIN

NET "clk" LOC = P2; - Connect to 100K Clock Pin

NET "rst" LOC = P3;

NET "dir" LOC = P4;

NET "step_ctrl<0>" LOC = P5;

NET "step_ctrl<1>" LOC = P7;

NET "dout<0>" LOC = P31;

NET "dout<1>" LOC = P33;
NET "dout<2>" LOC = P34; ---> Connect Pin 1, 2, 3 and 4 of Stepper Motor
NET "dout<3>" LOC = P35;

#PINLOCK_END

BLOCK DIAGRAM OF STEPPER MOTOR

dout RST
FPGA STEPPER MOTOR
CLK

Dir Step Control [1:0]

Dept. of ECE, Govt. SKSJTI Page 42

HDL LAB (18ECL58)

Additional Programs

1. Write a VERILOG code to simulate and synthesize Logic Gates and demonstrate the
operation.

module gates(a,b,andg,org,nandg,norg,xorg,xnorg);
output andg,org,nandg,norg,xorg,xnorg;
input a,b;
assign andg =a&b;
assign org = a|b;
assign nandg
=~(a&b); assign norg
=~(a|b);
assign xorg =(a&(~b))|((~a)&b);
assign xnorg =(a&b)|((~a)&(~b));
endmodule

module gates_test;
wire andg,org,nandg,norg,xorg,xnorg;
reg a,b;
gates g(a,b,andg,org,nandg,norg,xorg,xnorg);
task display;
begin
$display (" a= ",a," b= ",b," and_out= ",andg," or_out= ",org," nand_out= ",nandg,"
nor_out= ",norg," xor_out= ",xorg,
" xnor_out= ",xnorg);
end
endtask
initial
begin
a=1'b0;b=1'b0;#5;display;
a=1'b0;b=1'b1;#5;display;
a=1'b1;b=1'b0;#5;display;
a=1'b1;b=1'b1;#5;display;
end
endmodule

Dept. of ECE, Govt. SKSJTI Page 43

HDL LAB (18ECL58)

Block Diagram: RTL Schematic:

Truth Table:
INPUTS OUTPUTS
A B ANDG NOTG ORG NANDG NORG XORG XNORG
0 0 0 1 0 1 1 0 1
0 1 0 1 1 1 0 1 0
1 0 0 0 1 1 0 1 0
1 1 1 0 1 0 0 0 1

Waveform:

Dept. of ECE, Govt. SKSJTI Page 44

HDL LAB (18ECL58)

2. Write a Verilog code for LCD Display and demonstrate it.

module LCD1602(clk, rs, rw, en,dat,LCD_P,LCD_N);

input clk;
output [7:0] dat;
output rs,rw,en,LCD_P,LCD_N;

reg e;
reg [7:0] dat;
reg rs;
reg [15:0] counter;
reg [4:0] current,next;
reg clkr;
reg [31:0] cnt=0;

parameter set0=4'h0;
parameter set1=4'h1;
parameter set2=4'h2;
parameter set3=4'h3;
parameter dat0=4'h4;
parameter dat1=4'h5;
parameter dat2=4'h6;
parameter dat3=4'h7;
parameter dat4=4'h8;
parameter dat5=4'h9;

parameter dat6=4'hA;
parameter dat7=4'hB;
parameter dat8=4'hC;
parameter dat9=4'hD;
parameter dat10=4'hE;
parameter dat11=5'h10;
parameter nul=4'hF;

assign LCD_N=0;
assign LCD_P=1;

always @(posedge clk)

begin
counter<=counter+1;
if(counter==16'h000f)
clkr<=~clkr;
end
always @(posedge clkr)
begin
current<=next;
case(current)
set0: begin rs<=0; dat<=8'h31; next<=set1; end
set1: begin rs<=0; dat<=8'h0C; next<=set2; end
set2: begin rs<=0; dat<=8'h6; next<=set3; end
set3: begin rs<=0; dat<=8'h1; next<=dat0; end

dat0: begin rs<=1; dat<="A"; next<=dat1; end

dat1: begin rs<=1; dat<="D"; next<=dat2; end
dat2: begin rs<=1; dat<="M"; next<=dat3; end

Dept. of ECE, Govt. SKSJTI Page 45

HDL LAB (18ECL58)

dat3: begin rs<=1; dat<=" "; next<=dat4; end

dat4: begin rs<=1; dat<="P"; next<=dat5; end
dat5: begin rs<=1; dat<="V"; next<=dat6; end
dat6: begin rs<=1; dat<="T"; next<=dat7; end
dat7: begin rs<=1; dat<=" "; next<=dat8; end
dat8: begin rs<=1; dat<="L"; next<=dat9; end
dat9: begin rs<=1; dat<="T"; next<=dat10; end
dat10: begin rs<=1; dat<="D"; next<=dat11; end
dat11: begin rs<=1; dat<=" "; next<=nul; end

nul: begin rs<=0; dat<=8'h00;

if(cnt!=2'h2)
begin
e<=0;next<=set0;cnt<=cnt+1;
end
else
begin next<=nul; e<=1;
end
end

default: next<=set0;
endcase
end
assign en=clkr|e;
assign rw=0;
endmodule

#PINLOCK_BEGIN

NET "clk" LOC = P52; ---> Connect to 100K Clock Pin

NET "en" LOC = P2; --- Connect to LCD Control Pin - EN

NET "rs" LOC = P3; -- Connect to LCD Control Pin - RS
NET "rw" LOC = P4; ---> Connect to LCD Control Pin - RW

NET "LCD_N" LOC = P7; - Connect to GND

NET "LCD_P" LOC = P5; --> Connect to +5V

NET "dat<0>" LOC = P31;

NET "dat<1>" LOC = P33;
NET "dat<2>" LOC = P34;
NET "dat<3>" LOC = P35; - -> Connect Header - H3 to LCD Data Pins
NET "dat<4>" LOC = P36;
NET "dat<5>" LOC = P37;
NET "dat<6>" LOC = P39;
NET "dat<7>" LOC = P40;

#PINLOCK_END

BLOCK DIAGRAM OF MOVING DISPLAY

in o/p LCD Data

CLK FPGA LCD Control LCD DISPLAY

o/p

Dept. of ECE, Govt. SKSJTI Page 46

HDL LAB (18ECL58)

EXPECTED VIVA QUESTION

1. Write a Verilog code to swap contents of two register with & without a temporary register?
2. Difference between task & function?
3. Difference between Inter statement &Intra statement delay ?
4. Difference between $Monitor & $Display
5. Tell me how blocking & non-blocking statements get executed ?
6. Variable & signal which will be updated first ?
7. What is sensitivity list ?
8. In a pure combinational circuit is it necessary to mention all the inputs is sensitivity disk ?
if YES, why ?
9. Difference between Verilog & VHDL ?
10. Can you tell me some of system tasks & their purpose?
11. What is the difference between === & == ?
12. What is the difference between wire & register?
13. Data types, operators of Verilog & VHDL ?
14. What is the difference between simulation & synthesize ?
15. What is an event
16. What is the purpose of a for loop
17. Name any two programming tool of VHDL
18. What is the difference between concurrent & sequential statements?
19. What is an alias & write its syntax
20. What is the difference between array & record?
21. What are signal?
22. List out the four model for port in VHDL
23. What do we need to generate hardware from VHDL model ?
24. Difference between FPGA & CPLD ?
25. Expansion of VHDL, FPGA, CPLD, ASIC
26. Number of pin in CPLD & FPGA
27. Device , family & speed of FPGA
28. Different styles of abstraction levels
29. Difference between always & initial
30. Difference between case, casex & casez
31. Difference between synchronous & asynchronous reset.

Dept. of ECE, Govt. SKSJTI Page 47