Microprocessors and Embedded Systems

EEE 4109

Introduction to Microcontroller
and ATmega328p

Md. Ariful Islam

Lecturer, Department of Electrical & Electronic Engineering
Rajshahi University of Engineering & Technology, Rajshahi-6204, Bangladesh
E-mail: arif.ruet.eee17@gmail.com ; ariful.islam@eee.ruet.ac.bd
 What is a Microcontroller ?

▪ A microcontroller is a small, integrated circuit (a "computer on a chip") designed to control

specific functions within an embedded system.
▪ It combines a processor core, memory, input/output (I/O) and other peripherals such as
counter/timers, analog-to-digital converters, serial communication hardware, etc. on a single
chip.

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 Microprocessor vs Microcontroller

Aspects Microprocessor Microcontroller

A general-purpose CPU used in computers and A compact integrated circuit with CPU, memory,
Definition
systems and I/O on a single chip
Purpose Processing large amounts of data and tasks Controlling specific embedded applications
Contains only CPU; memory and I/O Includes CPU, RAM, ROM, timers, I/O ports
Components
connected externally on-chip
Cost Higher Lower
Power
Higher Lower
Consumption
Speed Generally faster due to powerful architecture Slower compared to microprocessors
Flexibility More flexible for general computing tasks Less flexible, designed for specific tasks
Embedded systems like washing machines,
Application PCs, servers, high-end computing devices
robots, smart watch, digital camera etc.
Examples Intel Core i7, AMD Ryzen, ARM Cortex-A Atmel ATmega328, PIC16F877A, STM32
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 Classification of Microcontrollers

Types of
Microcontroller

Bus Width Memory Device Instruction Set Memory Architecture

1. 8-bit Microcontroller 1. Embedded Memory 1. RISC Microcontroller 1. Harvard Microcontroller

2. 16-bit Microcontroller 2. External Memory 2. CISC Microcontroller 2. Von-Neumann Microcontroller
3. 32-bit Microcontroller

https://www.elprocus.com/microcontrollers-types-and-applications/

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 RISC vs SISC

Reduced Instruction Set Computer (RISC) Complex Instruction Set Computer (CISC)

Instruction takes one or two cycles Instruction takes multiple cycles

Only load/store instructions are used to access In additions to load and store instructions, memory
memory access is possible with other instructions also.
Instructions executed by hardware Instructions executed by the micro program
Fixed format instruction Variable format instructions
Few addressing modes Many addressing modes
Few instructions Complex instruction set
Most of the have multiple register banks Single register bank
Highly pipelined Less pipelined
Complexity is in the compiler Complexity in the microprogram

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 Von-Neumann v/s Harvard Architecture

Von-Neumann Architecture Harvard Architecture

Von-Neumann architecture has single physical Harvard architecture has physically separate
memory for program and data as well as single program and data memory and separate buses to
bus to access the same access the same.
With harvard architecture processor can access
In Von-Neumann architecture either program or
program and data memory at the same time which
data can be accessed at a time.
can help to perform faster program execution
With Von-Neumann architecture since only With harvard architecture it is possible to have
single bus is available, bus characteristics are different address and data bus width for program
same for program and data. and data memory
H/W design is simple and cost efficient. H/W design is complex and expensive.
Since program and data share the same memory, a
Since program and data are different, programs are
program error can rewrite the instruction and
prone to crash caused by program error itself.
result into undesirable behavior or crash.
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 Von-Neumann v/s Harvard Architecture (contd.)

Von-Neumann/Princeton Architecture Harvard Architecture

Data Bus
Data Bus Program Program
Address Bus
Memory Memory
CPU Address Bus CPU Data Bus
Data
Data
Memory Address Bus
Memory

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 Microcontroller Family

Microcontroller

8051 AVR PIC ARM

89S51 ATmega8 PIC10F XX STM32 F103 C8T6

89S52 ATmega16 PIC12F XX STM32 F407 VG
89C51 ATmega32 PIC16F XX etc.
89C52 ATmega328 etc.
etc. etc.

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 Comparison of Microcontroller Family

Aspects 8051 AVR PIC ARM

ARM Holdings (cores licensed to
Developed By Intel Atmel (now Microchip) Microchip Technology
vendors)

Architecture CISC RISC RISC RISC (Advanced)

32-bit (some 64-bit in advanced

Word Size 8-bit 8-bit (some 16/32-bit) 8-bit, 16-bit, 32-bit
versions)
Moderate (12 clock Fast (1–4 clock Very fast (pipelining, high clock
Speed Fast (1 clock cycle/instruction)
cycles/instruction) cycles/instruction) rates)
Memory
Harvard/Von Neumann Harvard Harvard Harvard
Architecture
Thumb/Thumb-2 (compact), ARM
Instruction Set Complex and long Simple and efficient Simple and efficient
(powerful)
Programming
Assembly, C Assembly, C Assembly, C C, C++, Assembly
Language
Power Low to moderate (depending on
High Low Low
Consumption implementation)
Varies (some very low-cost Moderate to high (but efficient for
Cost Low Moderate
models) performance)

Basic control systems, Smartphones, IoT devices, drones,

Applications Robotics, automation Industrial, consumer electronics
legacy systems automotive
ATmega328p

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 Features of ATmega328p

▪ High performance, low power AVR 8-bit microcontroller

▪ Advanced RISC architecture:

✓ 131 powerful instructions – most single clock cycle execution
✓ 32 × 8 general purpose working registers
✓ Up to 16 MIPS (Million Instructions Per Second) throughput at 16 MHz

▪ Memory:
✓ 32 Kbytes of in-system self-programmable Flash program memory
✓ 1 Kbytes EEPROM (Electrically Erasable Programmable Read-only Memory)
✓ 2 Kbytes internal SRAM (Static Random Access Memory)

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 Features of ATmega328p (contd.)

▪ Peripheral features:
✓ Two 8-bit Timer/Counters with separate prescaler and compare mode
✓ One 16-bit Timer/Counter with separate prescaler, compare mode, and capture mode
✓ Real time counter with separate oscillator
✓ Six PWM channels
✓ Programmable serial USART
✓ Programmable watchdog timer with separate on-chip oscillator
✓ On-chip analog comparator
✓ Interrupt and wake-up on pin change

▪ Special microcontroller features:

✓ Power-on reset and programmable brown-out detection
✓ Internal calibrated oscillator
✓ External and internal interrupt sources
✓ Six sleep modes: Idle, ADC noise reduction, power-save, power-down, standby, and extended
standby 12
 Features of ATmega328p

▪ I/O and packages:

✓ 23 programmable I/O lines
✓ 32-lead TQFP, and 32-pad QFN/MLF

▪ Operating voltage: 2.7 V to 5.5 V for ATmega328P

▪ Temperature range: Automotive temperature range: -40°C to +125°C

▪ Speed grade:
✓ 0 to 8 MHz at 2.7 to 5.5V (automotive temperature range: -40°C to +125°C)
✓ 0 to 16 MHz at 4.5 to 5.5V (automotive temperature range: -40°C to +125°C)

▪ Low power consumption:

✓ Active mode: 1.5 mA at 3 V – 4 MHz
✓ Power-down mode: 1 μA at 3 V

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General Architecture of an AVR Microcontroller

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 General Architecture of an AVR Microcontroller (contd.)

▪ Memory Organization:

➢ 32 Kbytes Flash program memory: Non-volatile memory (retains data even when power is off) used
to store the firmware or program code.
➢ 1 Kbytes EEPROM (Electrically Erasable Programmable Read-only Memory): Non-volatile
memory used for frequent small writes (e.g., storing configuration settings or calibration data).
➢ 2 Kbytes internal SRAM (Static Random Access Memory): Volatile memory used for temporary data
storage during program execution.

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 General Architecture of an AVR Microcontroller (contd.)

➢ 32 Kbytes Flash program memory:

Details: https://cookierobotics.com/043/

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 General Architecture of an AVR Microcontroller (contd.)

➢ 2 Kbytes internal SRAM:

Details: https://cookierobotics.com/043/
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 General Architecture of an AVR Microcontroller (contd.)

▪ Status and Control Register: Holds flags (Zero, Carry, Overflow, etc.) and control bits that indicate or
modify the behavior of the ALU and other operations.

SREG Register Bits

7 6 5 4 3 2 1 0
I T H S V N Z C
(Global (Bit Copy (Half Carry (Sign Flag) (Overflow (Negative (Zero Flag) (Carry Flag)
Interrupt Storage) Flag) Flag) Flag)
Enable)

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 General Architecture of an AVR Microcontroller (contd.)

SREG Bit Name Description

Enables/disables all interrupts. Set (1) to enable interrupts, cleared (0) to
7 I (Global Interrupt Enable)
disable.
Used with BLD (Bit Load) and BST (Bit Store) instructions for bit
6 T (Bit Copy Storage)
manipulation.
Set (1) when a carry occurs between bits 3 and 4 in an arithmetic
5 H (Half Carry Flag)
operation.
Indicates the true sign of a result (always S = N ⊕ V, where N is
4 S (Sign Flag)
Negative, V is Overflow).
Set (1) if an arithmetic operation results in a signed overflow (e.g.,
3 V (Overflow Flag)
adding two positives yields a negative).
2 N (Negative Flag) Set (1) if the result of an operation is negative (MSB of result is 1).
1 Z (Zero Flag) Set (1) if the result of an operation is zero; otherwise cleared (0).
Set (1) if an operation generates a carry (addition) or borrow
0 C (Carry Flag)
(subtraction). Also used in shift/rotate operations.

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 General Architecture of an AVR Microcontroller (contd.)

▪ Arithmetic and Logic Unit (ALU): Performs arithmetic and logical operations like ADD, SUB, AND,
OR, etc. It operates incorporating registers and flags in Status Register.

▪ Program Counter (PC): Holds the address of the next instruction to be executed from the Flash
memory. It’s value is auto-incremented after fetching each instruction.

▪ Instruction Register: Temporarily holds the instruction fetched from Flash memory before decoding.

▪ Instruction Decoder: Decodes the instruction and generates control signals for internal operations.

▪ Data Bus (8-bit): Internal data path used to transfer 8-bit data between components (registers, ALU,
SRAM, etc.).

▪ I/O Lines: Digital input/output pins used to interface with external components like LEDs, switches,
sensors, etc.
 General Architecture of an AVR Microcontroller (contd.)

▪ Interrupt Unit: Manages interrupt signals. It allows the CPU to respond immediately to asynchronous
events (e.g., pin change, timer overflow).

▪ SPI Unit (Serial Peripheral Interface): Enables serial communication with other SPI devices (e.g.,
sensors, memory chips).

▪ Watchdog Timer: Resets the microcontroller if the software becomes unresponsive. It prevents system
hang.

▪ Analog Comparator: Compares two analog voltages and sets a flag if one is higher than the other. Used in
analog signal processing.

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Architecture of ATmega328p

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How an Instruction is Executed ?

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 How an Instruction is Executed ? (contd.)

1. The next instruction in memory is read, indicated by the address stored in the program
counter
2. The instruction is decoded into a set of commands or signals for each of the components in
the processor
3. The program counter increments so that it points to the next location in memory
4. Data is loaded from memory (or input device(s)) into register(s), the location of this data is
usually stored in the instruction code as an operand
5. If the ALU is required to execute the operation, the processor instructs the hardware to carry
this out
6. The result is written back to a memory location, to a register, or even to an output device
7. Jump back to step 1

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 Pin Diagram of ATmega328p

28-Pin Plastic Dual In-line Package (PDIP): It is used in breadboarded designs.

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 Pin Diagram of ATmega328p (contd.)

Bit 7 6 5 4 3 2 1 0
ATmega328p PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Port B
Arduino -- -- D13 D12 D11 D10 D9 D8
ATmega328p -- PC6 PC5 PC4 PC3 PC2 PC1 PC0
Port C
Arduino -- -- A5 A4 A3 A2 A1A0
ATmega328p PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Port D
Arduino D7 D6 D5 D4 D3 D2 D1 D0

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 Pin Diagram of ATmega328p (contd.)

Pin No. Pin name Secondary Function

1 PC6 (RESET) Pin by default is used as RESET pin.

2 PD0 (RXD) RXD (Data Input Pin for USART)

3 PD1 (TXD) TXD (Data Output Pin for USART)

4 PD2 (INT0) External Interrupt source 0

External Interrupt source 1
5 PD3 (INT1/OC2B) OC2B (PWM - Timer/Counter 2 Output Compare Match B Output)

T0 (Timer 0 External Counter Input)

6 PD4 (XCK/T0) XCK (USART External Clock I/O)

7 VCC Connected to positive voltage

8 GND Connected to ground

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 Pin Diagram of ATmega328p (contd.)

Pin No. Pin name Secondary Function

PB6 XTAL1 (Chip Clock Oscillator pin 1 or External clock input)

9
(XTAL1/TOSC1) TOSC1 (Timer Oscillator pin 1)

PB7 XTAL2 (Chip Clock Oscillator pin 2)

10
(XTAL2/TOSC2) TOSC2 (Timer Oscillator pin 2)

PD5 T1 (Timer1 External Counter Input)

11
(T1/OC0B) OC0B (PWM - Timer/Counter 0 Output Compare Match B Output)

PD6 AIN0 (Analog Comparator Positive I/P)

12
(AIN0/OC0A) OC0A (PWM - Timer/Counter 0 Output Compare Match A Output)

13 PD7 (AIN1) AIN1 (Analog Comparator Negative I/P)

ICP1 (Timer/Counter1 Input Capture Pin). When the specified edge is detected, the
PB0
14 current value of the timer counter is copied into the Input Capture Register (ICR).
(ICP1/CLKO)
CLKO (Divided System Clock. The divided system clock can be output on the PB0 pin)

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 Pin Diagram of ATmega328p (contd.)

Pin No. Pin name Secondary Function

15 PB1 (OC1A) OC1A (Timer/Counter1 Output Compare Match A Output)

SS (SPI Slave Select Input). This pin is low when controller acts as slave.
16 PB2 (SS/OC1B)
OC1B (Timer/Counter1 Output Compare Match B Output)
MOSI (Master Output Slave Input). When controller acts as slave, the data is
17 PB3 (MOSI/OC2A) received by this pin.
OC2 (Timer/Counter2 Output Compare Match Output)

MISO (Master Input Slave Output). When controller acts as slave, the data is sent
18 PB4 (MISO)
to master by this controller through this pin.

SCK (SPI Bus Serial Clock). This is the clock shared between this controller and
19 PB5 (SCK)
other system for accurate data transfer.

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 Pin Diagram of ATmega328p (contd.)

Pin No. Pin name Secondary Function

20 AVCC Power for Internal ADC Converter

21 AREF Analog Reference Pin for ADC

22 GND GROUND

23 PC0 (ADC0) ADC0 (ADC Input Channel 0)

24 PC1 (ADC1) ADC1 (ADC Input Channel 1)

25 PC2 (ADC2) ADC2 (ADC Input Channel 2)

26 PC3 (ADC3) ADC3 (ADC Input Channel 3)

ADC4 (ADC Input Channel 4)

27 PC4 (ADC4/SDA)
SDA (Two-wire Serial Bus Data Input/output Line for I2C communication)
ADC5 (ADC Input Channel 5)
28 PC5 (ADC5/SCL)
SCL (Two-wire Serial Bus Clock Line for I2C communication)
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 THE END

Thank You
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