NYCU EE-VLSI 2023
Lab2: 1-Bit Full Adder: Standard Cell Layout
Due Date 2025/10/17 12:00
I. Please Design 1-bit full adder with D flip-flop attached. The design specifications
are given as follows:
1. Circuit name: FA (FA.sp)
2. Input port: A, B, CIN, CLK
3. Output port: DCOUT, DSUM, COUT, SUM
4. Please name your FA circuit in following order:
.subckt FA A B CIN CLK DSUM DCOUT SUM COUT
II. The specification is described as the following:
1. Output loading of COUT and SUM: 10fF
2. Supply voltage: 1.8V
3. Rise time and fall time of input signal: 0.1ns
4. Pre-simulation (Hspice):
worst case needs to meet following requirements (TT corner)
(1) Longest rise and fall time of output COUT/SUM: < 0.3ns
(2) Maximum propagation delay, i.e. A/B/CIN to DSUM/DCOUT: < 0.3ns
(3) Average power: 0~300uw (with given pattern) in 0~30ns
(4) Use positive edge trigger D flip-flop and there is only one clock source.
(5) Input signals will change at negative edge and the output will be checked
at next negative edge.
(6) Clock frequency can be defined by yourself.
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5. This design will be requested to follow the standard cell layout and the layout
shape of FA is shown as follows:
Fig.1 Layout shape
6. The specifications of layout:
(1) The whole layout shape (except NWell) has to be fixed in layout height.
(2) The layout height should be fixed to be 5.04um. (from P-PLUS to
N-PLUS)
(3) The metal width of VDD & GND rails should be fixed to be 0.8um.
(4) Power rails should be placed at the top (VDD) and bottom (GND) of your
layout design.
(5) All PMOSs and NMOSs should be limited to locate in opposite parts.
(6) About usage of metal, only metal 1~metal 3 are allowed.
(7) Use FA logic (like below).
(8) The schematic of D flip-flop is not limited, but must be positive edge
trigger.
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III. Questions:
1. How to reduce your area of layout? What are advantages and disadvantages of
reducing area?
2. What causes the difference between pre-sim and post-sim?
3. Why you need Avoid-Latch-Up contact and how it works?
IV. Grading Policy:
1. Demo: 50%
(1) Layout: 15% (Partial Scoring)
(2) DRC, LVS: 20% (10% for each)
(3) Post-sim waveform correctness (including input signals): 15%
2. Performance: 20% (Area ranking, those who fail demo will not be included.)
3. Report: 30%
(1) Summary of your structure including whole layout of 1-bit full adder.
(2) Fill the table in the report, including rise time, fall time and propagation
delay of all 8 conditions with highlighting of the worst case, and average
power. (Also paste the screenshot)
(3) Output waveform (pre-sim & post-sim), with given input patterns.
(4) Capture the right DRC and LVS result in picture.
(5) Questions above in III.
(6) Please keep the report comprehensive yet concise.
Fig2. Correct DRC and LVS result
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V. Demo rules:
1. Location: ED415
2. Demo time:
1st demo: 2025/10/17 (Fri.) 13:20
2nd demo: 2025/10/22 (Wed.) 12:00 (30% off)
3. Show your layout, verification results and post-simulation waveform.
4. Please hand in your HW on system before you demo with TAs.
Fig. 3 Input signals
Note:
1. Extract the files to your own account：
“tar -xvf ~vlsilabTA01/UMC018.tar” No need to re-tar if you have extracted the .tar file in Lab01.
2. Create new cell view and finish your design. (Library creation is optional.)
3. You need to hand in the following files:
File Description
FA.gds From Stream directory.
FA.sp Pre-sim design.
Lab02_report.pdf PDF format, others are forbidden.
Step1. >> cd ~/UMC018/SUBMIT/
Step2. >> ./00_tar Lab02
Step3. >> ./01_submit Lab02
Step4. >> ./02_check Lab02 1st_demo OR >> ./02_check Lab02 2nd_demo
You will find Lab02_report.pdf and Lab02_[StudentID]_[Demo].tar.gz in your dictionary. You
can extract Lab02_[StudentID]_[Demo].tar.gz to check all the files have been submitted.
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4. Do NOT modify port names, A, B, CIN, CLK, DSUM, DCOUT, SUM and COUT
in your pre-sim file and layout.
5. You will not get any point if you break any rules.
6. Any question about Lab2 should be posted on New E3, rather than directly send
emails to TA.
7. Enjoy the fun from this assigned work.
