COMPUTER ORGANIZATION AND RISC-V

2nd ed.
The Hardware/Software
DESIGN Interface

Chapter 4
The Processor
 §4.1 Introduction
Introduction
■ CPU performance factors
■ Instruction count
■ Determined by ISA and compiler
■ CPI and Cycle time
■ Determined by CPU hardware
■ We will examine two RISC-V implementations
■ A simplified version
■ A more realistic pipelined version
■ Simple subset, shows most aspects
■ Memory reference: ld, sd
■ Arithmetic/logical: add, sub, and, or
■ Control transfer: beq

Chapter 4 — The Processor — 2

Instruction Execution
■ PC → instruction memory, fetch instruction
■ Register numbers → register file, read registers
■ Depending on instruction class
■ Use ALU to calculate
■ Arithmetic result
■ Memory address for load/store
■ Branch comparison
■ Access data memory for load/store
■ PC ← target address or PC + 4

Chapter 4 — The Processor — 3

CPU Overview

Chapter 4 — The Processor — 4

Multiplexers
■ Can’t just join
wires together
■ Use multiplexers

Chapter 4 — The Processor — 5

Control

Chapter 4 — The Processor — 6

 §4.2 Logic Design Conventions
Logic Design Basics
■ Information encoded in binary
■ Low voltage = 0, High voltage = 1
■ One wire per bit
■ Multi-bit data encoded on multi-wire buses
■ Combinational element
■ Operate on data
■ Output is a function of input
■ State (sequential) elements
■ Store information

Chapter 4 — The Processor — 7

Combinational Elements
■ AND-gate ■ Adder A
Y
+
■ Y=A&B ■ Y=A+B B

A
Y
B

■ Arithmetic/Logic Unit
■ Multiplexer ■ Y = F(A, B)
■ Y = S ? I1 : I0
A
I0 M
u Y AL Y
I1 x U
B
S F

Chapter 4 — The Processor — 8

Sequential Elements
■ Register: stores data in a circuit
■ Uses a clock signal to determine when to
update the stored value
■ Edge-triggered: update when Clk changes
from 0 to 1

Clk
D Q
D

Clk
Q

Chapter 4 — The Processor — 9

 Sequential Elements
■ Register with write control
■ Only updates on clock edge when write control
input is 1
■ Used when stored value is required later

Clk

D Q Write

Write D
Clk
Q

Chapter 4 — The Processor — 10

Clocking Methodology
■ Combinational logic transforms data during
clock cycles
■ Between clock edges
■ Input from state elements, output to state
element
■ Longest delay determines clock period

Chapter 4 — The Processor — 11

 §4.3 Building a Datapath
Building a Datapath
■ Datapath
■ Elements that process data and addresses
in the CPU
■ Registers, ALUs, mux’s, memories, …
■ We will build a RISC-V datapath
incrementally
■ Refining the overview design

Chapter 4 — The Processor — 12

Instruction Fetch

Increment by
4 for next
64-bit instruction
register

Chapter 4 — The Processor — 13

R-Format Instructions
■ Read two register operands
■ Perform arithmetic/logical operation
■ Write register result

Chapter 4 — The Processor — 14

Load/Store Instructions
■ Read register operands
■ Calculate address using 12-bit offset
■ Use ALU, but sign-extend offset
■ Load: Read memory and update register
■ Store: Write register value to memory

Chapter 4 — The Processor — 15

Branch Instructions
■ Read register operands
■ Compare operands
■ Use ALU, subtract and check Zero output
■ Calculate target address
■ Sign-extend displacement
■ Shift left 1 place (halfword displacement)
■ Add to PC value

Chapter 4 — The Processor — 16

Branch Instructions
Just
re-routes
wires

Sign-bit wire
replicated

Chapter 4 — The Processor — 17

Composing the Elements
■ First-cut data path does an instruction in
one clock cycle
■ Each datapath element can only do one
function at a time
■ Hence, we need separate instruction and data
memories
■ Use multiplexers where alternate data
sources are used for different instructions

Chapter 4 — The Processor — 18

R-Type/Load/Store Datapath

Chapter 4 — The Processor — 19

Full Datapath

Chapter 4 — The Processor — 20

 §4.4 A Simple Implementation Scheme
ALU Control
■ ALU used for
■ Load/Store: F = add
■ Branch: F = subtract
■ R-type: F depends on opcode
ALU control Function
0000 AND
0001 OR
0010 add
0110 subtract

Chapter 4 — The Processor — 21

 ALU Control
■ Assume 2-bit ALUOp derived from opcode
■ Combinational logic derives ALU control

ALU
opcode ALUOp Operation ALU function control
ld 00 load register add 0010
sd 00 store register add 0010
beq 01 branch on equal subtract 0110

R-type 10 add add 0010

subtract subtract 0110
AND AND 0000
OR OR 0001

Chapter 4 — The Processor — 22

Datapath With Control

Chapter 4 — The Processor — 23

R-Type Instruction

Chapter 4 — The Processor — 24

Load Instruction

Chapter 4 — The Processor — 25

Branch-on-Equal Instruction

Chapter 4 — The Processor — 26

Performance Issues
■ Longest delay determines clock period
■ Critical path: load instruction
■ Instruction memory → register file → ALU →
data memory → register file
■ Not feasible to vary period for different
instructions
■ Violates design principle
■ Making the common case fast
■ We will improve performance by pipelining

Chapter 4 — The Processor — 27

 §4.6 An Overview of Pipelining
Pipelining Analogy
■ Pipelined laundry: overlapping execution
■ Parallelism improves performance

Chapter 4 — The Processor — 28

RISC-V Pipeline
■ Five stages, one step per stage
1. IF: Instruction fetch from memory
2. ID: Instruction decode & register read
3. EX: Execute operation or calculate address
4. MEM: Access memory operand
5. WB: Write result back to register

Chapter 4 — The Processor — 29

 Pipeline Performance
■ Assume time for stages is
■ 100ps for register read or write
■ 200ps for other stages
■ Compare pipelined datapath with single-cycle
datapath

Instr Instr fetch Register ALU op Memory Register Total time

read access write
ld 200ps 100 ps 200ps 200ps 100 ps 800ps
sd 200ps 100 ps 200ps 200ps 700ps
R-format 200ps 100 ps 200ps 100 ps 600ps
beq 200ps 100 ps 200ps 500ps

Chapter 4 — The Processor — 30

Pipeline Performance
Single-cycle (Tc= 800ps)

Pipelined (Tc= 200ps)

Chapter 4 — The Processor — 31

Pipelining and ISA Design
■ RISC-V ISA designed for pipelining
■ All instructions are 32-bits
■ Easier to fetch and decode in one cycle
■ c.f. x86: 1- to 17-byte instructions
■ Few and regular instruction formats
■ Can decode and read registers in one step
■ Load/store addressing
■ Can calculate address in 3rd stage, access memory
in 4th stage

Chapter 4 — The Processor — 32

Hazards
■ Situations that prevent starting the next
instruction in the next cycle
■ Structure hazards
■ A required resource is busy
■ Data hazard
■ Need to wait for previous instruction to
complete its data read/write
■ Control hazard
■ Deciding on control action depends on
previous instruction

Chapter 4 — The Processor — 33

Structural Hazards
■ Conflict for use of a resource
■ In RISC-V pipeline with a single memory
■ Load/store requires data access
■ Instruction fetch would have to stall for that
cycle
■ Would cause a pipeline “bubble”
■ Hence, pipelined datapaths require
separate instruction/data memories
■ Or separate instruction/data caches

Chapter 4 — The Processor — 34

Data Hazards
■ An instruction depends on completion of
data access by a previous instruction
■ addx19, x0, x1
sub x2, x19, x3

Chapter 4 — The Processor — 35

Forwarding (aka Bypassing)
■ Use result when it is computed
■ Don’t wait for it to be stored in a register
■ Requires extra connections in the datapath

Chapter 4 — The Processor — 36

Load-Use Data Hazard
■ Can’t always avoid stalls by forwarding
■ If value not computed when needed
■ Can’t forward backward in time!

Chapter 4 — The Processor — 37

 Code Scheduling to Avoid Stalls
■ Reorder code to avoid use of load result in
the next instruction
■ C code for a = b + e; c = b + f;

ld x1, 0(x0) ld x1, 0(x0)

ld x2, 8(x0) ld x2, 8(x0)
x
add x3, x1, ld x4, 16(x0)
stall 2
sd x3, 24(x0) add x3, x1, x2
ld x4, 16(x0) sd x3, 24(x0)
add x5, x1, x add x5, x1, x4
stall 4
sd x5, 32(x0) sd x5, 32(x0)
13 cycles 11 cycles

Chapter 4 — The Processor — 38

Stall on Branch
■ Wait until branch outcome determined
before fetching next instruction

Chapter 4 — The Processor — 39

 §4.7 Pipelined Datapath and Control
RISC-V Pipelined Datapath

MEM

Right-to-left WB
flow leads to
hazards

Chapter 4 — The Processor — 40

Pipeline registers
■ Need registers between stages
■ To hold information produced in previous cycle

Chapter 4 — The Processor — 41

Pipeline Summary
The BIG
Picture
■ Pipelining improves performance by
increasing instruction throughput
■ Executes multiple instructions in parallel
■ Each instruction has the same latency
■ Subject to hazards
■ Structure, data, control
■ Instruction set design affects complexity of
pipeline implementation
Chapter 4 — The Processor — 42