COMPUTER ORGANIZATION AND DESIGN ARM
Edition
The Hardware/Software Interface
Chapter 4
The Processor
Lecture 8: ECE4206 Intro to Microprocessors
§4.2 Logic Design Conventions
Logic Design Basics
◼ Information encoded in binary
◼ Low voltage = 0, High voltage = 1
◼ One wire per bit
◼ Multi-bit data encoded on multi-wire buses
◼ Combinational element
◼ Operate on data
◼ Output is a function of current input
◼ State (sequential) elements
◼ Store information
Chapter 4 — The Processor — 2
Combinational Elements
◼ AND-gate ◼ Adder A
Y
+
◼ Y=A&B ◼ Y=A+B B
A
Y
B
◼ Arithmetic/Logic Unit
◼ Multiplexer ◼ Y = F(A, B)
◼ Y = S ? I1 : I0
A
I0 M
u Y ALU Y
I1 x
B
S F
Chapter 4 — The Processor — 3
Sequential Elements
◼ Register: stores data in a circuit
◼ Uses a clock signal to determine when to
update the stored value
◼ Edge-triggered: update when Clk changes
from 0 to 1
Clk
D Q
D
Clk
Q
Chapter 4 — The Processor — 4
Sequential Elements
◼ Register with write control
◼ Only updates on clock edge when write
control input is 1
◼ Used when stored value is required later
Clk
D Q Write
Write D
Clk
Q
Chapter 4 — The Processor — 5
Clocking Methodology
◼ Combinational logic transforms data during
clock cycles
◼ Between clock edges
◼ Input from state elements, output to state
element
◼ Longest delay determines clock period
Chapter 4 — The Processor — 6
§4.3 Building a Datapath
Building a Datapath
◼ Datapath
◼ Elements that process data and addresses
in the CPU
◼ Registers, ALUs, mux’s, memories, …
◼ We will build a LEGv8 datapath
incrementally
◼ Refining the overview design
Chapter 4 — The Processor — 7
Instruction Fetch
Increment by
4 for next
64-bit instruction
register
Chapter 4 — The Processor — 8
LEGv8 R-format Instructions
R-Type
opcode Rm shamt Rn Rd Instruction
11 bits 5 bits 6 bits 5 bits 5 bits Format
◼ Instruction fields
◼ opcode: operation code
◼ Rm: the second register source operand
◼ shamt: shift amount (00000 for now) used in
shift instructions
◼ Rn: the first register source operand
◼ Rd: the register destination
Chapter 2 — Instructions: Language of the Computer — 9
R-Format Instructions
◼ Read two register operands
◼ Perform arithmetic/logical operation
◼ Write register result
◼ The register number inputs are 5 bits wide to specify one of 32 registers (32 = 2^5),
whereas the data input and two data output buses are each 64 bits wide.
Chapter 4 — The Processor — 10
LEGv8 D-format Instructions
D-Type
opcode address op2 Rn Rt Instruction
11 bits 9 bits 2 bits 5 bits 5 bits Format
◼ Load/store instructions
◼ Can not use R-Type instruction format as the 5-bit field is too
small to be used for the address as the largest constant would
be 31
◼ Rn: base register
◼ address: constant offset from contents of the base register (+/-
32 doublewords)
◼ Rt: destination (load) or source (store) register number
◼ Design Principle 3: Good design demands good
compromises
◼ Different formats complicate decoding but allow 32-bit
instructions uniformly
◼ Keep formats as similar as possible
Chapter 2 — Instructions: Language of the Computer — 11
Load/Store Instructions
◼ Read register operands
◼ Calculate address using 9-bit offset
◼ Use ALU, but sign-extend offset to 64-bit sign-extend. Sign-extend is to increase
the size of a data item by replicating the high-order sign bit of the original data
item in the high order bits of the larger, destination data item.
◼ Load: Read memory and update register
◼ Store: Write register value to memory
Chapter 4 — The Processor — 12
Load/Store Instructions
◼ The sign extension unit has a 32-bit instruction as input that selects a 9-bit for load
and store or a 19-bit field for compare and branch on zero that is sign-extended
into a 64-bit result appearing on the output
Chapter 4 — The Processor — 13
Branch Addressing
◼ B-type
◼ B 1000 // go to location 10000ten
5 10000ten
6 bits 26 bits
◼ CB-type
◼ CBNZ X19, Exit // go to Exit if X19 != 0
181 Exit 19
8 bits 19 bits 5 bits
◼ Both addresses are PC-relative
◼ Address = PC + offset (from instruction)
Chapter 2 — Instructions: Language of the Computer — 14
Branch Instructions
◼ Read register operands
◼ Compare operands
◼ Use ALU, subtract and check Zero output
◼ Calculate target address
◼ Sign-extend displacement
◼ Shift left 2 places (word displacement)
◼ Add to PC + 4
◼ Already calculated by instruction fetch
Chapter 4 — The Processor — 15
Branch Instructions
Just
re-routes
wires
Sign-bit wire
replicated
Chapter 4 — The Processor — 16
Composing the Elements
◼ First-cut data path does an instruction in
one clock cycle
◼ Each datapath element can only do one
function at a time
◼ Hence, we need separate instruction and data
memories
◼ Use multiplexers where alternate data
sources are used for different instructions
Chapter 4 — The Processor — 17
R-Type/Load/Store Datapath
Chapter 4 — The Processor — 18
Full Datapath
Chapter 4 — The Processor — 19
