Lecture Note 2: Von Neumann Computer Architecture and the IAS Machine

Introduction
The Von Neumann Architecture is the foundational design for most general-purpose computers.
Proposed in 1945 by John Von Neumann, it describes how a computer should execute instructions
and process data using a simple, flexible model. This architecture introduced the stored-program
concept, which transformed computing from hardwired systems to programmable systems.

Rationale Behind the Von Neumann Architecture

a. Problem with Early Computers
Before 1945, computers like the ENIAC used hardwired programs. Programs were physically built
into the machine using switches and cables. To change a program, the entire machine had to be
rewired manually, which was slow, error-prone, and not scalable.

b. Von Neumann’s Proposal

John Von Neumann proposed that a computer should store both instructions and data in the same
memory. Programs could be loaded from memory and executed step-by-step by the CPU. This
would make the computer reprogrammable, flexible, and general-purpose.

Core Concepts of the Von Neumann Model

a. Stored Program Concept
Both instructions and data are stored in memory. The CPU retrieves and executes instructions
from memory sequentially. Programs can be changed without altering hardware.

b. Instruction Execution Cycle (Fetch–Decode–Execute)

1. Fetch the instruction from memory.
2. Decode it to understand the operation and operands.
3. Execute the instruction.
4. Repeat until the program ends.

The IAS Computer (1946)

The IAS computer was built by Von Neumann and colleagues at the Institute for Advanced Study
(IAS), Princeton, in 1946. It was the first implementation of the Von Neumann architecture and
served as a prototype for many future machines (like the IBM 701, UNIVAC, and others).

Structure of the IAS Machine

Figure 2.1 shows the structure of the IAS computer. It consists of:

1
- Main Memory: Stored both data and program instructions. It had 1,024 words of 40 bits
each.
- Arithmetic Logic Unit (ALU): Performed arithmetic and logical operations on binary data.
- Control Unit: which interprets the instructions in memory and causes them to be executed
- Registers: Temporary data holders used during execution (e.g., AC, MQ, MBR, MAR, IR, PC).
- System Bus: A single bus used to transfer both instructions and data.
- Input/Output: Managed communication with external devices under the directive of
control unit.

Figure 2.1 IAS Structure

2
The memory of the IAS consists of 4,096 storage locations, called words , of 40 binary digits (bits)
each.6 Both data and instructions are stored there. Numbers are represented in binary form, and
each instruction is a binary code. Figure 2.2 illustrates these formats. Each number is represented
by a sign bit and a 39-bit value. A word may alternatively contain two 20-bit instructions, with
each instruction consisting of an 8-bit operation code (opcode ) specifying the operation to be
performed and a 12-bit address designating one of the words in memory (numbered from 0 to
999). Figure 2.3 shows the IAS instruction set.

Figure 2.2 IAS Memory

Format

The IAS computer had a total of 21 instructions, which are shown in Figure 2.3. These can be grouped as
follows:

• Data transfer: Move data between memory and ALU registers or between two ALU registers.

Unconditional branch: Normally, the control unit executes instructions in sequence from memory. This
sequence can be changed by a branch instruction, which facilitates repetitive operations.

• Conditional branch: The branch can be made dependent on a condition, thus allowing decision points.

• Arithmetic: Operations performed by the ALU.

• Address modify: Permits addresses to be computed in the ALU and then inserted into instructions
stored in memory. This allows a program considerable addressing flexibility.

Figure 2.3 presents instructions in a symbolic, easy-to-read form. Actually, each instruction must conform
to the format of Figure 2.2b. The opcode portion (first 8 bits) specifies which of the 21 instructions is to be
executed. The address portion (remaining 12 bits) specifies which of the 4,096 memory locations is to be
involved in the execution of the instruction.

3
Figure 2.3 IAS Instruction Set

Instruction Fetch- Decode and Execute Cycle of IAS

The control unit operates the IAS by fetching instructions from memory and executing them one
at a time. We explain these operations with reference to Figure 2. 1. This figure reveals that both
the control unit and the ALU contain storage locations, called registers, defined as follows:
• Memory buffer register (MBR): Contains a word to be stored in memory or sent to the I/O
unit, or is used to receive a word from memory or from the I/O unit.
Memory address register (MAR): Specifies the address in memory of the word to be written
from or read into the MBR.
Instruction register (IR): Contains the 8-bit opcode instruction being executed.
Instruction buffer register (IBR): Employed to hold temporarily the right-hand instruction from a
word in memory.
Program counter (PC): Contains the address of the next instruction pair to be fetched from
memory.

4
 Accumulator (AC) and multiplier quotient (MQ): Employed to hold temporarily operands and
results of ALU operations. For example, the result of multiplying two 40-bit numbers is an 80-bit
number; the most significant 40 bits are stored in the AC and the least significant in the MQ.

The IAS machine processes instructions using the fetch–decode–execute cycle. Each instruction
is 20 bits long, and two instructions are stored in each 40-bit memory word (left and right) as
shown in Figure 2.2.

Cycle Stages (General)1

1. Fetch:
The Program Counter (PC) points to the address of the next memory word containing a pair of
instructions.
The address is copied to the Memory Address Register (MAR).
MAR ← PC
The 40-bit word is fetched from memory into the Memory Buffer Register (MBR).

MBR ← M(MAR)

The left instruction is moved to the Instruction Register (IR).

IR ← MBR (0:7)

The right instruction is moved to the Instruction Buffer Register (IBR).

IBR ← MBR (20:39)

PC is incremented to point to the next instruction word.

PC ← PC + 1
2. Decode:
o The opcode in the IR is decoded.
o The memory address is identified.
3. Execute:
o Based on the instruction, data is fetched/stored using the AC (Accumulator), MQ,
MBR, and MAR.
o Arithmetic operations are performed using the ALU.
o If an instruction exists in the IBR, it is transferred to the IR and executed next
otherwise it fetch next instruction based on content of the PC

1
M(X) = contents of memory location whose address is X

(i:j) = bits i through j (i:j) = bits i through j]

5
Program Example: Add Two Numbers and Output the Result
Write an IAS-style program to:

1. Load a number from memory location 100.

2. Add a number from memory location 101.
3. Store the result into memory location 102.
4. Output the result.

Assumed Memory Contents (Before Execution)

Address Content
100 First number (e.g., 12)
101 Second number (e.g., 8)
102 — (Result will be stored here)
200 Program starts here

Sample IAS Program Instructions

Address Left Instruction Right Instruction
(0:19) (20:39)
200 LOAD M(100) ADD M(101)
201 STOR M(102) OUTPUT
202 HALT —

 Each instruction is 20 bits: 8-bit opcode + 12-bit address

 For simplicity, opcodes are written as mnemonics.

Step-by-Step Fetch–Decode–Execute Walkthrough

Step 1: Fetch Instructions from Address 200

 PC ← 200
 MAR ← PC
 MBR ← M(MAR) i.e MBR ← Memory[200] i.e. instruction: (LOAD M(100), ADD
M(101)) . Meaning content of memory location inside MAR put into MBR
 IR ← MBR (0:7) i.e left instruction from MBR store into IR : IR ← LOAD M(100)
 IBR ← MBR (20:39) i.e right instruction from MBR store into IR IR ← ADD M(101)
 PC ← 201

Step 2: Decode & Execute LOAD M(100)

 IR = LOAD 100
 MAR ← 100 executing LOAD instruction causes address 100 to be loaded to MAR
 MBR ←M(MAR) content of Memory[100] i.e value 12 is stored into MBR
 AC ← MBR i.e content of MBR stored into accumulator AC = 12

6
Step 3: Execute ADD M(101) (from IBR)

 IR ← IBR put next instruction from IBR to IR i,e IR← ADD M(101)
 MAR ← 101 executing ADD M(101) instruction causes address 101 to be loaded to
MAR
 MBR ← M(MAR) content of Memory[101] i.e value 8 is stored into MBR
 AC ← AC + MBR add content of MBR to the accumulator i.e AC← 12 + 8 i.e AC←20

Step 4: Fetch Instructions from Address 201

 PC = 201 fetch next instruction from memory 201 based on content of PC i.e PC=201
 MAR ← PC
 MBR ← M(MAR) i.e MBR ← Memory[201] (STORE M(102), OUTPUT ) meaning
content of memory address inside MAR put the content of that memory address into MBR
 IR ← MBR (0:7) i.e left instruction from MBR store into IR . IR ← STOR M(102)
 IBR ← MBR (20:39) i.e right instruction from MBR store into IBR. IBR← OUTPUT
 PC ← 202

Step 5: Execute STORE M(102)

 R ← STOR M(102)
 MAR ← 102 executing STOR M(102) instruction causes address 102 to be loaded to MAR
 MBR ← AC Put accumulator value 20 to MBR
 Memory[102] ← MBR Store content of MBR i.e 20 to memory location 102

Step 6: Execute OUTPUT

 Send value from AC = 20 to output device (screen/printer)

Step 7: Fetch HALT (Address 202)

 IR ← HALT → Execution stops.

Final Memory Content (After Execution)

Address Content

100 12

101 8

102 20 (result)

This example illustrates how the IAS machine:

 Uses PC, MAR, MBR, IR, IBR, AC to control instruction flow.

 Executes sequential instructions from memory in the Fetch–Decode–Execute cycle.
 Handles two instructions per memory word, improving efficiency.
 Stores and processes data using simple load-store-add-store-output pattern.
7
 Limitations of the Von Neumann Architecture

a. Von Neumann Bottleneck

Instructions and data share the same memory and bus. The CPU can only fetch either an
instruction or a data item at one time, which causes a performance bottleneck.

b. Performance Gap
Modern CPUs are very fast, but memory speed is comparatively slower. The CPU often idles while
waiting for data or instructions from memory.

Modern Modifications to the Von Neumann Architecture

- Split Caches (Modified Harvard Architecture): Separate Instruction and Data Caches allow
parallel access.
- Pipelining: Breaks execution into stages; multiple instructions are processed concurrently.
- Superscalar Execution: Multiple instructions are executed per clock cycle.
- Multicore Processors: Multiple cores allow true parallelism.
- Cache Hierarchy: L1, L2, and L3 caches reduce memory access delays.

Conclusion
The Von Neumann architecture, introduced in 1945 and first realized in the IAS computer, laid the
foundation for the modern digital computer. While the stored-program concept revolutionized
programming and general-purpose computing, the Von Neumann bottleneck became a major
performance limitation. Modern systems build on and enhance this model with techniques like
split caches, pipelining, superscalar execution, and multicore processing.

Essay Questions
1. Explain the main problem with early computers like the ENIAC and how Von Neumann's architecture
solved this issue.
2. Describe the stored-program concept and its impact on the flexibility and design of modern computers.
3. Discuss the Fetch–Decode–Execute cycle of the IAS computer and explain the function of each stage.
4. With the aid of a diagram or description, explain the roles of major registers (PC, IR, IBR, MAR, MBR, AC,
MQ) in the IAS computer.
5. Write a step-by-step execution of an IAS program that adds two numbers and outputs the result,
including register content changes.
6. What is the Von Neumann bottleneck? Explain how it limits computer performance and list any modern
solutions.
7. Compare and contrast the original Von Neumann architecture and its modern modifications such as
pipelining and split caches.
8
8. Describe the structure of the IAS computer and explain how it implements the Von Neumann
architecture principles.
9. Discuss the instruction format of the IAS machine, including the structure of a 40-bit word and how two
20-bit instructions are stored.
10. Highlight the advantages and limitations of the Von Neumann model in the context of contemporary
computing.

Multiple Choice Questions (MCQs)

1. Who proposed the stored-program concept in 1945?

A. Charles Babbage
B. Alan Turing
C. John Von Neumann
D. Ada Lovelace

2. In the Von Neumann model, both instructions and data are stored in:

A. ALU
B. Registers
C. Memory
D. Control Unit

3. What was the major drawback of early computers like ENIAC?

A. They were programmable

B. They could store data
C. Programs were hardwired
D. They used binary arithmetic

4. What does the control unit do in the Von Neumann architecture?

A. Stores data
B. Executes arithmetic operations
C. Directs instruction execution
D. Manages I/O operations

5. How many bits are in each word of IAS main memory?

A. 20
B. 32
C. 40
D. 64

6. What is the maximum number of instructions in an IAS word?

A. 1
B. 2
9
C. 3
D. 4

7. The Instruction Buffer Register (IBR) in IAS is used to:

A. Store the accumulator value

B. Store memory addresses
C. Temporarily hold the right instruction
D. Hold output values

8. What does the Program Counter (PC) hold?

A. The current instruction

B. The last output
C. Address of the next instruction
D. The opcode

9. What are AC and MQ used for in IAS?

A. Control signals
B. Program counters
C. Operand/result registers
D. Instruction decoding

10. What happens in the decode stage of the instruction cycle?

A. Instruction is executed
B. Operand is fetched
C. Opcode is interpreted
D. Data is stored

11. The MAR holds:

A. Instructions
B. Memory addresses
C. Data to be printed
D. Output instructions

12. The MBR receives data from:

A. PC
B. IR
C. Memory
D. ALU

13. Which register holds the current instruction being executed?

A. MAR
B. IR
C. MQ
D. AC
10
14. What is the function of the OUTPUT instruction in IAS?

A. Stop execution
B. Print PC value
C. Send AC value to output device
D. Store to memory

15. What is the function of the HALT instruction?

A. Output data
B. Clear memory
C. Stop execution
D. Restart PC

16. What is the Von Neumann bottleneck?

A. Lack of registers
B. Slow output devices
C. Shared bus for data and instructions
D. No cache memory

17. What improvement allows data and instruction to be accessed simultaneously?

A. ALU duplication
B. Dual-core processing
C. Split caches
D. Superscalar design

18. Which of these is a modern enhancement of Von Neumann architecture?

A. Hardwired logic
B. ENIAC framework
C. Pipelining
D. Vacuum tube circuits

19. Superscalar execution means:

A. One instruction per cycle

B. Several instructions in parallel
C. Instructions are stored twice
D. Cache memory is skipped

20. The use of multiple cores in CPUs helps to:

A. Increase instruction size

B. Slow down bottleneck
C. Enable true parallelism
D. Remove memory latency

11