Chapter 3

ASSEMBLY LEVEL MACHINE

ORGANIZATION

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 Basic organization of the
VON NEUMANN MACHINE

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• Virtually all computer designs are based on
concepts developed by John von Neumann.
Such design is referred to as the Von
Neumann Architecture and is based on three
key concepts.
1. Data and instructions are stored in a single
read-write memory
2. The contents of this memory are addressable
by location, without regard to the type of
data contained there.
3. Execution occurs in a sequential fashion
(unless explicitly modified) from one
instruction to the next.
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Von Neumann Structure

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• Several other components are needed to yield a
functioning computer.
• Data and instructions must be put into the system.
For this we need some sort of input module.
• This module contains basic components for
accepting data and instructions in some form and
converting them into an internal form of signals
usable by the system.
• A means of reporting results is needed, and this is
in the form of an output module.
• Taken together, these are referred to as I/O
components.
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• An input device will bring instructions and
data, in sequentially.
• But a program is not invariably executed
sequentially; it may jump around.
• There must be a place to store temporarily
both instructions and data. That module is
called memory (or main memory).
• Von Neumann pointed out that the same
memory could be used to store both the
instructions and data.

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The below figure illustrates the top-level components
and suggest the interactions among them.

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• The CPU exchanges data with memory. For this
purpose, it typically makes use of two internal registers:
MAR and MBR
• Memory Buffer Register (MBR) which contains the data
to be returned into (writing) memory or received data
(reading) from memory.
• Similarly an I/O address register (I/O AR) specifies a
particular I/O device.
• An I/O buffer register (I/O BR) is used for the exchange
of data between an I/O module and the CPU.
• A memory module consists of a set of locations, defined
by sequentially numbered address.
• An I/O module transfers data from external devices to
CPU and memory and vice versa. It contains internal
buffers for temporary holding these data until they can
be send on. 8
 CONTROL UNIT:
(Instruction Fetch, Decode, and
Execution)

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 1. Load the address of next instruction in the PC into the
MAR.
– So that the control unit can fetch the instruction from the right
part of the memory.
2. Copy the instruction/data that is in the memory
address given by the MAR into the MDR.
– MDR is used whenever anything is to go from the CPU to main
Fetch memory, or vice versa.
3. Increment the PC by 1.
– So that it contains the address of the next instruction, assuming
that the instructions are in consecutive locations.
4. Load the instruction/data that is now in the MDR into
the CIR.
– Thus the next instruction is copied from memory -> MDR -> CIR.
5. Contents of CIR split into operation code and address if
present e.g. store, add or jump instructions.
Decode 6. Decode the instruction that is in the CIR.
 6. Execute the instruction but what is involved in this
depends on the instruction being executed (there are
several different instructions you need to know about).

• If the instruction is a jump instruction then

– Load the address part of the instruction in the CIR into the PC.
• If the instruction is an input / load (directly) instruction
then take data input and place in accumulator.
• If the instruction is a load (from memory) instruction.
Ex ecute – Copy address part of the instruction (to load from) in the CIR
into MAR.
– Copy data from memory address held in MAR to MDR.
– Copy data in MDR into accumulator.
 • If the instruction is a store instruction then:
– Copy address part of the instruction (to store in) in the CIR into
MAR.
– Copy data in accumulator to MDR.
– Copy data in MDR into memory address held in MAR.
• If the instruction is an add instruction then:
– Copy address part of the instruction (of number to add) in the
CIR into MAR.
Ex ecute – Copy number from memory address held in MAR into MDR.
– Add number in MDR to number in accumulator (accumulator
will now hold the result).
• If the instruction is an output (directly from
accumulator) then output number in accumulator.
 • If the instruction is an output (from memory)
instruction then:
Ex ecute – Copy address part of part of the instruction (of data to output)
in CIR into MAR.
– Output contents of MDR.

7. Cycle is reset (restarted) by passing control back to

Reset the PC (step 1).
 The Fetch/Execute Cycle
• “Instruction Execution Engine”…a machine
that cycles through a series of operations
• Series is called: Fetch/Execute Cycle
– Get the next instruction
– Figure out what to do
– Gathering the data needed to do it
– Do it
– Save the result, and
– Repeat (billions of times/second)!
 A Five-Step Cycle
• These operations are repeated in a never-
ending sequence
• The step names suggest the operations
described in the previous paragraph
Principal Subsystems of a Computer
 The Fetch/Execute Cycle
• A five-step cycle:
1. Instruction Fetch (IF)
2. Instruction Decode (ID)
3. Data Fetch (DF) / Operand Fetch (OF)
4. Instruction Execution (EX)
5. Result Return (RR) / Store (ST)
 ADD 800, 428, 884

ADD the values found in memory locations 428 and

884 and store the result in location 800
 Instruction Fetch (IF)
• Execution begins by moving the instruction at
the address given by the PC (PC 2200) from
memory to the control unit
• Bits of instruction are placed into the decoder
circuit of the CU
• Once instruction is fetched, the PC can be
readied for fetching the next instruction
 IF

ADD 800, 428, 884

 Instruction Decode (ID)
• ALU is set up for the operation
• Decoder finds the memory address of the
instruction's data (source operands)
– Most instructions operate on two data values
stored in memory (like ADD), so most instructions
have addresses for two source operands
– These addresses are passed to the circuit that
fetches them from memory during the next step
 Instruction Decode (ID)
• Decoder finds the destination address for the
Result Return step and places the address in
the RR circuit
• Decoder determines what operation the ALU
will perform (ADD), and sets up the ALU
 ID

+ ADD 800 428 884

 Data Fetch (DF)
• The data values to be operated on are
retrieved from memory
• Bits at specified memory locations are copied
into locations in the ALU circuitry
• Data values remain in memory (they are not
destroyed)
DF

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 Instruction Execution (EX)
• For this ADD instruction, the addition circuit
adds the two source operands together to
produce their sum
• Sum is held in the ALU circuitry
• This is the actual computation
 EX

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 Return Result (RR)
• RR returns the result of EX to the memory
location specified by the destination address.
• Once the result is stored, the cycle begins
again
 RR

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 INSTRUCTION SETS AND TYPES:
(Data manipulation, Control, I/O)

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• The operation of the CPU is determined by
the instructions it executes, referred to as
machine instructions or computer
instructions.

• The collection of different instructions that

the CPU can execute is referred to as the
CPU’s instructions set.

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 Elements of an Instruction
• Each instruction must contain the information
required by the CPU for execution. These
information (or elements) are as follows:
– Opcode (Operation Code) specifies the
operation to be performed. (E.g. ADD,
MOV, LOAD, etc…).
– Operands: - specifies the inputs for the
operation. Instruction can normally have
one or two operands (source operand,
destination operand) and there are some
instructions with no operand also. 32
 Instruction Representation
• Within the computer, each instruction is
represented by a sequence of bits.
• During the execution of an instruction the
instruction is read into an instruction register
(IR) in the CPU.
• Then the CPU should be able to extract the
data from the various instructions to perform
the required operations.

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• It is very difficult to deal with the binary
representation of machine instructions. So we
will use a symbolic representation (or simply
assembly language) of machine instructions.

– ADD -for Addition operation

– SUB -for Subtraction
– MUL -for multiplication
– DIV -for Division
– MOV -moving data between registers or between
registers and memory
» and many more…………….

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 Instruction Types
• Data processing
• Data storage (main memory)
• Data movement (I/O)
• Program flow control
Instruction formats

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 Instruction Formats
• An instruction format defines the layout of
the bits of an instruction.
• An instruction format must include an opcode
and , implicitly or explicitly zero or more
operands.

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Simple Instruction Format
 Instruction Length
• The instruction format length affects and is
affected by memory size, memory
organization, bus structure, CPU complexity
and CPU speed.
• Programmers want more operands, opcodes,
addressing modes and greater address range.
• It may make life easier for the programmer
because shorter programs can be written to
accomplish given tasks greater.

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 5.2 Instruction
In designing Formats
an instruction set, consideration
is given to:
• Instruction length.
–Whether short, long, or variable.
• Number of operands.
• Number of addressable registers.
• Memory organization.
–Whether byte- or word addressable.
• Addressing modes.
–Choose any or all: direct, indirect or
indexed.
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Assembly/Machine Language
Programming

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 Assembly language
• The binary object file is the only form a
computer can be given software
• Computers can be programmed to translate
software expressed in other forms into binary
object code.
• This process includes as assembling.
 Constants
• Integer Constants
– Examples: –10, 42d, 10001101b, 0FF3Ah, 777o
– Radix: b = binary, d = decimal, h = hexadecimal, and o = octal
– If no radix is given, the integer constant is decimal
– A hexadecimal beginning with a letter must have a leading 0
• Character and String Constants
– Enclose character or string in single or double quotes
– Examples: 'A', "d", 'ABC', "ABC", '4096'
– Embedded quotes: "single quote ' inside", 'double quote "
inside'
– Each ASCII character occupies a single byte
 Instructions
• Assembly language instructions have the format:
[label:] mnemonic [operands]
[;comment]
• Instruction Label (optional)
– Marks the address of an instruction, must have a colon :
– Used to transfer program execution to a labeled instruction
• Mnemonic
– Identifies the operation (e.g. MOV, ADD, SUB, JMP, CALL)
• Operands
– Specify the data required by the operation
– Executable instructions can have zero to three operands
– Operands can be registers, memory variables, or constants
 Instruction Examples
• No operands
stc ; set carry flag
• One operand
inc eax ; increment register eax
call Clrscr ; call procedure Clrscr
jmp L1 ; jump to instruction with label
L1
• Two operands
add ebx, ecx ; register ebx = ebx + ecx
sub var1, 25 ; memory variable var1 =
var1 - 25
• Three operands
imul eax,ebx,5 ; register eax = ebx * 5
 Adding and Subtracting Integers
TITLE Add and Subtract (AddSub.asm)
; This program adds and subtracts 32-bit integers.
.686
.MODEL FLAT, STDCALL
.STACK
INCLUDE Irvine32.inc

.CODE
main PROC
mov eax,10000h ; EAX = 10000h
add eax,40000h ; EAX = 50000h
sub eax,20000h ; EAX = 30000h
call DumpRegs ; display registers
exit
main ENDP
END main
Addressing modes

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 Instruction Addressing
• Instruction addressing turns to the question of
“how” to specify the operands and opcodes of
an instruction and particularly how the address
of an operand is specified.
• We would like to refer a large range of locations
in main memory. To achieve this objective a
variety of addressing techniques have been
employed.

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 Addressing techniques:
–Immediate
–Direct
–Indirect
–Register
–Register Indirect
–Displacement
–Stack
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 Location 0 1 2 3 4 5

Value 17 3

1. Immediate = supplies the actual value and is

normally prefixed with a #.

• Load AX, #5 ;load actual value 5 in AX

• AX = 5 (5 is an operand)

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2. Direct = uses the number as a memory location
where the value is stored.
• Load AX, 5 ;Load the value in memory location 5 into the accumulator
• Ax becomes 3.
3. Indirect = uses the value as a memory location that
points to the memory location that holds the value.
In this case the number is usually enclosed with
square brackets.
• LD Acc, [5] ;Load the value stored in the memory location pointed to by
the operand into the accumulator
• Memory location 5 is accessed which contains 3. Memory location 3 is
accessed which is 17.
• Ax becomes 17.

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4. Register = operand is
held in register named
in address field.
Register have address
not content.

5. Register indirect =
operand is in memory
cell pointed to by
contents of register.

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6. Displacement = Combines
register indirect addressing
with direct addressing.

7. Stack = Operand is
(implicitly) on top of stack.

• e.g. PUSH, POP

 ADD (Pop top two items
from stack and add)

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Subroutine Call and Return
mechanisms

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 Subroutines
• A subroutine is a piece of program codes that
performs some particular functions.
– Function, Procedure, Method

• A subroutine must behave:

– in-line execution: flow naturally.
– no unintended side effects: must declare
explicitly which registers will be changed which
will be not after the call.
– multiple arguments: should allow a caller to pass
more than one argument.
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 Subroutine
• Thus, CPU must provide:
• Call/return mechanism.
– Save the address of the instruction being
executed (pc) of the caller so that, when return,
it can resume execution at the next instruction.
• A register protection mechanism.
– How to save the values of the register before the
call and restore the values back when returns
from calling.
• An argument passing convention.
– An agreement between caller and callee on how
arguments are to be passed.
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 Call/Return Mechanism
• Two special instructions: call and ret.
• Use “call” to call for a particular subroutine.
• Use “ret” to return from the subroutine.
• Both have a delay slot.

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 Subroutines

The Call / Return Mechanism

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I/O and interrupts

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 Interrupts
• Virtually all computers provide a mechanism
by which other modules (I/O, memory) may
interrupt the normal processing of the
processor.
• Interrupts provide primarily as a way to
improve processing efficiency.

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• For e.g.:
Suppose, the processor is transferring data to a
printer using the instruction cycle scheme.
(most external devices are much slower than the
processor).
After each write operation the processor must
pause and remain idle until the printer catches
up. The length of this pause may be on the order
of many hundreds or thousands instruction cycles
that do not involve memory.

Clearly this is a very wasteful use of the processor.

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 Interrupts and the instruction cycle
• With interrupts, the processor can be
engaged in executing other instructions while
an I/O operation is in progress.
• When an external device becomes ready to be
serviced, ie, when it is ready to accept more
data from the processor, the I/O module for
that external device sends an interrupt
request signal to the processor.
• The processor responds by suspending the
current program operation, branching off to a
program (known as interrupt handler) to serve
that particular I/O device’s request and
resuming the original execution after the
device is serviced. 62
• From the point of view of a user program, an
interrupt is just that; an interruption of the
normal sequence of executions.
• When interrupt processing is completed
execution resumes.
• The processor and the operating system are
responsible for suspending the user program
and then resuming it at the same point

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 I/O functions
 An I/O module (eg: a disk controller) can exchange
data directly with the processor.
 Just as the processor can initiate a read/write with
memory, the processor can also read data from or
write data to an I/O module.
 In some cases it is desirable to allow I/O exchanges to
occur directly with memory. In such a case the
processor grants the authority to read from or write to
memory to an I/O module, so that the I/O- memory
transfer can occur without tying up the processor.
 During such a transfer the I/O module issues read or
write commands to memory, relieving the processor of
responsibility for the exchange. This operation is known
as Direct Memory Access (DMA).
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 I/O Module
• There are 2 operations. Read and Write. We
can refer to each of the interfaces to an
external device as a port and give each a
unique address 0,1,2,3,……M-1.
• In addition there are external data paths for
the input and output data with an external
device.
• Finally an I/O module may be able to send
interrupt signals to the processor.

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END

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