a Active Energy Metering IC with

di/dt Sensor Interface

ADE7759*
FEATURES can be switched off if the ADE7759 is used with conventional
High Accuracy, Supports IEC 687/1036 current sensors.
On-Chip Digital Integrator Allows Direct Interface with
The ADE7759 contains a sampled waveform register and an
Current Sensors with di/dt Output Such as Rogowski Coil
active energy register capable of holding at least 11.53 seconds
Less Than 0.1% Error over a Dynamic Range of 1000 to 1
of accumulated power at full ac load. Data is read from the
On-Chip User-Programmable Threshold for Line Voltage
ADE7759 via the serial interface. The ADE7759 also provides a
SAG Detection and PSU Supervisory
pulse output (CF) with frequency that is proportional to the
Supplies Sampled Waveform Data and Active Energy
active power.
(40 Bits)
Digital Power, Phase, and Input DC Offset Calibration In addition to active power information, the ADE7759 also
On-Chip Temperature Sensor (Typical 1 LSB/
C Resolution) provides various system calibration features, i.e., channel offset
SPI Compatible Serial Interface correction, phase calibration, and power offset correction. The
Pulse Output with Programmable Frequency part also incorporates a detection circuit for short duration
Interrupt Request Pin (IRQ) and IRQ Status Register voltage drop (SAG). The voltage threshold and the duration (in
Proprietary ADCs and DSP provide High Accuracy over number of half-line cycles) of the drop are user programmable.
Large Variations in Environmental Conditions and Time An open-drain logic output (SAG) goes active low when a sag
Reference 2.4 V  8% (20 ppm/
C Typical) with External event occurs.
Overdrive Capability A zero crossing output (ZX) produces an output that is synchro-
Single 5 V Supply, Low Power Consumption (25 mW nized to the zero crossing point of the line voltage. This output
Typical) can be used to extract timing or frequency information from the
GENERAL DESCRIPTION line. The signal is also used internally to the chip in the line
The ADE7759 is an accurate active power and energy measure- cycle energy accumulation mode; i.e., the number of half-line
ment IC with a serial interface and a pulse output. The ADE7759 cycles in which the energy accumulation occurs can be con-
incorporates two second-order Σ-∆ ADCs, a digital integrator trolled. Line cycle energy accumulation enables a faster and
(on CH1), reference circuitry, temperature sensor, and all the more precise energy accumulation and is especially useful dur-
signal processing required to perform active power and energy ing calibration. This signal is also useful for synchronization of
measurement. relay switching with a voltage zero crossing.
An on-chip digital integrator allows direct interface to di/dt The interrupt request output is an open drain, active low logic
current sensors such as a Rogowski coil. The digital integrator output. The interrupt status register indicates the nature of the
eliminates the need for an external analog integrator and pro- interrupt, and the interrupt enable register controls which event
vides excellent long-term stability and precise phase matching produces an output on the IRQ pin. The ADE7759 is available
between the current and the voltage channels. The integrator in a 20-lead SSOP package.
FUNCTIONAL BLOCK DIAGRAM
AVDD RESET DVDD DGND

ADE7759
INTEGRATOR MULTIPLIER ZX
MULTIPLIER
V1P
ADC dt LPF2 SAG
V1N
HPF1

TEMP APGAIN[11:0] APOS[15:0]

SENSOR
PHCAL[7:0]
V2P
ADC  DFC
V2N
CFNUM[11:0]
4k CF
2.4V REGISTERS AND CFDEN[11:0]
REFERENCE SERIAL INTERFACE
LPF1

AGND REFIN/OUT DIN DOUT SCLK CS IRQ CLKIN CLKOUT

*U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com
registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2002 Analog Devices, Inc. All rights reserved.
ADE7759
TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 CHANNEL 1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 Channel 1 ADC Gain Adjust . . . . . . . . . . . . . . . . . . . . . . 18
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 Channel 1 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 CHANNEL 1 AND CHANNEL 2 WAVEFORM
TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5 SAMPLING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6 CHANNEL 2 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Channel 2 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PHASE COMPENSATION . . . . . . . . . . . . . . . . . . . . . . . . 19
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 7 ACTIVE POWER CALCULATION . . . . . . . . . . . . . . . . . 20
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ENERGY CALCULATION . . . . . . . . . . . . . . . . . . . . . . . . 21
MEASUREMENT ERROR . . . . . . . . . . . . . . . . . . . . . . . . . 8 Integration Time under Steady Load . . . . . . . . . . . . . . . . 22
PHASE ERROR BETWEEN CHANNELS . . . . . . . . . . . . . 8 POWER OFFSET CALIBRATION . . . . . . . . . . . . . . . . . . 22
POWER SUPPLY REJECTION . . . . . . . . . . . . . . . . . . . . . . 8 ENERGY-TO-FREQUENCY CONVERSION . . . . . . . . . 22
ADC OFFSET ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 LINE CYCLE ENERGY ACCUMULATION MODE . . . 24
GAIN ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 CALIBRATING THE ENERGY METER . . . . . . . . . . . . . 24
GAIN ERROR MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Calculating the Average Active Power . . . . . . . . . . . . . . . 24
TYPICAL PERFORMANCE CHARACTERISTICS (TPC) . . 9 Calibrating the Frequency at CF . . . . . . . . . . . . . . . . . . . 25
TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Energy Meter Display . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ANALOG INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 CLKIN FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
di/dt CURRENT SENSOR AND DIGITAL SUSPENDING THE ADE7759 FUNCTIONALITY . . . . 26
INTEGRATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . . 26
ZERO CROSSING DETECTION . . . . . . . . . . . . . . . . . . . 13 SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LINE VOLTAGE SAG DETECTION . . . . . . . . . . . . . . . . 14 Serial Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Sag Level Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Serial Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
POWER SUPPLY MONITOR . . . . . . . . . . . . . . . . . . . . . . 14 CHECKSUM REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . 28
INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . 30
Using the ADE7759 Interrupts with an MCU . . . . . . . . . 15 Communications Register . . . . . . . . . . . . . . . . . . . . . . . . 30
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Mode Register (06H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TEMPERATURE MEASUREMENT . . . . . . . . . . . . . . . . 16 Interrupt Status Register (04H) . . . . . . . . . . . . . . . . . . . . 32
ANALOG-TO-DIGITAL CONVERSION . . . . . . . . . . . . . 16 Reset Interrupt Status Register (05H) . . . . . . . . . . . . . . . 32
Antialias Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 CH1OS Register (08H) . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . 17 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

–2– REV. A
 ADE7759
SPECIFICATIONS1 (AVT to=TDV ==–40C
5 V
5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL,
DD
MIN
DD
to +85C, unless otherwise noted.)
MAX

Parameter Spec Unit Test Conditions/Comments

ENERGY MEASUREMENT ACCURACY
Measurement Bandwidth 14 kHz CLKIN = 3.579545 MHz
Measurement Error1 on Channel 1 Channel 2 = 300 mV rms/60 Hz, Gain = 1
Channel 1 Range = 0.5 V Full-Scale
Gain = 1 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 2 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 4 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 8 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 16 0.2 % typ Over a Dynamic Range 1000 to 1
Channel 1 Range = 0.25 V Full-Scale
Gain = 1 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 2 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 4 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 8 0.2 % typ Over a Dynamic Range 1000 to 1
Gain = 16 0.2 % typ Over a Dynamic Range 1000 to 1
Channel 1 Range = 0.125 V Full-Scale
Gain = 1 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 2 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 4 0.2 % typ Over a Dynamic Range 1000 to 1
Gain = 8 0.2 % typ Over a Dynamic Range 1000 to 1
Gain = 16 0.4 % typ Over a Dynamic Range 1000 to 1
Phase Error1 between Channels ± 0.05 ∞ max Line Frequency = 45 Hz to 65 Hz, HPF on
AC Power Supply Rejection1 AVDD = DVDD = 5 V + 175 mV rms/120 Hz
Output Frequency Variation (CF) 0.2 % typ Channel 1 = 20 mV rms/60 Hz, Gain = 16, Range = 0.5 V
Channel 2 = 300 mV rms/60 Hz, Gain = 1
DC Power Supply Rejection1 AVDD = DVDD = 5 V ± 250 mV dc
Output Frequency Variation (CF) ± 0.3 % typ Channel 1 = 20 mV rms/60 Hz, Gain = 16, Range = 0.5 V
Channel 2 = 300 mV rms/60 Hz, Gain = 1
ANALOG INPUTS3
Maximum Signal Levels ± 0.5 V max V1P, V1N, V2N, and V2P to AGND
Input Impedance (DC) 390 kW min
Bandwidth 14 kHz CLKIN/256, CLKIN = 3.579545 MHz
Gain Error1, 3 External 2.5 V Reference, Gain = 1 on Channels 1 and 2
Channel 1
Range = 0.5 V Full-Scale ±4 % typ V1 = 0.5 V dc
Range = 0.25 V Full-Scale ±4 % typ V1 = 0.25 V dc
Range = 0.125 V Full-Scale ±4 % typ V1 = 0.125 V dc
Channel 2 ±4 % typ V2 = 0.5 V dc
Gain Error Match1 External 2.5 V Reference
Channel 1
Range = 0.5 V Full-Scale ± 0.3 % typ Gain = 1, 2, 4, 8, 16
Range = 0.25 V Full-Scale ± 0.3 % typ Gain = 1, 2, 4, 8, 16
Range = 0.125 V Full-Scale ± 0.3 % typ Gain = 1, 2, 4, 8, 16
Channel 2 ± 0.3 % typ Gain = 1, 2, 4, 8, 16
Offset Error1
Channel 1 ± 20 mV max Gain = 1
Channel 2 ± 20 mV max Gain = 1
WAVEFORM SAMPLING Sampling CLKIN/128, 3.579545 MHz/128 = 27.9 kSPS
Channel 1 See Channel 1 Sampling
Signal-to-Noise plus Distortion 62 dB typ 150 mV rms/60 Hz, Range = 0.5 V, Gain = 2
Bandwidth (–3 dB) 14 kHz CLKIN = 3.579545 MHz
Channel 2 See Channel 2 Sampling
Signal-to-Noise plus Distortion 52 dB typ 150 mV rms/60 Hz, Gain = 2
Bandwidth (–3 dB) 156 Hz CLKIN = 3.579545 MHz

REV. A –3–
ADE7759–SPECIFICATIONS (continued)
Parameter Spec Unit Test Conditions/Comments
REFERENCE INPUT
REFIN/OUT Input Voltage Range 2.6 V max 2.4 V + 8%
2.2 V min 2.4 V – 8%
Input Capacitance 10 pF max
ON-CHIP REFERENCE Nominal 2.4 V at REFIN/OUT Pin
Reference Error ± 200 mV max
Current Source 10 mA max
Output Impedance 4 kW min
Temperature Coefficient 20 ppm/∞C typ
CLKIN Note All Specifications CLKIN of 3.579545 MHz
Input Clock Frequency 4 MHz max
1 MHz min
LOGIC INPUTS
RESET, DIN, SCLK, CLKIN, and CS
Input High Voltage, VINH 2.4 V min DVDD = 5 V ± 5%
Input Low Voltage, VINL 0.8 V max DVDD = 5 V ± 5%
Input Current, IIN ±3 mA max Typically 10 nA, VIN = 0 V to DVDD
Input Capacitance, CIN 10 pF max
LOGIC OUTPUTS
SAG and IRQ Open Drain Outputs, 10 kW pull-up resistor
Output High Voltage, VOH 4 V min ISOURCE = 5 mA
Output Low Voltage, VOL 0.4 V max ISINK = 0.8 mA
ZX and DOUT
Output High Voltage, VOH 4 V min ISOURCE = 5 mA
Output Low Voltage, VOL 0.4 V max ISINK = 0.8 mA
CF
Output High Voltage, VOH 4 V min ISOURCE = 5 mA
Output Low Voltage, VOL 1 V max ISINK = 7 mA
POWER SUPPLY For Specified Performance
AVDD 4.75 V min 5 V – 5%
5.25 V max 5 V + 5%
DVDD 4.75 V min 5 V – 5%
5.25 V max 5 V + 5%
AIDD 3 mA max Typically 2.0 mA
DIDD 4 mA max Typically 3.0 mA
NOTES
1
See Terminology section for explanation of specifications.
2
See plots in Typical Performance Characteristics.
3
See Analog Inputs section.
Specifications subject to change without notice.

–4– REV. A
 ADE7759
(AVDD = DVDD = 5 V
5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz
TIMING CHARACTERISTICS1, 2 XTAL, TMIN to TMAX = –40C to +85C, unless otherwise noted.)
Parameter A, B Versions Unit Test Conditions/Comments
Write Timing
t1 20 ns (min) CS Falling Edge to First SCLK Falling Edge
t2 150 ns (min) SCLK Logic High Pulsewidth
t3 150 ns (min) SCLK Logic Low Pulsewidth
t4 10 ns (min) Valid Data Setup Time before Falling Edge of SCLK
t5 5 ns (min) Data Hold Time after SCLK Falling Edge
t6 6.4 ms (min) Minimum Time between the End of Data Byte Transfers
t7 4 ms (min) Minimum Time between Byte Transfers during a Serial Write
t8 100 ns (min) CS Hold Time after SCLK Falling Edge
Read Timing
t9 4 ms (min) Minimum Time between Read Command (i.e., a Write to Communications
Register) and Data Read
t10 4 ms (min) Minimum Time between Data Byte Transfers during a Multibyte Read
t113 30 ns (min) Data Access Time after SCLK Rising Edge following a Write to the Communica-
tions Register
t124 100 ns (max) Bus Relinquish Time after Falling Edge of SCLK
10 ns (min)
t134 100 ns (max) Bus Relinquish Time after Rising Edge of CS
10 ns (min)
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns
(10% to 90%) and timed from a voltage level of 1.6 V.
2
See Figures 2 and 3 and Serial Interface section of this data sheet.
3
Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.

200A IOL

TO
OUTPUT 2.1V
PIN CL
50pF

1.6mA IOH

Figure 1. Load Circuit for Timing Specifications

t8
CS
t1 t2 t3 t6
t7 t7
SCLK
t4
t5
DIN 1 0 0 A4 A3 A2 A1 A0 DB7 DB0 DB7 DB0

COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE

Figure 2. Serial Write Timing

CS
t1 t 13
t9 t 10
SCLK

DIN 0 0 0 A4 A3 A2 A1 A0

t 11 t 11 t 12

DOUT DB7 DB0 DB7 DB0

COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE

Figure 3. Serial Read Timing

REV. A –5–
ADE7759
ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE
(TA = 25∞C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Model Package Option*
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V ADE7759ARS RS-20
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V ADE7759ARSRL RS-20
Analog Input Voltage to AGND EVAL-ADE7759EB ADE7759 Evaluation Board
V1P, V1N, V2P, and V2N . . . . . . . . . . . . . . . . –6 V to +6 V
Reference Input Voltage to AGND . . –0.3 V to AVDD + 0.3 V *RS = Shrink Small Outline Package in tubes; RSRL = Shrink Small
Outline Package in reel.
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C
20-Lead SSOP, Power Dissipation . . . . . . . . . . . . . . . 450 mW
qJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 112∞C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the ADE7759 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.

–6– REV. A
 ADE7759
PIN CONFIGURATION

RESET 1 20 DIN

DVDD 2 19 DOUT
AVDD 3 18 SCLK
V1P 4 17 CS
V1N 5 ADE7759 16 CLKOUT
V2N 6 TOP VIEW 15 CLKIN
(Not to Scale)
V2P 7 14 IRQ

AGND 8 13 SAG

REFIN/OUT 9 12 ZX
DGND 10 11 CF

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 RESET Reset Pin for the ADE7759. A logic low on this pin will hold the ADCs and digital circuitry
(including the serial interface) in a reset condition.
2 DVDD Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7759.
The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be
decoupled to DGND with a 10 mF capacitor in parallel with a ceramic 100 nF capacitor.
3 AVDD Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7759.
The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made
to minimize power supply ripple and noise at this pin by the use of proper decoupling method.
This pin should be decoupled to AGND with a 10 mF capacitor in parallel with a ceramic 100 nF
capacitor.
4, 5 V1P, V1N Analog Inputs for Channel 1. This channel is intended for use with the di/dt current transducers
such as Rogowski coil, or other current sensors such as shunt or current transformer (CT). These
inputs are fully differential voltage inputs with maximum differential input signal levels of ± 0.5 V,
± 0.25 V, and ± 0.125 V, depending on the full-scale selection—see Analog Inputs section.
Channel 1 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these
pins with respect to AGND is ± 0.5 V. Both inputs have internal ESD protection circuitry. In addi-
tion, an overvoltage of ± 6 V can be sustained on these inputs without risk of permanent damage.
6, 7 V2N, V2P Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These inputs
are fully differential voltage inputs with a maximum differential signal level of ± 0.5 V. Channel 2
also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins
with respect to AGND is ± 0.5 V. Both inputs have internal ESD protection circuitry, and an over-
voltage of ± 6 V can be sustained on these inputs without risk of permanent damage.
8 AGND This pin provides the ground reference for the analog circuitry in the ADE7759, i.e., ADCs and
reference. This pin should be tied to the analog ground plane or the quietest ground reference in
the system. This quiet ground reference should be used for all analog circuitry, e.g., antialiasing
filters, current and voltage transducers. To keep ground noise around the ADE7759 to a minimum,
the quiet ground plane should be connected to the digital ground plane at only one point. It is
acceptable to place the entire device on the analog ground plane—see Application Information section.
9 REFIN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal
value of 2.4 V ± 8% and a typical temperature coefficient of 20 ppm/∞C. An external reference
source may be connected at this pin. In either case, this pin should be decoupled to AGND with
a 1 mF capacitor in parallel with a 100 nF capacitor.
10 DGND This provides the ground reference for the digital circuitry in the ADE7759, i.e., multiplier, filters,
and frequency output (CF). Because the digital return currents in the ADE7759 are small, it is
acceptable to connect this pin to the analog ground plane of the system—see Application Information
section. However, high bus capacitance on the DOUT pin may result in noisy digital current that
affects performance.
11 CF Calibration Frequency Logic Output. The CF logic output gives Active Power information. This
output is intended to be used for operational and calibration purposes. The full-scale output fre-
quency can be adjusted by writing to the APGAIN, CFNUM, and CFDEN registers—see Energy
to Frequency Conversion section.

REV. A –7–
ADE7759
PIN FUNCTION DESCRIPTIONS (continued)
Pin No. Mnemonic Description
12 ZX Voltage Waveform (Channel 2) Zero Crossing Output. This output toggles logic high and low at
the zero crossing of the differential signal on Channel 2—see Zero Crossing Detection section.
13 SAG This open-drain logic output goes active low when either no zero crossings are detected or a low
voltage threshold (Channel 2) is crossed for a specified duration—see Line Voltage Sag Detec-
tion section.
14 IRQ Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts
include active energy register rollover, active energy register at half-full, zero crossing, SAG, and
arrivals of new waveform samples—see Interrupts section.
15 CLKIN Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this
logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and
CLKOUT to provide a clock source for the ADE7759. The clock frequency for specified opera-
tion is 3.579545 MHz. Ceramic load capacitors of between 10 pF and 30 pF should be used with
the gate oscillator circuit. Refer to crystal manufacturer’s data sheet for load capacitance requirements.
16 CLKOUT A crystal can be connected across this pin and CLKIN as described above to provide a clock source
for the ADE7759. The CLKOUT pin can drive one CMOS load when either an external clock is
supplied at CLKIN or a crystal is being used.
17 CS Chip Select. Part of the 4-wire SPI serial interface. This active low logic input allows the ADE7759 to
share the serial bus with several other devices—see Serial Interface section.
18 SCLK Serial Clock Input for the Synchronous serial interface. All serial data transfers are synchronized to
this clock—see Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock
source that has a slow edge transition time, e.g., opto-isolator outputs.
19 DOUT Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK.
This logic output is normally in a high impedance state unless it is driving data onto the serial data
bus—see Serial Interface section.
20 DIN Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK—see
Serial Interface section.

TERMINOLOGY nominal supplies (5 V) is taken. A second reading is obtained

with the same input signal levels when the supplies are varied ± 5%.
MEASUREMENT ERROR Any error introduced is again expressed as a percentage of reading.
The error associated with the energy measurement made by the
ADE7759 is defined by the following formula: ADC OFFSET ERROR
This refers to the dc offset associated with the analog inputs to
Percentage Error = the ADCs. It means that with the analog inputs connected to
Energy registered by the ADE 7759 – True Energy AGND, the ADCs still see a dc analog input signal. The magni-
True Energy tude of the offset depends on the gain and input range selection—see
Typical Performance Characteristics. However, when HPF1 is
switched on, the offset is removed from Channel 1 (current) and
PHASE ERROR BETWEEN CHANNELS the power calculation is not affected by this offset. The offsets
The digital integrator and the HPF1 (High-Pass Filter) in may be removed by performing an offset calibration—see Analog
Channel 1 have nonideal phase response. To offset this phase Inputs section.
response and equalize the phase response between channels, two
phase correction networks are placed in Channel 1: one for the GAIN ERROR
digital integrator and the other for the HPF1. Each phase cor- The gain error in the ADE7759 ADCs is defined as the difference
rection network corrects the phase response of the corresponding between the measured ADC output code (minus the offset)
component and ensures a phase match between Channel 1 and the ideal output code—see Channel 1 ADC and Channel
(current) and Channel 2 (voltage) to within ± 0.1∞ over a range 2 ADC. It is measured for each of the input ranges on Channel
of 45 Hz to 65 Hz and ± 0.2∞ over a range 40 Hz to 1 kHz. 1 (0.5 V, 0.25 V, and 0.125 V). The difference is expressed as a
percentage of the ideal code.
POWER SUPPLY REJECTION
This quantifies the ADE7759 measurement error as a percent- GAIN ERROR MATCH
age of reading when the power supplies are varied. The Gain Error Match is defined as the gain error (minus the
For the ac PSR measurement, a reading at nominal supplies offset) obtained when switching between a gain of 1 (for each of
(5 V) is taken. A second reading is obtained with the same input the input ranges) and a gain of 2, 4, 8, or 16. It is expressed as a
signal levels when an ac (175 mV rms/120 Hz) signal is intro- percentage of the output ADC code obtained under a gain of 1.
duced onto the supplies. Any error introduced by this ac signal This gives the gain error observed when the gain selection is
is expressed as a percentage of reading—see Measurement Error changed from 1 to 2, 4, 8, or 16.
definition above. For the dc PSR measurement a reading at
–8– REV. A
 Typical Performance Characteristics–ADE7759
0.5 0.5
FULL SCALE = 0.5V
0.4 0.4 GAIN = 1
–40
C, PF = 1 INTEGRATOR OFF
0.3 0.3 INTERNAL REFERENCE
+85
C, PF = 1 +85
C, PF = 0.5
0.2 0.2 –40
C, PF = 0.5
ERROR – %

ERROR – %
0.1 0.1

0.0 0.0

–0.1 –0.1
+25
C, PF = 1 +25
C, PF = 0.5 +25
C, PF = 1
–0.2 –0.2
FULL SCALE = 0.5V
–0.3 –0.3
GAIN = 1
INTEGRATOR OFF
–0.4 –0.4
INTERNAL REFERENCE
–0.5 –0.5
0.01 0.1 1 10 100 0.01 0.1 1 10 100
CURRENT – A CURRENT – A

TPC 1. Error as a % of Reading TPC 4. Error as a % of Reading

0.5 0.5
FULL SCALE = 0.5V
0.4 0.4 GAIN = 1
–40
C, PF = 1 INTEGRATOR OFF –40
C, PF = 0.5
0.3 0.3 EXTERNAL REFERENCE

0.2 +25
C, PF = 1 0.2

+25
C, PF = 1
ERROR – %

0.1
ERROR – %
0.1

0.0 0.0

–0.1 –0.1

–0.2 +85
C, PF = 1 –0.2 +25
C, PF = 0.5

+85
C, PF = 0.5
FULL SCALE = 0.5V
–0.3 –0.3
GAIN = 1
INTEGRATOR OFF
–0.4 –0.4
EXTERNAL REFERENCE
–0.5 –0.5
0.01 0.1 1 10 100 0.01 0.1 1 10 100
CURRENT – A CURRENT – A

TPC 2. Error as a % of Reading TPC 5. Error as a % of Reading

0.5 0.5

0.4 0.4 +85
C, PF = 0.5

–40
C, PF = 1
0.3 0.3
–40
C, PF = 0.5
0.2 0.2
+25
C, PF = 1
ERROR – %

ERROR – %

0.1 0.1
+85
C, PF = 1
0.0 0.0

–0.1 +25
C, PF = 1 –0.1

–0.2 –0.2
FULL SCALE = 0.5V FULL SCALE = 0.5V
–0.3 –0.3
GAIN = 4 GAIN = 4
INTEGRATOR OFF INTEGRATOR OFF
–0.4 –0.4
INTERNAL REFERENCE +25
C, PF = 0.5 INTERNAL REFERENCE
–0.5 –0.5
0.01 0.1 1 10 100 0.01 0.1 1 10 100
CURRENT – A CURRENT – A

TPC 3. Error as a % of Reading TPC 6. Error as a % of Reading

REV. A –9–
ADE7759
0.5 0.5
FULL SCALE = 0.5V
0.4 0.4 +85
C, PF = 0.5 GAIN = 4
INTEGRATOR OFF
0.3 0.3
EXTERNAL REFERENCE
–40
C, PF = 1
0.2 0.2 +25
C, PF = 1
+25
C, PF = 1
ERROR – %

ERROR – %
0.1 0.1

0.0 0.0
–40
C, PF = 0.5
–0.1 –0.1

–0.2 +85
C, PF = 1 –0.2 +25
C, PF = 0.5

FULL SCALE = 0.5V
–0.3 –0.3
GAIN = 4
INTEGRATOR OFF
–0.4 –0.4
EXTERNAL REFERENCE
–0.5 –0.5
0.01 0.1 1 10 100 0.01 0.1 1 10 100
CURRENT – A CURRENT – A

TPC 7. Error as a % of Reading TPC 10. Error as a % of Reading

0.5 1.5
FULL SCALE = 0.5V
0.4 1.3 GAIN = 4
INTEGRATOR ON
0.3 1.1
INTERNAL REFERENCE
0.2 –40
C, PF = 1 0.9
+25
C, PF = 1
0.7
ERROR – %
ERROR – %

0.1
–40
C, PF = 0.5
0.0 0.5
+85
C, PF = 0.5
–0.1 0.3
+25
C, PF = 1
+85
C, PF = 1 0.1
–0.2
FULL SCALE = 0.5V
–0.3 –0.1
GAIN = 4
INTEGRATOR ON +25
C, PF = 0.5
–0.4 –0.3
INTERNAL REFERENCE
–0.5 –0.5
0.01 0.1 1 10 100 0.01 0.1 1 10 100
CURRENT – A CURRENT – A

TPC 8. Error as a % of Reading TPC 11. Error as a % of Reading

0.5 1.5
FULL SCALE = 0.5V FULL SCALE = 0.5V
0.4 GAIN = 4 1.3 GAIN = 4
INTEGRATOR ON INTEGRATOR ON
0.3 EXTERNAL REFERENCE 1.1 EXTERNAL REFERENCE
–40
C, PF = 1
0.2 0.9
+85
C, PF = 0.5
+25
C, PF = 1 0.7
ERROR – %

ERROR – %

0.1

0.0 0.5
–40
C, PF = 0.5
–0.1 0.3

–0.2 0.1 +25
C, PF = 1

+85
C, PF = 1
–0.3 –0.1

–0.4 –0.3 +25
C, PF = 0.5

–0.5 –0.5
0.01 0.1 1 10 100 0.01 0.1 1 10 100
CURRENT – A CURRENT – A

TPC 9. Error as a % of Reading TPC 12. Error as a % of Reading

–10– REV. A
 ADE7759
Test Circuits VDD VDD

I
10F 100nF 100nF 10F I 10F 100nF 100nF 10F

AVDD DVDD RESET di/dt CURRENT

AVDD DVDD RESET
SENSOR
1k DIN 100 1k DIN
V1P V1P
33nF DOUT TO SPI BUS 33nF 33nF DOUT TO SPI BUS
RB (USED ONLY FOR (USED ONLY FOR
1k SCLK CALIBRATION) 100 1k SCLK CALIBRATION)
V1N U1 V1N U1
33nF CS 33nF 33nF CS
ADE7759 ADE7759
CLKOUT CLKOUT
V2N Y1 22pF Y1 22pF
V2N
1k 33nF 3.58MHz 1k 33nF 3.58MHz
CLKIN CLKIN
22pF 22pF
600k 600k
V2P V2P
IRQ IRQ
110V 1k 33nF 110V 1k 33nF
SAG NOT CONNECTED SAG NOT CONNECTED
ZX ZX
REFIN/OUT REFIN/OUT
10F 100nF CF U3 100nF CF U3
10F
AGND DGND TO AGND DGND
CT TURN RATIO = 1800:1 TO
FREQUENCY CHANNEL 1 GAIN = 4 FREQUENCY
CHANNEL 2 GAIN = 1
COUNTER CHANNEL 2 GAIN = 1 COUNTER
GAIN (CH1) RB
1 10
4 2.5 PS2501-1 PS2501-1

Test Circuit 1. Performance Curve (Integrator OFF) Test Circuit 2. Performance Curve (Integrator ON)

ANALOG INPUTS In addition to the PGA, Channel 1 also has a full-scale input
The ADE7759 has two fully differential voltage input channels. range selection for the ADC. The ADC analog input range
The maximum differential input voltage for input pairs V1P/V1N selection is also made using the gain register—see Figure 5. As
and V2P/V2N are ± 0.5 V. In addition, the maximum signal mentioned previously the maximum differential input voltage is
level on analog inputs for V1P/V1N and V2P/V2N are ± 0.5 V 0.5 V. However, by using Bits 3 and 4 in the gain register, the
with respect to AGND. maximum ADC input voltage can be set to 0.5 V, 0.25 V, or
Each analog input channel has a PGA (Programmable Gain 0.125 V. This is achieved by adjusting the ADC reference—see
Amplifier) with possible gain selections of 1, 2, 4, 8, and 16. The Reference Circuit section. Table I summarizes the maximum
gain selections are made by writing to the gain register—see differential input signal level on Channel 1 for the various ADC
Figure 5. Bits 0 to 2 select the gain for the PGA in Channel 1 and range and gain selections.
the gain selection for the PGA in Channel 2 is made via Bits 5
to 7. Figure 4 shows how a gain selection for Channel 1 Table I. Maximum Input Signal Levels for Channel 1
is made using the gain register. Max Signal ADC Input Range Selection
GAIN[7:0]
Channel 1 0.5 V 0.25 V 0.125 V
0.5 V Gain = 1
0.25 V Gain = 2 Gain = 1
GAIN (K) 0.125 V Gain = 4 Gain = 2 Gain = 1
SELECTION 0.0625 V Gain = 8 Gain = 4 Gain = 2
V1P 0.0313 V Gain = 16 Gain = 8 Gain = 4
0.0156 V Gain = 16 Gain = 8
0.00781 V Gain = 16
VIN
K  VIN

GAIN REGISTER*
CHANNEL 1 AND CHANNEL 2 PGA CONTROL
V1N 7 6 5 4 3 2 1 0
+
0 0 0 0 0 0 0 0 ADDR:
OFFSET ADJUST 0AH
(50mV)
PGA 2 GAIN SELECT PGA 1 GAIN SELECT
000 = 1 000 = 1
001 = 2 001 = 2
010 = 4 010 = 4
CH1OS[7:0] 011 = 8 011 = 8
BIT 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION 100 = 16 100 = 16
BIT 6: NOT USED
BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT ON) CHANNEL 1 FULL-SCALE SELECT
*REGISTER CONTENTS 00 = 0.5V
01 = 0.25V
Figure 4. PGA in Channel 1 SHOW POWER-ON DEFAULTS
10 = 0.125V

Figure 5. Analog Gain Register

REV. A –11–
ADE7759
It is also possible to adjust offset errors on Channel 1 and CH1OS[5:0]

Channel 2 by writing to the offset correction registers (CH1OS

1Fh 01,1111b SIGN + 5 BITS
and CH2OS, respectively). These registers allow channel
offsets in the range ± 24 mV to ± 50 mV (depending on the
gain setting) to be removed. Note that it is not necessary to
perform an offset correction in an energy measurement applica- 00h
tion if HPF1 Channel 1 is switched on. Figure 6 shows the –50mV 0mV +50mV
effect of offsets on the real power calculation; an offset on OFFSET
Channel 1 and Channel 2 will contribute a dc component ADJUST

after multiplication. Since this dc component is extracted by

3Fh 11,1111b SIGN + 5 BITS
LPF2 to generate the active (real) power information, the
offsets will have contributed an error to the active power
calculation. This problem is easily avoided by enabling HPF1 Figure 7. Channel Offset Correction Range (Gain = 1)
in Channel 1. By removing the offset from at least one channel,
no error component is generated at dc by the multiplication. di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR
Error terms at cos(ω t) are removed by LPF2 and by integra- The di/dt sensor detects changes in magnetic field caused by ac
tion of the active power signal in the active energy register current. Figure 8 shows the principle of a di/dt current sensor.
(AENERGY[39:0])—see Energy Calculation section.

DC COMPONENT (INCLUDING ERROR TERM)

IS EXTRACTED BY THE LPF FOR REAL MAGNETIC FIELD CREATED BY CURRENT
POWER CALCULATION (DIRECTLY PROPORTIONAL TO CURRENT)
VOS  I OS
VI
2

IOS  V + EMF (ELECTROMOTIVE FORCE)

– INDUCED BY CHANGES IN
MAGNETIC FLUX DENSITY (di/dt)
VOS  I
0  2 Figure 8. Principle of a di/dt Current Sensor
Figure 6. Effect of Channel Offsets on the Real
Power Calculation The flux density of a magnetic field induced by a current is directly
proportional to the magnitude of the current. The changes in the
The contents of the offset correction registers are 6-bit, sign and
magnetic flux density passing through a conductor loop generate
magnitude coded. The weighting of the LSB size depends on
an electromotive force (EMF) between the two ends of the loop.
the gain setting, i.e., 1, 2, 4, 8, or 16. Table II shows the
The EMF is a voltage signal that is proportional to the di/dt of
correctable offset span for each of the gain settings and the LSB
the current. The voltage output from the di/dt current sensor
weight (mV) for the offset correction registers. The maximum
is determined by the mutual inductance between the current-
value that can be written to the offset correction registers is ± 31
carrying conductor and the di/dt sensor. Figure 9 shows that
decimal—see Figure 7.
the mutual inductance produces a di/dt signal at the output
of the sensor.
Table II. Offset Correction Range
MUTUAL INDUCTANCE M
Gain Correctable Span LSB Size
1 ± 50 mV 1.61 mV/LSB
2 ± 37 mV 1.19 mV/LSB + di(t)
i(t) v=M
4 ± 30 mV 0.97 mV/LSB dt
–
8 ± 26 mV 0.84 mV/LSB
16 ± 24 mV 0.77 mV/LSB
Figure 7 shows the relationship between the offset correction Figure 9. Mutual Inductance Between the di/dt
register contents and the offset (mV) on the analog inputs for a Sensor and the Current Carrying Conductor
gain setting of one. To perform an offset adjustment, the analog The current signal needs to be recovered from the di/dt signal
inputs should be first connected to AGND, and there should be before it can be used for active power calculation. An integrator
no signal on either Channel 1 or Channel 2. A read from is therefore necessary to restore the signal to its original form.
Channel 1 or Channel 2 using the waveform register will give an The ADE7759 has a built-in digital integrator to recover the
indication of the offset in the channel. This offset can be current signal from the di/dt sensor. The digital integrator on
canceled by writing an equal but opposite offset value to the Channel 1 is switched on by default when the ADE7759 is
relevant offset register. The offset correction can be confirmed powered up. Setting the MSB of the CH1OS register to 0 will
by performing another read. Note that when adjusting the offset of turn off the integrator. Figures 10 to 13 show the magnitude
Channel 1, the digital integrator and the HPF1 should be disabled. and phase response of the digital integrator.

–12– REV. A
 ADE7759
30 –89.980

20 –89.985

10
–89.990
0

PHASE – Degrees
–89.995
GAIN – dB

–10
–90.000
–20
–90.005
–30
–90.010
–40

–50 –90.015

–60 –90.020
101 102 103 104 40 45 50 55 60 65 70
FREQUENCY – Hz FREQUENCY – Hz

Figure 10. Gain Response of the Digital Integrator Figure 13. Phase Response of the Digital Integrator
(40 Hz to 70 Hz)
–88.0
Note that the integrator has a –20 dB/dec attenuation and
–88.5 approximately –90° phase shift. When combined with a di/dt
sensor, the resulting magnitude and phase response should be a
–89.0
flat gain over the frequency band of interest. However, the di/dt
PHASE – Degrees

–89.5 sensor has a 20 dB/dec gain associated with it, and generates
significant high frequency noise. A more effective antialiasing
–90.0 filter is needed to avoid noise due to aliasing—see Antialias
–90.5
Filter section.
When the digital integrator is switched off, the ADE7759 can be
–91.0
used directly with a conventional current sensor such as current
–91.5
transformer (CT) or a low resistance current shunt.

–92.0 ZERO CROSSING DETECTION

101 102 103 104
FREQUENCY – Hz
The ADE7759 has a zero crossing detection circuit on Channel 2.
This zero crossing is used to produce an external zero cross
Figure 11. Phase Response of the Digital Integrator signal (ZX), and it is also used in the calibration mode—see
Energy Calibration section. The zero crossing signal is also used
0
to initiate a temperature measurement on the ADE7759—see
Temperature Measurement section. Figure 14 shows how the
–1 zero cross signal is generated from the output of LPF1.

–2 1, 2, 4, REFERENCE

8, 16
GAIN – dB

V2P {GAIN [7:5]}

1 –63% TO +63% FS
–3 TO
V2 PGA2 ADC 2
MULTIPLIER
V2N
–4
ZERO
ZX
CROSS
–5 LPF1
f–3dB = 156Hz
–6
40 45 50 55 60 65 70 21.04
@ 60Hz
1.0
FREQUENCY – Hz 0.93
ZX
Figure 12. Gain Response of the Digital Integrator
(40 Hz to 70 Hz)
V2 LPF1

Figure 14. Zero Cross Detection on Channel 2

REV. A –13–
ADE7759
The ZX signal will go logic high on a positive going zero crossing The SAG pin will go logic high again when the absolute value of
and logic low on a negative going zero crossing on Channel 2. the signal on Channel 2 exceeds the sag level set in the Sag
The zero crossing signal ZX is generated from the output of Level register. This is shown in Figure 15 when the SAG pin
LPF1. LPF1 has a single pole at 156 Hz (CLKIN = 3.579545 MHz). goes high during the tenth half cycle from the time when the
As a result, there will be a phase lag between the analog input signal on Channel 2 first dropped below the threshold level.
signal V2 and the output of LPF1. The phase response of this
Sag Level Set
filter is shown in the Channel 2 Sampling section. The phase
The contents of the sag level register (1 byte) are compared to
lag response of LPF1 results in a time delay of approximately
the absolute value of the most significant byte output from
0.97 ms (@ 60 Hz) between the zero crossing on the analog
LPF1, after it is shifted left by one bit. For example, the nomi-
inputs of Channel 2 and the rising or falling edge of ZX.
nal maximum code from LPF1 with a full-scale signal on
The zero crossing detection also has an associated timeout reg- Channel 2 is 257F6h or (0010, 0101, 0111, 1111, 0110b)—see
ister, ZXTOUT. This unsigned, 12-bit register is decremented Channel 2 Sampling section. Shifting one bit left will give 0100,
1 LSB every 128/CLKIN seconds. The register is reset to its 1010, 1111, 1110, 1100b, or 4AFECh. Therefore, writing 4Ah
user-programmed full-scale value every time a zero crossing on to the sag level register will put the sag detection level at full
Channel 2 is detected. The default power-on value in this regis- scale. Writing 00h will put the sag detection level at zero. The
ter is FFFh. If the register decrements to zero before a zero sag level register is compared to the most significant byte of a
crossing is detected and the DISSAG bit in the mode register is waveform sample after the shift left, and detection is made when
logic zero, the SAG pin will go active low. The absence of a zero the contents of the sag level register are greater.
crossing is also indicated on the IRQ output if the SAG Enable
bit in the interrupt enable register is set to Logic 1. Irrespective POWER SUPPLY MONITOR
of the enable bit setting, the SAG flag in the interrupt status The ADE7759 also contains an on-chip power supply monitor.
register is always set when the ZXTOUT register is decremented The analog supply (AVDD) is continuously monitored by the
to zero—see Interrupts section. The zero cross timeout register ADE7759. If the supply is less than 4 V ± 5%, the ADE7759
can be written/read by the user and has an address of 0Eh—see will go into an inactive state, i.e., no energy will be accumulated
Serial Interface section. The resolution of the register is 128/CLKIN when the supply voltage is below 4 V. This is useful to ensure
seconds per LSB. Thus the maximum delay for an interrupt correct device operation at power-up and during power-down.
is 0.15 second (128/CLKIN × 212 ). The power supply monitor has built-in hysteresis and filtering.
This gives a high degree of immunity to false triggering due to
LINE VOLTAGE SAG DETECTION noisy supplies.
In addition to the detection of the loss of the line voltage signal
(zero crossing), the ADE7759 can also be programmed to detect AVDD
when the absolute value of the line voltage drops below a certain 5V
peak value, for a number of half cycles. This condition is illus- 4V
trated in Figure 15.

CHANNEL 2
FULL SCALE 0V
TIME
SAGLVL [7:0]

ADE7759
POWER-ON INACTIVE ACTIVE INACTIVE
RESET

SAG RESET HIGH

WHEN CHANNEL 2
EXCEEDS SAGLVL [7:0] SAG
SAGCYC [7:0] = 06H
6 HALF CYCLES
SAG Figure 16. On-Chip Power Supply Monitor
As seen in Figure 16, the trigger level is nominally set at 4 V.
The tolerance on this trigger level is about ± 5%. The SAG pin
Figure 15. Sag Detection can also be used as a power supply monitor input to the MCU.
The SAG pin will go logic low when the ADE7759 is reset. The
Figure 15 shows the line voltage fall below a threshold that is set power supply and decoupling for the part should be such that
in the sag level register (SAGLVL[7:0]) for nine half cycles. the ripple at AVDD does not exceed 5 V ± 5% as specified for
Since the sag cycle register (SAGCYC[7:0]) contains 06h, the normal operation.
SAG pin will go active low at the end of the sixth half cycle for
which the line voltage falls below the threshold, if the DISSAG Bit 6 of the interrupt status register (STATUS[7:0]) will be set
bit in the mode register is Logic 0. As is the case when zero to logic high upon power-up or every time the analog supply
crossings are no longer detected, the sag event is also recorded (AVDD) dips below the power supply monitor threshold (4 V ± 5%)
by setting the SAG flag in the interrupt status register. If the and recovers. However, no interrupt can be generated because
SAG enable bit is set to Logic 1, the IRQ logic output will go the corresponding bit (Bit 6) in the interrupt enable register
active low—see Interrupts section. (IRQEN[7:0]) is not active—see Interrupts section.

–14– REV. A
 ADE7759
INTERRUPTS MCU should be configured to start executing its Interrupt Ser-
ADE7759 interrupts are managed through the interrupt status vice Routine (ISR). On entering the ISR, all interrupts should
register (STATUS[7:0]) and the interrupt enable register be disabled using the global interrupt enable bit. At this point,
(IRQEN[7:0]). When an interrupt event occurs in the ADE7759, the MCU external interrupt flag can be cleared to capture inter-
the corresponding flag in the status register is set to a Logic 1—see rupt events that occur during the current ISR.
Interrupt Status Register section. If the enable bit for this When the MCU interrupt flag is cleared, a read from the status
interrupt in the interrupt enable register is Logic 1, then the register with reset is carried out. This will cause the IRQ line to
IRQ logic output goes active low. The flag bits in the status be reset logic high (t2)—see Interrupt Timing section. The
register are set irrespective of the state of the enable bits. status register contents are used to determine the source of
To determine the source of the interrupt, the system master the interrupt(s), and thus the appropriate action will be taken. If
(MCU) should perform a read from the status register with a subsequent interrupt event occurs during the ISR, that event
reset (RSTATUS[7:0]). This is achieved by carrying out a will be recorded by the MCU external interrupt flag being set
read from address 05h. The IRQ output will go logic high on again (t3). On returning from the ISR, the global interrupt mask
completion of the interrupt status register read command— will be cleared (same instruction cycle) and the external inter-
see Interrupt Timing section. When carrying out a read with rupt flag will cause the MCU to jump to its ISR once again. This
reset, the ADE7759 is designed to ensure that no interrupt will ensure that the MCU does not miss any external interrupts.
events are missed. If an interrupt event occurs just as the status Interrupt Timing
register is being read, the event will not be lost and the IRQ The Serial Interface section should be reviewed first, before the
logic output is guaranteed to go high for the duration of the Interrupt Timing section. As previously described, when the
interrupt status register data transfer before going logic low IRQ output goes low, the MCU ISR must read the interrupt
again to indicate the pending interrupt. See the following status register to determine the source of the interrupt. When
section for a more detailed description. reading the status register contents, the IRQ output is set high
Using the ADE7759 Interrupts with an MCU on the last falling edge of SCLK of the first byte transfer (read
Figure 17 shows a timing diagram with a suggested implementa- interrupt status register command). The IRQ output is held
tion of ADE7759 interrupt management using an MCU. At high until the last bit of the next 8-bit transfer is shifted out
time t1, the IRQ line will go active low, indicating that one or (interrupt status register contents)—see Figure 18. If an inter-
more interrupt events have occurred in the ADE7759. The IRQ rupt is pending at this time, the IRQ output will go low again. If
logic output should be tied to a negative edge-triggered external no interrupt is pending, the IRQ output will stay high.
interrupt on the MCU. On detection of the negative edge, the

MCU
INTERRUPT
FLAG SET
t1 t2 t3

IRQ

MCU JUMP GLOBAL CLEAR MCU READ ISR ACTION ISR RETURN JUMP
PROGRAM TO INTERRUPT INTERRUPT STATUS WITH (BASED ON GLOBAL INTERRUPT TO
SEQUENCE ISR MASK SET FLAG RESET (05h) STATUS CONTENTS) MASK RESET ISR

Figure 17. Interrupt Management

CS

t1
SCLK

t9

DIN 0 0 0 0 0 1 0 1

t 11 t 11
DOUT DB7 DB0

READ STATUS REGISTER COMMAND

STATUS REGISTER CONTENTS

IRQ

Figure 18. Interrupt Timing

REV. A –15–
ADE7759
TEMPERATURE MEASUREMENT the signal is sampled at a rate (frequency) that is many times
ADE7759 also includes an on-chip temperature sensor. A higher than the bandwidth of interest. For example, the sam-
temperature measurement can be made by setting Bit 5 in the pling rate in the ADE7759 is CLKIN/4 (894 kHz) and the band
mode register. When Bit 5 is set logic high in the mode register, the of interest is 40 Hz to 2 kHz. Oversampling has the effect of
ADE7759 will initiate a temperature measurement on the next spreading the quantization noise (noise due to sampling) over a
zero crossing. When the zero crossing on Channel 2 is de- wider bandwidth. With the noise spread more thinly over a
tected, the voltage output from the temperature sensing wider bandwidth, the quantization noise in the band of interest
circuit is connected to ADC1 (Channel 1) for digitizing. The is lowered—see Figure 20. However, oversampling alone is not
resultant code is processed and placed in the temperature an efficient enough method to improve the signal-to-noise ratio
register (TEMP[7:0]) approximately 26 µs later (24 CLKIN (SNR) in the band of interest. For example, an oversampling
cycles). If enabled in the interrupt enable register (Bit 5), the ratio of 4 is required just to increase the SNR by only 6 dB (one
IRQ output will go active low when the temperature conversion bit). To keep the oversampling ratio at a reasonable level, it is
is finished. Note that temperature conversion will introduce a possible to shape the quantization noise so that the majority of
small amount of noise in the energy calculation. If temperature the noise lies at the higher frequencies. This is what happens in
conversion is performed frequently (i.e., multiple times per sec- the sigma-delta modulator: the noise is shaped by the integrator,
ond), a noticeable error will accumulate in the resulting energy which has a high-pass type response for the quantization noise.
calculation over time. The result is that most of the noise is at the higher frequencies,
The contents of the temperature register are signed (twos where it can be removed by the digital low-pass filter. This noise
complement) with a resolution of approximately 1 LSB/°C. The shaping is also shown in Figure 20.
temperature register will produce a code of 00h when the ambient ANTIALIAS
temperature is approximately 70°C. The temperature mea- DIGITAL
FILTER (RC)
SAMPLING
surement is uncalibrated in the ADE7759 and has an offset SIGNAL FILTER FREQUENCY
SHAPED
tolerance that could be as high as ± 20°C. NOISE

ANALOG-TO-DIGITAL CONVERSION NOISE

The analog-to-digital conversion in the ADE7759 is carried out
using two second-order sigma-delta ADCs. The block diagram in 0 2 447 894
Figure 19 shows a first-order (for simplicity) sigma-delta ADC. FREQUENCY – kHz

The converter is made up of two parts, first the sigma-delta modu-

HIGH RESOLUTION
lator and second the digital low-pass filter. SIGNAL OUTPUT FROM DIGITAL
LPF
A sigma-delta modulator converts the input signal into a con-
tinuous serial stream of 1s and 0s at a rate determined by the
NOISE
sampling clock. In the ADE7759, the sampling clock is equal to
CLKIN/4. The 1-bit DAC in the feedback loop is driven by the
0 2 447 894
serial data stream. The DAC output is subtracted from the input
FREQUENCY – kHz
signal. If the loop gain is high enough, the average value of the
DAC output (and therefore the bit stream) will approach that Figure 20. Noise Reduction Due to Oversampling
of the input signal level. For any given input value in a single and Noise Shaping in the Analog Modulator
sampling interval, the data from the 1-bit ADC is virtually Antialias Filter
meaningless. Only when a large number of samples are averaged Figure 19 also shows an analog low-pass filter (RC) on the input
will a meaningful result be obtained. This averaging is carried to the modulator. This filter is present to prevent aliasing.
out in the second part of the ADC, the digital low-pass filter. By Aliasing is an artifact of all sampled systems. Basically, it means
averaging a large number of bits from the modulator, the low- that frequency components in the input signal to the ADC that
pass filter can produce 20-bit datawords that are proportional to are higher than half the sampling rate of the ADC will appear in
the input signal level. the sampled signal at a frequency below half the sampling rate.
MCLK/4
Figure 21 illustrates the effect. Frequency components above
ANALOG
DIGITAL
half the sampling frequency (also known as the Nyquist frequency,
LOW-PASS FILTER
LOW-PASS i.e., 447 kHz) get imaged or folded back down below 447 kHz.
+ LATCHED FILTER
R This will happen with all ADCs regardless of the architecture.
– ∫ + COMPARATOR 1 20
C –
In the example shown, it can be seen that only frequencies near
VREF the sampling frequency (894 kHz) will move into the band of
interest for metering, i.e., 40 Hz–2 kHz. This allows us to use a
.....10100101.....
very simple LPF (low-pass filter) to attenuate these high fre-
1-BIT DAC quencies (near 900 kHz) and to prevent distortion in the band
of interest. For a conventional current sensor, a simple RC filter
Figure 19. First Order Sigma-Delta (Σ-∆) ADC (single pole) with a corner frequency of 10 kHz will produce an
attenuation of approximately 40 dB at 894 kHz—see Figure 20.
The sigma-delta converter uses two techniques to achieve high The 20 dB per decade attenuation is usually sufficient to elimi-
resolution from what is essentially a one-bit conversion tech- nate the effects of aliasing for a conventional current sensor.
nique. The first is oversampling. By oversampling we mean that

–16– REV. A
 ADE7759
ALIASING EFFECTS OUTPUT
IMPEDANCE
MAXIMUM 6k
LOAD = 10A
SAMPLING REFIN/OUT
FREQUENCY 2.42V
IMAGE
FREQUENCIES PTAT 60A
1.7k
2.5V

12.5k
0 2 447 894
12.5k
FREQUENCY – kHz

REFERENCE INPUT
Figure 21. ADC and Signal Processing in Channel 1 12.5k
TO ADC CHANNEL 1
(RANGE SELECT)
For a di/dt sensor such as a Rogowski coil, however, the sensor 12.5k 2.42V, 1.21V, 0.6V
has 20 dB per decade gain. This will neutralize the –20 dB per
decade attenuation produced by this simple LPF and nullifies
the antialias filter. Therefore, when using a di/dt sensor, mea- Figure 22. ADC and Reference Circuit Output
sures should be taken to offset the 20 dB per decade gain coming The REFIN/OUT pin can be overdriven by an external source,
from the di/dt sensor and produce sufficient attenuation to e.g., an external 2.5 V reference. Note that the nominal refer-
eliminate any aliasing effect. One simple approach is to cascade ence value supplied to the ADCs is now 2.5 V not 2.42 V. This
two RC filters to produce –40 dB per decade attenuation. The has the effect of increasing the nominal analog input signal
transfer function for a cascaded filter is the following: range by 2.5/2.42 ⫻ 100% = 3%, or from 0.5 V to 0.5165 V.
1 The internal voltage reference on the ADE7759 has a tempera-
H (s ) = ture drift associated with it—see ADE7759 Specifications section
1 + sR1C1 + sR2C 2 + sR1C 2 + s 2R1C1R2C 2
for the temperature coefficient specification (in ppm°C). The
where R1C1 represents the RC used in the first stage of the value of the temperature drift varies slightly from part to part.
cascade and R2C2 in that of the second stage. The s2 term in the Since the reference is used for the ADCs in both Channel 1 and 2,
transfer function produces a –40 dB/decade attenuation. Note any x% drift in the reference will result in 2x% deviation of the
that to minimize the measurement error, especially at low power meter reading. The reference drift resulting from temperature
factor, it is important to match the phase angle between the changes is usually very small, and it is typically much smaller
voltage and the current channel. The small phase mismatch in than the drift of other components on a meter. However, if
the external antialias filter can be corrected using the phase calibra- guaranteed temperature performance is needed, one needs to
tion register (PHCAL[7:0])—see Phase Compensation section. use an external voltage reference. Alternatively, the meter can be
ADC Transfer Function calibrated at multiple temperatures. Real-time compensation
Below is an expression which relates the output of the LPF in can be achieved easily using the on-chip temperature sensor.
the sigma-delta ADC to the analog input signal level. Both ADCs
in the ADE7759 are designed to produce the same output code CHANNEL 1 ADC
for the same input signal level. Figure 23 shows the ADC and signal processing chain for Chan-
nel 1. In waveform sampling mode, the ADC outputs a signed
VIN twos complement 20-bit dataword at a maximum of 27.9 kSPS
Code( ADC ) = 3.0492 × × 262, 144
VREF (CLKIN/128). The output of the ADC can be scaled by ± 50%
to perform an overall power calibration or to calibrate the ADC
Therefore, with a full-scale signal on the input of 0.5 V and an output. While the ADC outputs a 20-bit twos complement
internal reference of 2.42 V, the ADC output code is nominally value, the maximum full-scale positive value from the ADC is
165,151 or 2851Fh. The maximum code from the ADC is limited to 40,000h (+262,144 decimal). The maximum full-
±262,144, which is equivalent to an input signal level of ±0.794 V. scale negative value is limited to C0000h (–262,144 decimal). If
However, for specified performance it is not recommended that the the analog inputs are overranged, the ADC output code will
full-scale input signal level of 0.5 V be exceeded. clamp at these values. With the specified full-scale analog input
Reference Circuit signal of 0.5 V (or 0.25 V or 0.125 V—see Analog Inputs sec-
Shown in Figure 22 is a simplified version of the reference out- tion), the ADC will produce an output code that is approximately
put circuitry. The nominal reference voltage at the REFIN/OUT 63% of its full-scale value. This is illustrated in Figure 23. The
pin is 2.42 V. This is the reference voltage used for the ADCs in diagram in Figure 23 shows a full-scale voltage signal being
the ADE7759. However, Channel 1 has three input range selec- applied to the differential inputs V1P and V1N. The ADC
tions, which are selected by dividing down the reference value output swings between D7AE1h (–165,151) and 2851Fh
used for the ADC in Channel 1. The reference value used for (+165,151). This is approximately 63% of the full-scale value
Channel 1 is divided down to 1/2 and 1/4 of the nominal value 40,000h (262,144). Overranging the analog inputs with more
by using an internal resistor divider, as shown in Figure 22. than 0.5 V differential (0.25 V or 0.125 V, depending on
Channel 1 full-scale selection) will cause the ADC output to
increase towards its full-scale value. However, for specified
operation, the differential signal on the analog inputs should
not exceed the recommended value of 0.5 V.

REV. A –17–
ADE7759
2.42V, 1.21V, 0.6V
{GAIN[4:3]}
1, 2, 4, REFERENCE
8, 16
{GAIN[2:0]} DIGITAL TO WAVEFORM
V1P
MULTIPLIER DIGITAL LPF HPF INTEGRATOR* SAMPLE REGISTER
V1 PGA1 ADC 1 Sinc3 ∫ TO MULTIPLIER

V1N CHANNEL 1 (ACTIVE POWER)

50Hz DATA RANGE AFTER
801HEX–7FFHEX INTEGRATOR (50Hz)
APGAIN[11:0] 2E72Eh +94.5% FS
V1 1EF74h +63% FS
0.5V, 0.25V, +31.5% FS
F7BAh
0.125V, 62.5mV,
31.3mV, 15.6mV, 40000h +FS CHANNEL 1 (ACTIVE POWER) 00000h
DATA RANGE F0846h – 31.5% FS
0V 2851Fh +63% FS
3C7AEh +94.5% FS E108Ch – 63% FS
2851Fh +63% FS D18D2h – 94.5% FS
00000h 000h 7FFh 801h
ANALOG 1428Fh +31.5% FS
INPUT 00000h 60Hz APGAIN[11:0]
RANGE D7AE1h – 63% FS EBD71h – 31.5% FS
C0000h – FS D7AE1h – 63% FS CHANNEL 1 (ACTIVE POWER)
ADC OUTPUT DATA RANGE AFTER
C3852h – 94.5% FS INTEGRATOR (60Hz)
WORD RANGE 000h 7FFh 801h
26B50h +94.5% FS
APGAIN[11:0]
19CE0h +63% FS
0CE70h +31.5% FS
00000h
F3190h – 31.5% FS
*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA VARIES DEPENDING
E6320h – 63% FS
ON THE SIGNAL FREQUENCY BECAUSE OF –20dB/DECADE FREQUENCY RESPONSE.
D94B0h – 94.5% FS
000h 7FFh 801h

APGAIN[11:0]

Figure 23. ADC and Signal Processing in Channel 1

Channel 1 ADC Gain Adjust wave form samples are transferred from the ADE7759 one byte
The ADC gain in Channel 1 can be adjusted by using the multi- (eight bits) at a time, with the most significant byte shifted out
plier and active power gain register (APGAIN[11:0]). The gain of first. The 20-bit dataword is right justified and sign extended to
the ADC is adjusted by writing a twos complement 12-bit word 24 bits (three bytes)—see Serial Interface section.
to the active power gain register. Below is the expression that
shows how the gain adjustment is related to the contents of the SAMPLING RATE (27.9kSPS, 14kSPS, 7kSPS, OR 3.5kSPS)

active power gain register.

IRQ

  APGAIN  SCLK 16s

Code =  ADC × 1 + 
  212  DIN
READ FROM WAVEFORM
0 0 0 01 HEX

For example, when 7FFh is written to the active power gain DOUT SIGN
register, the ADC output is scaled up by 50%. 7FFh = 2047 CHANNEL 1 DATA
decimal, 2047/2 12 = 0.5. Similarly, 801h = 2047 decimal – 20 BITS

(signed twos complement) and ADC output is scaled by –50%. Figure 24. Waveform Sampling Channel 1
These two examples are illustrated in Figure 23.
Channel 1 Sampling CHANNEL 1 AND CHANNEL 2 WAVEFORM SAMPLING
The waveform samples may also be routed to the waveform MODE
register (MODE[14:13] = 1, 0) to be read by the system master In Channel 1 and Channel 2 waveform sampling mode
(MCU). In waveform sampling mode, the WSMP bit (Bit 3) in (MODE[14:13] = 01), the output is a 40-bit waveform sample
the interrupt enable register must also be set to Logic 1. The data that contains the waveform samples from both Channel 1
active power and energy calculation will remain uninterrupted and Channel 2 ADCs. Figure 25 shows the format of the 40-bit
during waveform sampling. waveform output.
When in waveform sample mode, one of four output sample 1 BYTE 2 BYTES 2 BYTES
rates may be chosen by using Bits 11 and 12 of the mode regis- BIT 39 BIT 0

ter DTRT(1, 0). The output sample rate may be 27.9 kSPS, CH2[19:16] CH1[19:16] CH1[15:0] CH2[15:0]

14 kSPS, 7 kSPS, or 3.5 kSPS—see Mode Register section. The

interrupt request output IRQ signals a new sample availability Figure 25. 40-Bit Combined Channel 1 and Channel 2
by going active low. The timing is shown in Figure 24. The 20-bit Waveform Sample Data Format

–18– REV. A
 ADE7759
CHANNEL 2 ADC 2.42V
1, 2, 4, REFERENCE
Channel 2 Sampling 8, 16
In Channel 2 waveform sampling mode (MODE[14:13] = 1, 1 V2P {GAIN [7:5]}
1 –63% TO +63% FS
and WSMP = 1), the ADC output code scaling for Channel 2 is V2 PGA2 ADC 2
TO
MULTIPLIER
the same as Channel 1, i.e., the output swings between D7AE1h V2N
LPF1
TO
20
(–165,151) and 2851Fh (+165,151)—see ADC Channel 1 WAVEFORM
REGISTER
section. However, before being passed to the waveform register, V1
the ADC output is passed through a single-pole, low-pass filter 0.5V, 0.25V, 0.125V,
LPF OUTPUT
62.5mV, 31.25mV
with a cutoff frequency of 156 Hz. The plots in Figure 26 show 0V
WORD RANGE
40000h +FS
the magnitude and phase response of this filter. 2851Fh +63% FS
257F6h +59% FS
0 0 ANALOG 00000h
INPUT RANGE
DA80Ah –59% FS
D7AE1h –63% FS
60Hz, –0.6dB C0000h –FS
–20
PHASE – Degrees

60Hz, –21.04
Figure 27. ADC and Signal Processing in Channel 2

GAIN – dB
–40 –10
PHASE COMPENSATION
When the HPF is disabled, the phase error between Channel 1 and
Channel 2 is zero from dc to 3.5 kHz. When HPF1 is enabled,
–60 Channel 1 has a phase response illustrated in Figures 29 and 30.
Also shown in Figure 31 is the magnitude response of the filter.
As can be seen from the plots, the phase response is almost zero
–80 –20 from 45 Hz to 1 kHz. This is all that is required in typical energy
101 102 103 measurement applications.
FREQUENCY – Hz
However, despite being internally phase compensated, the
Figure 26. Magnitude and Phase Response of LPF1 ADE7759 must work with transducers that may have inherent
The LPF1 has the effect of attenuating the signal. For example, phase errors. For example, a phase error of 0.1° to 0.3° is not
if the line frequency is 60 Hz, the signal at the output of LPF1 uncommon for a CT (Current Transformer). These phase
will be attenuated by 7%. errors can vary from part to part, and they must be corrected in
order to perform accurate power calculations. The errors associ-
1 ated with phase mismatch are particularly noticeable at low
H( f ) = = 0.93 = –0.6 dB power factors. The ADE7759 provides a means of digitally
2
 60 Hz  calibrating these small phase errors. The ADE7759 allows a
1+  
 156 Hz  small time delay or time advance to be introduced into the signal
processing chain in order to compensate for small phase errors.
Because the compensation is in time, this technique should only be
Note that LPF1 does not affect the power calculation. The
used for small phase errors in the range of 0.1° to 0.5°. Correcting
signal processing chain in Channel 2 is illustrated in Figure 27.
large phase errors using a time shift technique can introduce signifi-
Unlike Channel 1, Channel 2 has only one analog input range
cant phase errors at higher harmonics.
(0.5 V differential). However, like Channel 1, Channel 2 does
have a PGA with gain selections of 1, 2, 4, 8, and 16. For energy The phase calibration register (PHCAL[7:0]) is a twos comple-
measurement, the output of the ADC is passed directly to the ment signed single-byte register that has values ranging from 9Eh
multiplier and is not filtered. An HPF is not required to remove (–98 in decimal) to 5Ch (92 in decimal). By changing the PHCAL
any dc offset since it is only required to remove the offset from register, the time delay in the Channel 2 signal path can change
one channel to eliminate errors due to offsets in the power cal- from –110 µs to +103 µs (CLKIN = 3.579545 MHz). One LSB is
culation. When in waveform sample mode, one of four output equivalent to 1.12 µs time delay or advance. With a line frequency
sample rates can be chosen by using Bits 11 and 12 of the of 60 Hz, this gives a phase resolution of 0.024° at the fundamental
mode register. The available output sample rates are 27.9 kSPS, (i.e., 360° × 1.12 µs × 60 Hz). Figure 28 illustrates how the phase
14 kSPS, 7 kSPS, or 3.5 kSPS—see Mode Register section. The compensation is used to remove a 0.1° phase lead in Channel 1
interrupt request output IRQ signals a new sample availability due to the external transducer. To cancel the lead (0.1°) in
by going active low. The timing is the same as that for Channel 1, a phase lead must also be introduced into Channel 2.
Channel 1 and is shown in Figure 24. The resolution of the phase adjustment allows the introduction of a
phase lead in increments of 0.024°. The phase lead is achieved by
introducing a time advance into Channel 2. A time advance of
4.48 µs is made by writing –4 (FCh) to the time delay block, thus
reducing the amount of time delay by 4.48 µs, or equivalently, a
phase lead of approximately 0.1° at line frequency of 60 Hz.

REV. A –19–
ADE7759
V1P HPF 0.4
20
V1 PGA1 ADC 1
0.3
V1N LPF2
20 0.2

V2P 0.1

ERROR – %
1 CHANNEL 2 DELAY
PGA2 DELAY BLOCK REDUCED BY 4.48s
V2 ADC 2
1.12s/LSB (0.1
LEAD AT 60Hz) 0.0
V2N FCH IN PHCAL [7:0]
7 0 –0.1
V2
1 1 1 1 1 1 0 0 V1
V2
0.1
PHCAL [7:0] –0.2
V1 –110s TO +103s
–0.3

60Hz –0.4
54 56 58 60 62 64 66
60Hz FREQUENCY – Hz

Figure 28. Phase Calibration Figure 31. Combined Gain Response of the HPF and Phase
Compensation (Deviation of Gain in % from Gain at 60 Hz)
0.30

ACTIVE POWER CALCULATION

0.25
Electrical power is defined as the rate of energy flow from source to
0.20 load. It is given by the product of the voltage and current wave-
forms. The resulting waveform is called the instantaneous power
PHASE – Degrees

0.15
signal, and it is equal to the rate of energy flow at every instant
0.10
of time. The unit of power is the watt or joules/second. Equa-
tion 3 gives an expression for the instantaneous power signal in
0.05 an ac system.
0.00 v(t ) = 2 V (ωt ) (1)

–0.05 i(t ) = 2 I sin(ωt ) (2)

–0.10
100 200 300 400 500 600 700 800 900 1000 where:
FREQUENCY – Hz
V = rms voltage
Figure 29. Combined Phase Response of the HPF and I = rms current
Phase Compensation (100 Hz to 1 kHz) p(t ) = v(t ) × i(t )
(3)
p(t ) = VI – VI cos(2ωt )
0.30 The average power over an integral number of line cycles (n) is
given by the expression in Equation 4.
0.25
1 nT
0.20
P= ∫ p (t ) dt = VI (4)
nT 0
where T is the line cycle period. P is referred to as the active or
PHASE – Degrees

0.15
real power. Note that the active power is equal to the dc compo-
0.10 nent of the instantaneous power signal p(t) in Equation 3, i.e.,
VI. This is the relationship used to calculate active power in the
0.05
ADE7759. The instantaneous power signal p(t) is generated by
0.00 multiplying the current and voltage signals. The dc component
of the instantaneous power signal is then extracted by LPF2 (low-
–0.05 pass filter) to obtain the active power information. This process
is illustrated in Figure 32. Since LPF2 does not have an ideal
–0.10
40 45 50 55 60 65 70 “brick wall” frequency response (see Figure 33), the active power
FREQUENCY – Hz
signal will have some ripple due to the instantaneous power
Figure 30. Combined Phase Response of the HPF and signal. This ripple is sinusoidal and has a frequency equal to twice
Phase Compensation (40 Hz to 70 Hz) the line frequency. Since the ripple is sinusoidal in nature, it will
be removed when the active power signal is integrated to calcu-
late energy—see Energy Calculation section.

–20– REV. A
 ADE7759
INSTANTANEOUS p(t) = V  I – V  I  cos(2t)
POWER SIGNAL
1999Ah

ACTIVE REAL POWER

SIGNAL = V  I 13333h +30% FS

CCCDh +20% FS POSITIVE

POWER

OUTPUT LPF2
VI 6666h +10% FS
CCCDh
00000h

F999Ah –10% FS

F3333h –20% FS NEGATIVE

POWER
ECCCDh –30% FS
00000h
000h 7FFh 800h

CURRENT {APGAIN [11:0]}

i(t) = 2  I  sin(t)
CHANNEL 1 (ACTIVE POWER)
CALIBRATION RANGE
VOLTAGE
v(t) = 2  V  sin(t)
Figure 35. Active Power Calculation Output Range
Figure 32. Active Power Calculation
ENERGY CALCULATION
0 As stated earlier, power is defined as the rate of energy flow.
This relationship can be expressed mathematically as:
–4
dE
P= (5)
dt
–8
where P = power and E = energy.
Conversely, energy is given as the integral of power:
dB

–12

E = ∫ Pdt (6)
–16
The AD7759 achieves the integration of the active power signal
–20
by continuously accumulating the active power signal in the
40-bit active energy register (ASENERGY[39:0]). This discrete
time accumulation or summation is equivalent to integration in
–24
1 3 10 30 100 continuous time. Equation 7 expresses this relationship:
FREQUENCY – Hz
∞ 
Figure 33. Frequency Response of LPF2 E = ∫ P (t )dt = Lim ∑ p( nT ) × T  (7)

T →0 n = 0

Figure 34 shows the signal processing chain for the active power
calculation in the ADE7759. As explained, the active power is where n is the discrete time sample number and T is the
calculated by low pass filtering the instantaneous power signal. sample period.
The discrete time sample period (T) for the accumulation regis-
HPF ACTIVE POWER
SIGNAL – P ter in the ADE7759 is 1.1 µs (4/CLKIN). As well as calculating
I the energy, this integration removes any sinusodial components
CCCDh
CURRENT SIGNAL – i(t) LPF2 which may be in the active power signal.
20
MULTIPLIER Figure 36 shows a graphical representation of this discrete time
integration or accumulation. The active power signal in the wave-
INSTANTANEOUS POWER SIGNAL – p(t)
1 –40% TO +40% FS form register is continuously added to the active energy register.
V
VOLTAGE SIGNAL – v(t) 1999Ah
This addition is a signed addition; therefore negative energy will be
subtracted from the active energy contents.
00h As shown in Figure 36, the active power signal is accumulated
in a 40-bit signed register (AENERGY[39:0]). The active
Figure 34. Active Power Signal Processing power signal can be read from the waveform register by setting
MODE[14:13] = 0, 0 and setting the WSMP bit (Bit 3) in
Shown in Figure 35 is the maximum code (hexadecimal) output the interrupt enable register to 1. Like Channel 1 and Channel 2
range for the active power signal (LPF2) when the digital inte- waveform sampling modes, the waveform data is available at
grator is disabled. Note that when the integrator is enabled, the sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS—see
output range changes depending on the input signal frequency. Figure 24. Figure 37 shows this energy accumulation for full-scale
Furthermore, the output range can also be changed by the signals (sinusodial) on analog inputs. The three curves displayed
active power gain register—see Channel 1 ADC section. The illustrate the minimum period of time it takes the energy register to
minimum output range is given when the active power gain roll over when the active power gain register contents are 7FFh,
register contents are equal to 800h, and the maximum range is 000h, and 800h. The active power gain register is used to carry out
given by writing 7FFh to the active power gain register. This power calibration in the ADE7759. As shown, the fastest
can be used to calibrate the active power (or energy) calculation integration time will occur when the active power gain register is
in the ADE7759. set to maximum full scale, i.e., 7FFh.
REV. A –21–
ADE7759
15 APOS [15:0] 0

SIGN 26 25 24 23 22 21 20 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8

CURRENT CHANNEL

LPF2 + WAVEFORM [24:0]

23 0
20 +

AENERGY [39:0] +
39 0

VOLTAGE CHANNEL ACTIVE POWER

SIGNAL = P +

T 4
CLKIN WAVEFORM
OUTPUT LPF2

REGISTER WAVEFORM REGISTER VALUES ARE

VALUES ACCUMULATED (INTEGRATED) IN
THE ACTIVE ENERGY REGISTER

TIME – nT

Figure 36. Energy Calculation

AENERGY [39:0] 7F,FFFF,FFFFh. Therefore, the integration time under these

7F,FFFF,FFFFh
conditions is calculated as follows:
APGAIN = 7FFh
APGAIN = 000h
7 F , FFFF , FFFFh
APGAIN = 800h Time = × 1.1 µs = 11.53 seconds
3F,FFFF,FFFFh CCCDh

POWER OFFSET CALIBRATION

00,0000,0000h
5.8s 11.5s 23s
TIME – sec The ADE7759 also incorporates an active power offset regis-
ter (APOS[15:0]). This is a signed twos complement 16-bit
register that can be used to remove offsets in the active power
40,0000,0000
calculation—see Figure 36. An offset may exist in the power
calculation due to crosstalk between channels on the PCB or in
80,0000,0000h the IC itself. The offset calibration will allow the contents of the
active power register to be maintained at zero when no power is
being consumed.
Figure 37. Energy Register Rollover Time for Full-Scale
Power (Minimum and Maximum Power Gain) The 256 LSBs (APOS = 0100h) written to the active power
offset register are equivalent to 1 LSB in the waveform sample
Note that the energy register contents will roll over to full-scale register, assuming the average value output from LPF2 to
negative (80,0000,0000h) and continue increasing in value when store in the waveform register is CCCDh (52,429 in decimal)
the power or energy flow is positive—see Figure 37. Conversely, if when inputs on Channels 1 and 2 are both at full scale and
the power is negative, the energy register would underflow to full- the digital integrator is turned off. At –60 dB down on Chan-
scale positive (7F, FFFF, FFFFh) and continue decreasing in nel 1 (1/1000 of the Channel 1 full-scale input), the average
value. By using the interrupt enable register, the ADE7759 word value output from LPF2 is 52.429 (52,429/1,000). One
can be configured to issue an interrupt (IRQ) when the active LSB in the waveform register has a measurement error of
energy register is half-full (positive or negative) or when an 1/52.429 × 100% = 1.9% of the average value. The active
over/underflow occurs. power offset register has a resolution equal to 1/256 LSB of
the waveform register, thus the power offset correction reso-
Integration Time under Steady Load
lution is 0.007%/LSB (1.9%/256) at –60 dB. When the digital
As mentioned in the last section, the discrete time sample
integrator is turned on, the resolution of the LSB varies slightly
period (T) for the accumulation register is 1.1 µs (4/CLKIN).
with the line frequency.
With full-scale sinusoidal signals on the analog inputs, digital
integrator turned off, and the active power gain register set to
ENERGY-TO-FREQUENCY CONVERSION
000h, the average word value from LPF2 is CCCD—see
ADE7759 also provides energy-to-frequency conversion for
Figures 34 and 35. The maximum value that can be stored in
calibration purposes. After initial calibration at manufacturing,
the active energy register before it overflows is 239 or
the manufacturer or end customer will often verify the energy
meter calibration. One convenient way to verify the meter cali-
bration is for the manufacturer to provide an output frequency
that is proportional to the energy or active power under steady

–22– REV. A
 ADE7759
load conditions. This output frequency can provide a simple, output. Therefore, the content of CFDEN should always be set
single-wire, optically isolated interface to external calibration no less than that of the CFNUM register, i.e., the maximum
equipment. Figure 38 illustrates the energy-to-frequency con- output frequency from CF pin will never exceed that of the ETF
version in the ADE7759. output. The power-up default value for CFDEN is 3Fh and
The energy-to-frequency conversion is accomplished by accu- CFNUM is 0h.
mulating the active power signal in a 24-bit register. An output The output frequency will have a slight ripple at a frequency
pulse is generated when there is a zero to one transition on the equal to twice the line frequency. This is due to imperfect filter-
MSB (most significant bit) of the register. Under steady load con- ing of the instantaneous power signal to generate the active
ditions the output frequency is proportional to the active power. power signal—see Active Power Calculation section. Equation 3
The output frequency at CF, with full-scale ac signals on gives an expression for the instantaneous power signal. This is
Channel 1 and Channel 2 and CFDEN = 000h, CFNUM = 000h, filtered by LPF2, which has a magnitude response given by
and APGAIN = 000h, is approximately 5.593 kHz. This can be Equation 10:
calculated as follows:
1
With the active power gain register set to 000h, the average H( f ) = (10)
value of the instantaneous power signal (output of LPF2) is 1 + f / 8.9 Hz
CCCDh or 52,429 decimal. An output frequency is generated The active power signal (output of LPF2) can be rewritten as:
on CF when the MSB in the energy-to-frequency register (24 bits)
toggles, i.e., when the register accumulates 223. This means the
 VI 
register is updated 223/CCCDh times (or 159.999 times). Since p(t ) = VI −   cos(4πfl t ) (11)
the update rate is 4/CLKIN or 1.1175 µs, the time between 1 + 2 fl / 8.9 Hz 
MSB toggles (CF pulses) is given as:
where fl is the line frequency (e.g., 60 Hz).
159.999 · 1.1175 ms = 1.78799 · 10–4 s (5592.86 Hz )
From Equation 6:
Equation 8 gives an expression for the output frequency at the
 
 sin(4 πfl t )
Energy-to-Frequency (ETF) output with the contents of CFDEN VI
E (t ) = VIt − 
 4 πfl (1 + 2 fl / 8.9 Hz) 
and CFNUM registers are both zero. (12)

Average LPF 2 Output × CLKIN

ETF Output ( Hz ) = (8) From Equation 12 it can be seen that there is a small ripple in
225
the energy calculation due to a sin(2ωt) component. This is
This output frequency is easily scaled by a pair of calibration shown in Figure 39. The active energy calculation is shown by
frequency divider registers (CFDEN[11:0] and CFNUM[11:0]). the dashed straight line and is equal to V × I × t. The sinusoidal
These frequency scaling registers are 12-bit registers that can ripple in the active energy calculation is also shown. Since the
scale the output frequency by 1 to 212. The output frequency is average value of a sinusoid is zero, this ripple will not contribute
given by the expression below: to the energy calculation over time. However, the ripple can be
CFNUM [11:0] + 1 observed in the frequency output, especially at higher output
CF ( Hz ) = ETF Output ( Hz ) × (9) frequencies. The ripple will get larger as a percentage of the
CFDEN [11:0] + 1
frequency at larger loads and higher output frequencies. The rea-
For example, if the CF output frequency is 5.59286 kHz while son is that at higher output frequencies the integration or averaging
the contents of CFNUM and CFDEN are zero, the CF output time in the energy-to-frequency conversion process is shorter. As
frequency can be set to 25 Hz by writing 8 BDh (2237 in deci- a consequence, some of the sinusoidal ripple is observable in the
mal) to the CFDEN register and 00Ah (10 in decimal) to the frequency output. Choosing a lower output frequency at CF for
CFNUM register. Note that the CFNUM and CFDEN regis- calibration can significantly reduce the ripple. Also, averaging the
ters are meant only to scale down the frequency from the ETF output frequency by using a longer gate time for the counter will
achieve the same results.
15 APOS [15:0] 0

SIGN 26 25 24 23 22 21 20 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8

LPF2 WAVEFORM [23:0]

+ 23 0 ACTIVE POWER OFFSET
20 + CALIBRATION

ENERGY-TO-FREQUENCY
ACTIVE POWER 23 0 +
SIGNAL – P

+
MSB
11 CFNUM [11:0] 0 TRANSITION

CFDEN [11:0] CF
11 0

Figure 38. Energy-to-Frequency Conversion

REV. A –23–
ADE7759
E(t)
Vlt
From Equations 5 and 11:
nT  VI  nT
E(t ) = ∫ VIdt –   ∫ cos (2 wt ) dt (13)
0  4
fl (1 + 2 fl / 8.9 Hz)  0
where n is an integer and T is the line cycle period.
Since the sinusoidal component is integrated over an integer
–
VI number of line cycles, its value is always zero. Therefore:
sin(4␲ƒl t)
4␲ƒ l (1 + 2ƒ l /8.9Hz)
nT
E(t ) = ∫ VIdt + 0 (14)
Figure 39. Output Frequency Ripple 0

E(t ) = VInT (15)

LINE CYCLE ENERGY ACCUMULATION MODE
In line cycle energy accumulation mode, the energy accumula- Note that in this mode, the 14-bit LINECYC register can hold a
tion of the ADE7759 can be synchronized to the Channel 2 zero maximum value of 16,383. In other words, the line cycle
crossing so that active energy can be accumulated over an inte- energy accumulation mode can be used to accumulate active
gral number of half line cycles. The advantage of summing the energy for a maximum duration over 16,383 half-line cycles. At
active energy over an integer number of half-line cycles is that 60 Hz line frequency, it translates to a total duration of 16,383/
the sinusoidal component in the active energy is reduced to zero. 120 Hz = 136.5 seconds. The 40-bit signed LENERGY register
This eliminates any ripple in the energy calculation. Energy is can overflow if large signals are present at the inputs. The
calculated more accurately and in a shorter time because the LENERGY register can only hold up to 11.53 seconds of active
integration period can be shortened. By using the line cycle energy when both its input channels are at ac full-scale—see
energy accumulation mode, the energy calibration can be greatly Integration Time Under Steady Load section. Large LINECYC
simplified and the time required to calibrate the meter can be sig- content is meant to be used only when the input signal is low
nificantly reduced. The ADE7759 is placed in line cycle energy and extensive averaging is required to reduce the noise.
accumulation mode by setting Bit 7 (CYCMODE) in the mode
register. In line cycle energy accumulation mode the ADE7759 CALIBRATING THE ENERGY METER
accumulates the active power signal in the LENERGY register Calculating the Average Active Power
(Address 14h) for an integral number of half cycles, as shown in When calibrating the ADE7759, the first step is to calibrate the
Figure 40. The number of half-line cycles is specified in the frequency on CF to some required meter constant, e.g.,
LINECYC register (Address 14h). The ADE7759 can accumu- 3200 imp/kWh.
late active power for up to 16,383 half cycles. Because the active To determine the output frequency on CF, the average value of
power is integrated on an integral number of half-line cycles, at the active power signal (output of LPF2) must first be deter-
the end of a line cycle energy accumulation cycle, the CYCEND mined. One convenient way to do this is to use the line cycle
flag in the interrupt status register is set (Bit 2). If the CYCEND energy accumulation mode. When the CYCMODE (Bit 7) bit
enable bit in the interrupt enable register is enabled, the IRQ in the mode register is set to a Logic 1, energy is accumulated
output will also go active low. Thus the IRQ line can also be over an integer number of half-line cycles as described in the
used to signal the completion of the line cycle energy accumula- last section. Since the line frequency is fixed at, say, 60 Hz, and
tion. Another calibration cycle will start as long as the CYCMODE the number of half cycles of integration is specified, the total
bit in the mode register is set. Note that the result of the first integration time is given as:
calibration is invalid and should be ignored. The result of all
1
subsequent line cycle accumulation is correct. × number of half cycles
2 × 60 Hz

15 APOS [15:0] 0

SIGN 26 25 24 23 22 21 20 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8

LPF2 WAVEFORM [23:0]

+ 23 0
FROM +
MULTIPLIER

ACTIVE POWER 39 LENERGY [39:0] 0 +

SIGNAL – P

CCCDh +
00h

LPF1

CHANNEL 2 ZERO CROSS CALIBRATION

ADC DETECT CONTROL

LINECYC [13:0]

Figure 40. Energy Calculation in Line Cycle Energy Accumulation Mode

–24– REV. A
 ADE7759
For 255 half cycles this would give a total integration time of 2.125 frequency is accurately known during calibration. Using line
seconds. This would mean that the energy register was cycle energy accumulation mode, the calibration time can be
updated 2.125/1.1175 µs (4/CLKIN) times. The average output reduced by synchronizing energy accumulation to the zero
value of LPF2 is given as: crossing of the voltage channel—see the Line Cycle Energy
Accumulation Mode section. However, this requires the line
Contents of LENERGY [39:0] at the end frequency to be precisely known. As shown in Equation 16, the
Number of times LENERGY [39:0] was updated average value of LPF2 is directly proportional to the line fre-
quency. Any deviation from the nominal frequency will directly
affect the calibration result. The line frequency could be mea-
Or, equivalently, in terms of contents of various ADE7759
sured using the ZX output of the ADE7759. Alternatively, the
registers and CLKIN and line frequencies (fl):
average value of LPF2 can be calculated from the output frequency
from CF—see the Energy to Frequency Conversion section.
LENERGY [39: 0] × 8 × fl
Average Word ( LPF 2) = (16) Note that besides CFNUM and CFDEN registers, changing
LINECYC[13: 0] × CLKIN
APGAIN[11:0] register will also affect the output frequency
where fl is the line frequency. from CF. The APGAIN register has a resolution of 0.0244%/LSB.
Energy Meter Display
Calibrating the Frequency at CF
Besides the pulse output, which is used to verify calibration, a
Once the average active power signal is calculated, it can be
solid state energy meter will very often require some form of
used to determine the frequency at CF before calibration. When
display. The display should show the amount of energy con-
the frequency before calibration is known, the pair of CF fre-
sumed in kWh (kilowatthours). One convenient and simple way
quency divider registers (CFNUM and CFDEN) can be adjusted
to interface the ADE7759 to a display or energy register (e.g.,
so as to produce the required frequency on CF. In this example,
MCU with nonvolatile memory) is to use CF. For example, the
a meter constant of 3200 imp/kWh is chosen as an appropriate
CF frequency could be calibrated to 1,000 imp/kWhr. The
constant. This means that under a steady load of 1 kW, the
MCU would count pulses from CF. Every pulse would be
output frequency on CF would be:
equivalent to 1 watt-hour. If more resolution is required, the CF
3200 imp / kWh 3200 frequency could be set to, say, 10,000 imp/kWh.
Frequency (CF ) = = = 0.8888 Hz
60 min · 60 sec 3600 If more flexibility is required when monitoring energy usage, the
active energy register (AENERGY) can be used to calculate
Assuming the meter is set up with a test current (basic current) energy. A full description of this register can be found in the
of 20 A and a line voltage of 220 V for calibration, the load is Energy Calculation section. The AENERGY register gives the
calculated as 220 V × 20 A = 4.4 kW. Therefore, the expected user both sign and magnitude information regarding energy
output frequency on CF under this steady load condition would consumption. On completion of the CF frequency output cali-
be 4.4 × 0.8888 Hz = 3.9111 Hz. Under these load conditions, bration, i.e., after the active power gain (APGAIN) register has
the transducers on Channel 1 and Channel 2 should be selected been adjusted, a second calibration sequence can be initiated.
such that the signal on the voltage channel should see approxi- The purpose of this second calibration routine is to determine a
mately half scale and the signal on the current channel about 1/8 kWh/LSB coefficient for the AENERGY register. Once the
of full scale (assuming a maximum current of 80 A). The aver- coefficient has been calculated, the MCU can determine the
age value from LPF2 is calculated as 3,276.81 decimal using the energy consumption at any time by reading the AENERGY
calibration mode as described above. Then using Equation 8 contents and multiplying by the coefficient to calculate kWh.
(energy-to-frequency conversion), the frequency under this
load is calculated as: CLKIN FREQUENCY
3276.81 × 3.579545 MHz In this data sheet, the characteristics of the ADE7759 are
Frequency (CF ) = = 349.566 Hz shown with the CLKIN frequency equal to 3.579545 MHz.
225
However, the ADE7759 is designed to have the same accu-
This is the frequency with the contents of the CFNUM and racy at any CLKIN frequency within the specified range. If
CFDEN registers equal to 000h. The desired frequency out is the CLKIN frequency is not 3.579545 MHz, various timing
3.9111 Hz. Therefore, the CF frequency must be divided by and filter characteristics will need to be redefined with the
349.566/3.9111 Hz or 89.3779 decimal. This is achieved by new CLKIN frequency. For example, the cutoff frequencies
loading the pair of CF divider registers with the closest rational of all digital filters (LPF1, LPF2, HPF1, etc.) will shift in
number. In this case, the closest rational number is found to be proportion to the change in CLKIN frequency according to
25/2234 (or 19h/8BAh). Therefore, 18h and 8B9h should be the following equation:
written to the CFNUM and CFDEN registers, respectively.
Note that the CF frequency is divided by the contents of CLKIN Frequency
New Frequency = Original Frequency × (17)
(CFNUM + 1)/(CFDEN + 1). With the CF divide registers 3.579545 MHz
contents equal to 18h/8B9h, the output frequency is given as
The change of CLKIN frequency does not affect the timing
349.566 Hz/89.36 = 3.91188 Hz. Note that this setting has an
characteristics of the serial interface because the data transfer is
error of +0.02%.
synchronized with serial clock signal (SCLK). But one needs to
Calibrating CF is made easy by using the line cycle energy observe the read/write timing of the serial data transfer—see
accumulation mode on the ADE7759, provided that the line Timing Characteristics. Table III lists various timing changes
that are affected by CLKIN frequency.

REV. A –25–
ADE7759
Table III. Frequency Dependencies of the ADE7759 Parameters The communications register is an 8-bit wide register. The
MSB determines whether the next data transfer operation is a
Parameter CLKIN Dependency read or a write. The five LSBs contain the address of the register
Nyquist frequency for CH 1 and 2 ADCs CLKIN/8 to be accessed. See Communications Register section for a more
PHCAL resolution (seconds per LSB) 4/CLKIN detailed description. Figures 42 and 43 show the data transfer
Active Energy register update rate (Hz) CLKIN/4 sequences for a read and write operation, respectively.
Waveform sampling rate (Number of On completion of a data transfer (read or write), the ADE7759
samples per second) once again enters communications mode.
WAVSEL 1, 0 = 0 0 CLKIN/128
0 1 CLKIN/256 CS
1 0 CLKIN/512
SCLK
1 1 CLKIN/1024
COMMUNICATIONS REGISTER WRITE
Maximum ZXTOUT period 524,288/CLKIN
DIN 0 0 0 ADDRESS

SUSPENDING THE ADE7759 FUNCTIONALITY DOUT MULTIBYTE READ DATA

The analog and the digital circuit can be suspended separately.
The analog portion of the ADE7759 can be suspended by set- Figure 42. Reading Data from the ADE7759 via the
ting the ASUSPEND bit (Bit 4) of the mode register to logic Serial Interface
high—see Mode Register section. In suspend mode, all waveform
samples from the ADCs will be set to zeros. The digital circuitry CS
can be halted by stopping the CLKIN input and maintaining
a logic high or low on CLKIN pin. The ADE7759 can be reacti- SCLK

vated by restoring the CLKIN input and setting the ASUSPEND COMMUNICATIONS REGISTER WRITE
bit to logic low. DIN 1 0 0 ADDRESS MULTIBYTE WRITE DATA

APPLICATION INFORMATION
Figure 43. Writing Data to the ADE7759 via the Serial
Application Note AN-564 contains detailed information on how
Interface
to design an ANSI Class 100 watt-hour meter based on the
ADE7756, a pin-to-pin compatible product with the ADE7759. A data transfer is complete when the LSB of the ADE7759
Application Note AN-578 describes an algorithm on how to register being addressed (for a write or a read) is transferred to
calculate the voltage and current rms values using an external or from the ADE7759.
MCU. It is available from the ADE7756 product homepage The serial interface of the ADE7759 is made up of four signals:
under the Application Note link on the energy metering home- SCLK, DIN, DOUT, and CS. The serial clock for a data trans-
page, www.analog.com/energymeter.
fer is applied at the SCLK logic input. This logic input has a
SERIAL INTERFACE Schmitt-trigger input structure, which allows slow rising (and
All ADE7759 functionality is accessible via several on-chip regis- falling) clock edges to be used. All data transfer operations are
ters—see Figure 41. The contents of these registers can be updated synchronized to the serial clock. Data is shifted into the ADE7759
or read using the on-chip serial interface. After power-on, or tog- at the DIN logic input on the falling edge of SCLK. Data is
gling the RESET pin low, or a falling edge on CS, the ADE7759 is shifted out of the ADE7759 at the DOUT logic output on a
placed in communications mode. In communications mode the rising edge of SCLK. The CS logic input is the chip select
ADE7759 expects a write to its communications register. The input. This input is used when multiple devices share the serial
data written to the communications register determines whether bus. A falling edge on CS also resets the serial interface and
the next data transfer operation will be a read or a write and also places the ADE7759 into communications mode. The CS
which register is accessed. Therefore, all data transfer operations input should be driven low for the entire data transfer opera-
with the ADE7759, whether a read or a write, must begin with a tion. Bringing CS high during a data transfer operation will
write to the communications register. abort the transfer and place the serial bus in a high impedance
COMMUNICATIONS state. The CS logic input may be tied low if the ADE7759 is the
DIN REGISTER only device on the serial bus. However, with CS tied low, all
IN
initiated data transfer operations must be fully completed, i.e.,
REGISTER #1
DOUT OUT the LSB of each register must be transferred as there is no other
IN
way of bringing the ADE7759 back into communications mode
REGISTER #2
OUT without resetting the entire device, i.e., using RESET.
REGISTER
REGISTER #3
IN
ADDRESS
Serial Write Operation
OUT
DECODE The serial write sequence takes place as follows. With the
ADE7759 in communications mode (i.e., the CS input logic
low), a write to the communications register first takes place.
The MSB of this byte transfer is a 1, indicating that the data
IN
REGISTER #n –1
OUT
transfer operation is a write. The first five LSBs of this byte
contain the address of the register to be written to. The ADE7759
IN
REGISTER #n
OUT
starts shifting in the register data on the next falling edge of
SCLK. All remaining bits of register data are shifted in on the
Figure 41. Addressing ADE7759 Registers via the falling edge of subsequent SCLK pulses—see Figure 44.
Communications Register
–26– REV. A
 ADE7759
As explained earlier, the data write is initiated by a write to was the case with the data write operation, a data read must be
the communications register followed by the data. During a preceded by a write to the communications register.
data write operation to the ADE7759, data is transferred to With the ADE7759 in communications mode (i.e., CS logic
all on-chip registers one byte at a time. After a byte is trans- low), an 8-bit write to the communications register first takes
ferred into the serial port, there is a finite time before it is place. The MSB of this byte transfer is a 0, indicating that the
transferred to one of the ADE7759 on-chip registers. Although next data transfer operation is a read. The first five LSBs of this
another byte transfer to the serial port can start while the byte contain the address of the register that is to be read. The
previous byte is being transferred to an on-chip register, this ADE7759 starts shifting out of the register data on the next
second byte transfer should not finish until at least 4 µs after rising edge of SCLK—see Figure 46. At this point, the DOUT
the end of the previous byte transfer. This functionality is logic output leaves its high impedance state and starts driving
expressed in the timing specification t6—see Figure 44. If a the data bus. All remaining bits of register data are shifted out
write operation is aborted during a byte transfer (CS brought on subsequent SCLK rising edges. The serial interface also
high), then that byte will not be written to the destination enters communications mode again as soon as the read has been
register. completed. At this point, the DOUT logic output enters a high
Destination registers may be up to 3 bytes wide—see the Regis- impedance state on the falling edge of the last SCLK pulse. The
ter Description section. Therefore, the first byte shifted into read operation may be aborted by bringing the CS logic input
the serial port at DIN is transferred to the MSB (Most Signifi- high before the data transfer is complete. The DOUT output
cant Byte) of the destination register. If the addressed register enters a high impedance state on the rising edge of CS.
is 12 bits wide, for example, a two-byte data transfer must When an ADE7759 register is addressed for a read operation,
take place. The data is always assumed to be right justified: the entire contents of that register are transferred to the serial
therefore, in this case, the four MSBs of the first byte would be port. This allows the ADE7759 to modify its on-chip registers
ignored and the four LSBs of the first byte written to the without the risk of corrupting data during a multibyte transfer.
ADE7759 would be the four MSBs of the 12-bit word. Figure 45 Note that when a read operation follows a write operation, the
illustrates this example. read command (i.e., write to communications register) should
Serial Read Operation not happen for at least 4 µs after the end of the write operation.
During a data read operation from the ADE7759, data is shifted If the read command is sent within 4 µs of the write operation,
out at the DOUT logic output on the rising edge of SCLK. As the last byte of the write operation may be lost. This timing
constraint is given as timing specification t9.
t8
CS
t1 t6
t3
t7 t7
SCLK

t2 t4
t5
DIN 1 0 0 A4 A3 A2 A1 A0 DB7 DB0 DB7 DB0

COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE

Figure 44. Serial Interface Write Timing Diagram

SCLK

DIN X X X X DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE

Figure 45. 12-Bit Serial Write Operation

CS
t1
t13
t9 t10
SCLK

DIN 0 0 0 A4 A3 A2 A1 A0

t11 t11 t12

DOUT DB7 DB0 DB7 DB0

COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE

Figure 46. Serial Interface Read Timing Diagram

REV. A –27–
ADE7759
CHECKSUM REGISTER Note that a read to the CHKSUM register will also generate a
The ADE7759 has a checksum register (CHKSUM[5:0]) to checksum of the CHKSUM register itself.
ensure that the data bits received in the last serial read operation
are not corrupted. The 6-bit checksum register is reset before DOUT CONTENT OF REGISTER (n-bytes)
the first bit (MSB of the register to be read) is put on the DOUT
pin. During a serial read operation, when each data bit becomes +
CHECKSUM REGISTER ADDR: 1Eh
available on the rising edge of SCLK, the bit will be added to +
the checksum register. In the end of the serial read operation,
the content of the checksum register will be the sum of all the
Figure 47. Checksum Register for Serial Interface Read
ones contained in the register previously read. Using the checksum
register, the user can determine if an error has occurred during
the last read operation.

Table IV. Register List

Address Name R/W No. of Bits Default Description

01h WAVEFORM R 24/40 0h The Waveform Register is a read-only register. This register con-
tains the sampled waveform data from Channel 1, Channel 2, or the
active power signal. The data source and the length of the waveform
registers are selected by data bits 14 and 13 in the mode register—
see Channel 1 and 2 Sampling section.
02h AENERGY R 40 0h Active Energy Register. Active power is accumulated (Integrated)
over time in this 40-bit, read-only register. The energy register
can hold a minimum of 11.53 seconds of active energy information
with full-scale analog inputs before it overflows—see Energy Calcu-
lation section.
03h RSTENERGY R 40 0h Same as the active energy register except that the register is reset to
0 following a read operation.
04h STATUS R 8 40h Interrupt Status Register. This is an 8-bit read-only register. The
status register contains information regarding the source of
ADE7759 interrupts—see Interrupts section.
05h RSTSTATUS R 8 0h Same as the interrupt status register except that the register con-
tents are reset to 0 (all flags cleared) after a read operation.
06h MODE R/W 16 000Ch Mode Register. This is a 16-bit register through which most of
the ADE7759 functionality is accessed. Signal sample rates, filter
enabling, and calibration modes are selected by writing to this
register. The contents may be read at any time—see Mode Register
section.
07h CFDEN R/W 12 3Fh CF Frequency Divider Denominator Register. The output fre-
quency on the CF pin is adjusted by writing to this 12-bit read/write
register—see Energy-to-Frequency Conversion section.
08h CH1OS R/W 8 80h Channel 1 Offset Adjust. The MSB is used to enable the digital inte-
grator. Bit 6 is not used. Writing to Bits 0 to 5 allows offsets on
Channel 1 to be removed—see Analog Inputs section and CH1OS
Register section.
09h CH2OS R/W 6 0h Channel 2 Offset Adjust. Writing to this 6-bit register allows any offsets
on Channel 2 to be removed—see Analog Inputs section.
0Ah GAIN R/W 8 0h PGA Gain Adjust. This 8-bit register is used to adjust the gain selec-
tion for the PGA in Channel 1 and 2—see Analog Inputs section.

–28– REV. A
 ADE7759
Address Name R/W No. of Bits Default Description
0Bh APGAIN R/W 12 0h Active Power Gain Adjust. This is a 12-bit register. The active power
calculation can be calibrated by writing to this register. The calibration
range is ±50% of the nominal full-scale active power. The resolution of the
gain adjust is 0.0244%/LSB—see Channel 1 ADC Gain Adjust section.
0Ch PHCAL R/W 8 0h Phase Calibration Register. The phase relationship between Channel 1
and Channel 2 can be adjusted by writing to this 8-bit register. The
valid content of this twos complement register is between 9Eh and
5Ch, which is a phase difference of –2.365∞ to +2.221∞ at 60 Hz in
0.0241∞ steps—see Phase Compensation section.
0Dh APOS R/W 16 0h Active Power Offset Correction. This 16-bit register allows small off-
sets in the Active Power calculation to be removed—see Active Power
Calculation section.
0Eh ZXTOUT R/W 12 FFFh Zero Cross Timeout. If no zero crossings are detected on Channel 2
within a time period specified by this 12-bit register, the interrupt
request line (IRQ) will be activated. The maximum timeout period is
0.15 seconds—see Zero Crossing Detection section.
0Fh SAGCYC R/W 8 FFh Sag Line Cycle Register. This 8-bit register specifies the number of
consecutive half-line cycles the signal on Channel 2 must be below
SAGLVL before the SAG output is activated—see Voltage Sag
Detection section.
10h IRQEN R/W 8 40h Interrupt Enable Register. ADE7759 interrupts may be deactivated at
any time by setting the corresponding bit in this 8-bit enable register to
Logic 0. The status register will continue to register an interrupt event
even if disabled. However, the IRQ output will not be activated—see
Interrupts section.
11h SAGLVL R/W 8 0h Sag Voltage Level. An 8-bit write to this register determines at what
peak signal level on Channel 2 the SAG pin will become active. The
signal must remain low for the number of cycles specified in the
SAGCYC register before the SAG pin is activated—see Line Voltage
Sag Detection section.
12h TEMP R 8 0h Temperature Register. This is an 8-bit register which contains the
result of the latest temperature conversion—see Temperature
Measurement section.
13h LINECYC R/W 4 3FFFh Line Cycle Energy Accumulation Mode Half-Cycle Register. This
14-bit register is used during line cycle energy accumulation mode to
set the number of half-line cycles active energy is accumulated—see
Line Cycle Energy Accumulation Mode section.
14h LENERGY R 40 0h Line Cycle Energy Accumulation Mode Active Energy Register. This
40-bit register accumulates active energy during line cycle energy
accumulation mode. The number of half-line cycles is set by the
LINECYC register—see Line Cycle Energy Accumulation Mode section.
15h CFNUM R/W 2 0h CF Frequency Divider Numerator Register. The output frequency on
the CF pin is adjusted by writing to this 12-bit read/write register—see
Energy to Frequency Conversion section.
1Eh CHKSUM R 6 0h Checksum Register. This 6-bit read-only register is equal to the sum of
all the ones in the previous read—see Serial Read Operation section.
1Fh DIEREV R 8 01h Die Revision Register. This 8-bit read-only register contains the revision
number of the silicon.

REV. A –29–
ADE7759
REGISTER DESCRIPTIONS Communications Register
All ADE7759 functionality is accessed via the on-chip registers. The communications register is an 8-bit, write-only register
Each register is accessed by first writing to the communications that controls the serial data transfer between the ADE7759 and
register and then transferring the register data. A full description the host processor. All data transfer operations must begin with
of the serial interface protocol is given in the Serial Interface a write to the communications register. The data written to the
section. communications register determines whether the next operation
is a read or a write and which register is being accessed. Table V
outlines the bit designations for the communications register.

Table V. Communications Register

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

W/R 0 0 A4 A3 A2 A1 A0

Bit Bit
Location Mnemonic Description
0 to 4 A0 to A4 The five LSBs of the communications register specify the register for the data transfer opera-
tion. Table III lists the address of each ADE7759 on-chip register.
5 to 6 RESERVED These bits are unused and should be set to zero.
7 W/R When this bit is a Logic 1, the data transfer operation immediately following the write to the
Communications register will be interpreted as a write to the ADE7759. When this bit is a
Logic 0, the data transfer operation immediately following the write to the communications
register will be interpreted as a read operation.

–30– REV. A
 ADE7759
Mode Register (06H)
The ADE7759 functionality is configured by writing to the mode register—see Figure 45. Table VI summarizes the functionality of
each bit in the mode register.
Table VI. Mode Register

Bit Bit
Location Mnemonic Description
0 DISHPF The HFP (high-pass filter) in Channel 1 is disabled when this bit is set.
1 DISLPF2 The LPF (low-pass filter) after the multiplier (LPF2) is disabled when this bit is set.
2 DISCF The frequency output CF is disabled when this bit is set.
3 DISSAG The line voltage sag detection is disabled when this bit is set.
4 ASUSPEND By setting this bit to Logic 1, both ADE7759s’ A/D converters can be turned off. In normal
operation, this bit should be left at Logic 0. All digital functionality can be stopped by suspending
the clock signal at CLKIN pin.
5 TEMPSEL The temperature conversion starts when this bit is set to 1. This bit is automatically reset to
0 when the temperature conversion is finished.
6 SWRST Software Chip Reset. A data transfer should not take place to the ADE7759 for at least 18 µs after
a software reset.
7 CYCMODE Setting this bit to Logic 1 places the chip in line cycle energy accumulation mode.
8 DISCH1 ADC 1 (Channel 1) inputs are internally shorted together.
9 DISCH2 ADC 2 (Channel 2) inputs are internally shorted together.
10 SWAP By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and the
analog inputs V1P and V1N are connected to ADC 2.
12, 11 DTRT1, 0 These bits are used to select the waveform register update rate.
DTRT1 DTRT0 Update Rate
0 0 27.9 kSPS (CLKIN/128)
0 1 14 kSPS (CLKIN/256)
1 0 7 kSPS (CLKIN/512)
1 1 3.5 kSPS (CLKIN/1024)
14, 13 WAVSEL1, 0 These bits are used to select the source of the sampled data for the waveform register.
WAVSEL1, 0 Length Source
0 0 24 bits Active Power Signal (output of LPF2)
0 1 40 bits Channel 1 and Channel 2
1 0 24 bits Channel 1
1 1 24 bits Channel 2
15 TEST1 Writing a Logic 1 to this bit position places the ADE7759 in test mode. This is intended for fac-
tory testing only and should be left at 0.

REV. A –31–
ADE7759
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 ADDR: 06H

TEST1 DISHPF
(TEST MODE SELECTION SHOULD BE SET TO 0) (DISABLE HPF1 IN CHANNEL 1)
WAVSEL DISLPF2
(WAVEFORM SELECTION FOR SAMPLE MODE) (DISABLE LPF2 AFTER MULTIPLIER)
00 = LPF2
DISCF
01 = CH1 + CH2 (40-BIT WAVEFORM SAMPLES)
(DISABLE FREQUENCY OUTPUT CF)
10 = CH1
11 = CH2 DISSAG
(DISABLE SAG OUTPUT)
DTRT
(WAVEFORM SAMPLES OUTPUT DATA RATE) ASUSPEND
00 = 27.9kSPS (CLKIN/128) (SUSPEND CH1 AND CH2 ADCs)
01 = 14.4kSPS (CLKIN/256)
STEMP
10 = 7.2kSPS (CLKIN/512)
(START TEMPERATURE SENSING)
11 = 3.6kSPS (CLKIN/1024)
SWRST
(SOFTWARE CHIP RESET)
SWAP
(SWAP CH1 AND CH2 ADCs) CYCMODE
(LINE CYCLE ENERGY ACCUMULATION MODE)
DISCH2
(SHORT THE ANALOG INPUTS ON CHANNEL 2)

DISCH1
(SHORT THE ANALOG INPUTS ON CHANNEL 1)

NOTE: REGISTER CONTENTS SHOW POWER-ON DEFAULTS

Figure 48. Mode Register

Interrupt Status Register (04H)/Reset Interrupt Status Register (05H)

The status register is used by the MCU to determine the source of an interrupt request (IRQ). When an interrupt event occurs in the
ADE7759, the corresponding flag in the interrupt status register is set logic high. If the enable bit for this flag is Logic 1 in the inter-
rupt enable register, the IRQ logic output goes active low. When the MCU services the interrupt, it must first carry out a read from
the interrupt status register to determine the source of the interrupt.

Table VII. Interrupt Status Register, Reset Interrupt Status Register, and Interrupt Enable Register

Bit Interrupt
Location Flag Description
0 AEHF Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the active energy register.
1 SAG Indicates that an interrupt was caused by a SAG on the line voltage or no zero crossings were detected.
2 CYCEND Indicates the end of energy accumulation over an integer number of half line cycles as defined by
the content of the LINECYC register—see Line Cycle Energy Accumulation Mode section.
3 WSMP Indicates that new data is present in the waveform register.
4 ZX This status bit reflects the status of the ZX logic output—see Zero Crossing Detection section.
5 TEMP Indicates that a temperature conversion result is available in the temperature register.
6 RESET Indicates the end of a reset (for both software or hardware reset). The corresponding enable bit has
no function in the interrupt enable register, i.e., this status bit is set at the end of a reset, but it
cannot be enabled to cause an interrupt.
7 AEOF Indicates that the active energy register has overflowed.

–32– REV. A
 ADE7759
7 6 5 4 3 2 1 0
0 1 0 0 0 0 0 0 ADDR: 04H/RESET: 05H

AEOF AEHF
(ACTIVE ENERGY REGISTER OVERFLOW) (ACTIVE ENERGY REGISTER HALF FULL)

RESET SAG
(END OF A HARDWARE OR SOFTWARE RESET) (LINE VOLTAGE SAG DETECT)

TEMP CYCEND
(TEMPERATURE REGISTER READY) (LINE CYCLE ENERGY ACCUMULATION END)

ZX WSMP
(ZERO CROSSING DETECTED) (WAVEFORM SAMPLING)

NOTE: REGISTER CONTENTS SHOW POWER ON DEFAULTS

Figure 49. Interrupt Status Register

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 ADDR: 10H

AEOF AEHF
(ACTIVE ENERGY REGISTER OVERFLOW) (ACTIVE ENERGY REGISTER HALF FULL)
NOT USED SAG
(LINE VOLTAGE SAG DETECT)
TEMP
(TEMPERATURE REGISTER READY) CYCEND
(END OF LINE CYCLE ENERGY ACCUMULATION)
ZX
(ZERO CROSSING DETECTED) WSMP
(WAVEFORM SAMPLING)

NOTE: REGISTER CONTENTS SHOW POWER ON DEFAULTS

Figure 50. Interrupt Enable Register

CH1OS Register (08H)

The CH1OS register is an 8-bit, read/write enabled register. The MSB of this register is used to switch on/off the digital integrator in Chan-
nel 1, and Bits 0 to 5 indicate the amount of the offset correction in Channel 1. Table VIII summarizes the function of this register.

Table VIII. CH1OS Register

Bit Location Bit Mnemonic Description

0 to 5 OFFSET The six LSBs of the CH1OS register control the amount of dc offset correction in Channel 1
ADC. The 6-bit offset correction is sign and magnitude coded. Bits 0 to 4 indicate the magnitude
of the offset correction. Bit 5 shows the sign of the offset correction. A 0 in Bit 5 means the offset
correction is positive and a 1 indicates the offset correction is negative.
6 Not Used This bit is unused.
7 INTEGRATOR This bit is used to activate the digital integrator on Channel 1. The digital integrator is switched
on by setting this bit. This bit is set to be 1 on default.

CH1OS REGISTER*
7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0 ADDR: 08H

DIGITAL INTEGRATOR SELECTION SIGN AND MAGNITUDE CODED

1 = ENABLE OFFSET CORRECTION BITS
0 = DISABLE
NOT USED
*REGISTER CONTENTS SHOW POWER-ON DEFAULT

Figure 51. CH1OS Register

REV. A –33–
ADE7759
OUTLINE DIMENSIONS

20-Lead Shrink Small Outline Package [SSOP]

(RS-20)
Dimensions shown in millimeters

7.50
7.20
6.90

20 11

8.20 5.60
7.80 5.30
7.40 5.00
1 10

1.85
1.75
2.00 MAX 1.65 0.25
0.09
8

0.65 0.38 0.95
0.05 MIN 4

BSC 0.75
0.22 SEATING 0

COPLANARITY PLANE 0.55
0.10
COMPLIANT TO JEDEC STANDARDS MO-150AE

–34– REV. A
 ADE7759
Revision History
Location Page
12/02—Data Sheet changed from REV. 0 to REV. A.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to Figure 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

REV. A –35–
–36–
PRINTED IN U.S.A. C02744–0–12/02(A)