QCA8081

Data Sheet
80-Y0615-1 Rev. K

July 25, 2022

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© 2018-2019, 2022 Qualcomm Technologies, Inc. and/or its subsidiaries. All rights reserved.
Revision history

Revision Date Description

A July 2018 Initial release

B November 2018 ■ Updated Chapter 1.2 Features
■ Updated Table 2-1 Signal to pin descriptions
■ Updated Table 3-2 Operating conditions
■ Added Table 3-15 QCA8081 power consumption
■ Updated Table 4-2 Device marking (top view, not to scale), Table 4-3 Device identification
details, and Table 4-5 Ordering numbers
■ Added Chapter 7.1 Reliability qualification summary and Chapter 7.2 Qualification sample
description
C November 2018 Updated Table 3-15 QCA8081 power consumption
D January 2019 Updated Table 4-3 Device identification details and Table 4-5 Ordering numbers
E January 2019 Updated chip max power in worst case
F September 2019 ■ Updated Tmddl in MDIO AC characteristics table
■ Updated Qualcomm name in device marking
■ Added SR order number, and SR units per reel
G November 2019 Updated Mechanical dimensions
H November 2019 Updated pin descriptions and DC characteristics
Revision I was omitted in accordance with QTI document conventions.
J April 2022 ■ Changed device specification to data sheet
■ Fixed a typo in Table 3-15 QCA8081 power consumption
K July 2022 ■ Updated Tj in Table 3-2 Operating conditions
■ Updated Figure 4-2 Device marking (top view, not to scale)
■ Added a note to Table 4-2 Device marking line definitions

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Contents

Revision history............................................................................................................................................................2
1 Introduction.............................................................................................................................................................. 5
1.1 Device description...........................................................................................................................................5
1.2 Features...........................................................................................................................................................6
1.3 Transmit functionality......................................................................................................................................7
1.4 Receive functionality....................................................................................................................................... 7
2 Pin definitions........................................................................................................................................................... 9
2.1 Pinout diagram................................................................................................................................................9
2.2 I/O parameter definitions..............................................................................................................................10
2.3 Pin descriptions............................................................................................................................................. 10
2.4 Power-on strapping....................................................................................................................................... 13
3 Electrical specifications...........................................................................................................................................14
3.1 Absolute maximum ratings........................................................................................................................... 14
3.2 Operating conditions..................................................................................................................................... 14
3.3 SGMII/SGMII+ characteristics........................................................................................................................15
3.4 AC characteristics.......................................................................................................................................... 17
3.5 DC characteristics.......................................................................................................................................... 18
3.6 Clock characteristics...................................................................................................................................... 19
3.7 Power-on sequence.......................................................................................................................................21
3.8 Power consumption...................................................................................................................................... 21
4 Mechanical information..........................................................................................................................................23
4.1 Device physical dimensions...........................................................................................................................23
4.2 Part marking..................................................................................................................................................24
4.3 Device ordering information......................................................................................................................... 25
4.4 Device moisture-sensitivity level................................................................................................................... 26
4.5 Thermal characteristics................................................................................................................................. 26
5 Carrier, handling, and storage................................................................................................................................ 28
5.1 Carrier............................................................................................................................................................28
5.1.1 Tape and reel information................................................................................................................ 28

5.1.2 Matrix
80-Y0615-1 Rev. K
tray information.................................................................................................................... 293
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 5.2 Storage.......................................................................................................................................................... 30
5.2.1 Bagged storage conditions............................................................................................................... 30
5.2.2 Out-of-bag duration..........................................................................................................................30
5.3 Handling........................................................................................................................................................ 30
5.3.1 Baking............................................................................................................................................... 30
5.3.2 Electrostatic discharge......................................................................................................................30
5.4 Bar code label and packing for shipment......................................................................................................30
6 PCB mounting guidelines........................................................................................................................................ 31
6.1 RoHS compliance...........................................................................................................................................31
6.2 SMT parameters............................................................................................................................................31
6.2.1 Land pad and stencil design............................................................................................................. 31
6.2.2 Reflow profile................................................................................................................................... 32
6.2.3 SMT peak package-body temperature............................................................................................. 33
6.2.4 SMT process verification.................................................................................................................. 33
6.3 Board-level reliability.................................................................................................................................... 33
7 Part reliability..........................................................................................................................................................34
7.1 Reliability qualification summary.................................................................................................................. 34
7.2 Qualification sample description...................................................................................................................35

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1 Introduction

1.1 Device description

The QCA8081 integrates Green ETHOS® power-saving technologies, which significantly save power
in both active operation and idle condition. Green ETHOS power-saving schemes include ultralow
power in cable unplugged mode or port power-down mode. The QCA8081 supports standard IEEE
802.3az Energy Efficient Ethernet (EEE) for 10BASE-Te, 100BASE-TX, and 1000BASE-T.
■ 10BASE-Te: use reduced transmit amplitude.
■ 100BASE-TX and 1000BASE-T: Low Power Idle (LPI) mode to turn off unused analog and digital
blocks to save power when data traffic is idle.
Furthermore, the Wake-on-LAN (WoL) feature manages and regulates total system power
requirements.
The QCA8081 supports both IEEE 1588 V2 and synchronous Ethernet to offer a complete time
synchronization solution.
■ Clock synchronization between slave and master by the exchange of PTP packets. Supports IEEE
1588 V2 by offering a packet parser, accurate timestamping, and insertion to support both one-
step and two-step clock modes.
■ Supports synchronous Ethernet by offering clock output recovered from received data on the
network-line side.
The QCA8081 supports MACsec, which is defined by IEEE 802.1AE to offer hop-by-hop link layer
security based on symmetric key AES-GCM encryption and authentication.
■ Complete inline processing without software intervention in the data path
■ IEEE 802.1AE standard compliant

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QCA8081 Data Sheet Introduction

The QCA8081 embeds Cable Diagnostics Test (CDT) technology for measuring cable length,
detecting the cable status, and identifying remote and local PHY malfunctions, bad or marginal patch
cord segments or connectors.

QCA8081

Dig10

Dig100
TRXP[3:0]
TRXN[3:0] EQ/TR TXP
1 G control SGMII/ TXN
Ethernet IEEE MACsec SerDes
1 G PCS SGMII+
AFE 1588 AFE RXP
PCS
1 G canceler RXN

EQ/TR
2.5 G control 2.5 G
2.5 G LDPC/PCS
canceler

LED WoL interrupt Interrupt MDIO/I2C Reset

LED_[2:0] INTn_WOL INTn MDC MDIO RESETn

Figure 1-1 QCA8081 functional block diagram

1.2 Features
Transmit and receive functions
■ 10BASE-Te/100BASE-TX/1000BASE-T/2500BASE-T IEEE 802.3 compliant
■ Fully integrated digital adaptive equalizers, echo cancelers, and Near End Crosstalk (NEXT)
cancelers
■ Automatic Channel Swap (ACS)
■ Automatic MDI/MDIX crossover
■ Automatic polarity correction
■ IEEE 802.3u compliant autonegotiation
Management interfaces
■ PHY configuration using MDIO or I2C
Power and clock
■ Management interface supports 1.8 V I/O voltage
■ 1.05 V and 1.8 V power supplies for reduced power operation
■ 50 MHz crystal/differential clock/single-ended clock
Power management
■ Green ETHOS® power-saving modes
□ Power saving at media disconnected state
□ Low-power mode

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QCA8081 Data Sheet Introduction

■ IEEE 802.3az
■ WoL to detect magic packet and notify the sleeping system to wake up
ESD
■ Robust Electro-Static Discharge (ESD) protection without external protection circuit
■ Robust lightening surge protection without external protection circuit
Diagnostics
■ Multiple loopback modes for diagnostics
■ Cable Diagnostic Test (CDT)
■ CRC checker and packet counter
MACsec
■ Jumbo frame support up to 12 KB
■ IEEE 802.1AE, AEbn-2011, AEbw-2013 standard compliant
IEEE 1588 PTP
■ Support IEEE 1588 V2
■ Ordinary, boundary, transparent, and grandmaster clock mode
Performance
■ Robust operation over up to 100+ meters of CAT5e cable
Package
■ 7 mm × 7 mm, 56-pin MQFN package
■ Industry temperature option available
■ Heatsink-free design for commercial temperature part

1.3 Transmit functionality

Transmit decoder
■ In 2500BASE-T mode, the Tx data from XGMII interface is 64 B/65 B encoded, scrambled,
encoded by LDPC, and then be mapped to a PAM-16 constellation for transmission on cable.
■ In 1000BASE-T mode, the Ethernet transceiver scrambles Tx data bytes from the MAC interfaces
to 9‑bit symbols and encodes them to 4D five-level PAM signals over the four pairs of Cat5 cable.
■ In 100BASE-TX mode, 4‑bit data from the MII is 4 B/5 B serialized, scrambled, and encoded to a
3-level MLT3 sequence transmitted by the PMA.
■ In 10BASE-Te mode, the Ethernet transceiver transmits and receives Manchester encoded data.

1.4 Receive functionality

Receive decoder
■ In 2500BASE-T mode, the PMA recovers the PAM signals after accounting for the cabling
conditions such as skew among the four pairs, the pair swap order, and the polarity of the pairs.

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QCA8081 Data Sheet Introduction

The resulting code group is decoded into 32‑bit data values. Data stream delimiters are translated
appropriately and data is output to the MAC interfaces.
■ In 1000BASE-T mode, the PMA recovers the 4D PAM signals after accounting for the cabling
conditions such as skew among the four pairs, the pair swap order, and the polarity of the pairs.
The resulting code group is decoded into 8‑bit data values. Data stream delimiters are translated
appropriately and data is output to the MAC interfaces.
■ In 100BASE-TX mode, the receive data stream is recovered and descrambled to align to the
symbol boundaries. The aligned data is then parallelized and decoded to 4‑bit data by 5 B/4 B.
This output runs to the MII receive data pins after data stream delimiters have been translated.
■ In 10BASE-Te mode, the recovered 10BASE-Te signal is decoded from Manchester and then
aligned.
If cable polarity is incorrectly wired, the polarity correction function automatically corrects polarity
errors on the receive pairs in 2500BASE-T, 1000BASE-T, 100BASE-TX, and 10BASE-Te modes.
ADC converter
Each Rx channel includes an advanced high-speed ADC with high resolution for better Signal-to-
Noise Ratio (SNR) and lower error rates.
Echo canceler
Because hybrid circuit is used to transmit and receive simultaneously on each pair, echo occurs when
the transmitter is not perfectly matched to the line. Connector or cable imperfections, such as patch
panel discontinuity and variations in cable impedance along the twisted-pair cable, can also result in
drastic SNR degradation on the Rx signal.
The adaptive digital echo canceler is used to compensate for the varied channel conditions that result
in SNR degradation on the Rx signal.
NEXT canceler
The 1000BASE-T or 2500BASE-T physical layer uses all four twisted pairs to transmit data, which
incurs significant high frequency crosstalk, occurs between adjacent pairs.
Three parallel NEXT cancelers are thus integrated on each Rx channel to cancel high frequency
crosstalk by subtracting an estimate noise signals from the equalizer output.
Baseline wander canceler
Baseline wander occurs on Ethernet links AC-coupled to the transceiver. When the AC-coupling
cannot maintain voltage levels for a specific time, the transmitted pulses are distorted which results in
erroneous sampled values for affected pulses.
The baseline wander cancellation circuit continuously monitors and compensates for this issue,
minimizing the impact of DC baseline shift on the overall error rate.
Adaptive equalizer
The digital adaptive equalizer, using a combination of Feed Forward Equalizer (FFE) and Decision
Feedback Equalizer (DFE), removes intersymbol interference at the receiver by filtering unequalized
signals from ADC output for optimized SNR.

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2 Pin definitions

2.1 Pinout diagram

The QCA8081 device is available in the 56-pin MQFN package that includes an exposed ground pad
for electrical grounding, mechanical strength, and thermal continuity.

SYNC_CLKO_PTP

EVENT_TRG_I
PPS_OUT
XTL_SEL

DVDD18
TRXN0

TRXP0

LED_1

LED_0
DVDD

DVDD
AVDD

AVDD

NC

45

44

43
51

50

49

48

47

46
55

54

53

52
56

AVDD18 1
42 RXN
AVDD 2
41 AVDD
AVDD 3
40 RXP
TRXP1 4
EPAD
39 AVDD
TRXN1 5
38 AVDD
VDD1P25 6
37 TXN
VDD_LDO 7 QCA8081 36 TXP
AVDD 8 56 MQFN
35 RESETn
9
Top View
TRXP2
34 MDIO
TRXN2 10
Exposed Ground 33 MDC
AVDD 11 Pad on Bottom 32 DVDD
AVDD 12
31 INTRPT_GPIO_TDO
AVDD18 13
30 TOD_IN
AVDD 14
29 TOD_OUT
15

16

17

18

19

20

21

22

23

24

25

26

27

28
TRXP3

DVDD
TRXN3

XTLO

XTLI

INTn

DVDD18
AVDD

AVDD

PSS_IN
INTn_WOL

RTC_REFCLK

CLK125_TDI
EVENT_TRG_O

Figure 2-1 QCA8081 56-pin pinout (top view)

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QCA8081 Data Sheet Pin definitions

2.2 I/O parameter definitions

The following nomenclature is used for signal names:

NC No connection should be made to this pin

_n Signal name suffix indicating active low signals
_P Signal name suffix indicating the positive side of a differential signal
_N Signal name suffix indicating the negative side of a differential signal

The following nomenclature is used for signal types:

AI Analog input signal

I Digital input signal
IH Input signals with weak internal pull up to prevent signals from floating when left open
IL Input signals with weak internal pull down to prevent signals from floating when left open
D Open drain
I/O Digital bidirectional signal
AO Analog output signal
O Digital output signal
P Power or ground signal
PD Internal pull-down for input
PU Internal pull-up for input

2.3 Pin descriptions

Symbol Pin Type Description

System interface
XTL_SEL 50 PD, I 50 MHz reference clock input
■ 1 = 50 MHz crystal
■ 0 = 50 MHz differential or single-ended clock
RESETN 35 PD, I Power-on reset, low active
Management interface
MDC 33 PU, I MDIO clock signal
MDIO 34 MDIO MDIO data signal
INTn 22 PU, D PHY interrupt output
(O)
INTn_WOL 23 PU, D Wake-on-LAN interrupt output
(O)
LED interface
LED_0 48 PD, O ■ 0 = 2.5 G link up
■ 1 = 2.5 G link down

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QCA8081 Data Sheet Pin definitions

Symbol Pin Type Description

LED_1 49 PD, O ■ 0 = 1 G link up

■ 1 = 1 G link down
INTRPT_GPIO_TDO 31 PU, O This pin can be configured to the following:
■ LED_2 (default)
□ 0 = link up
□ 1 = link down
□ Blink = traffic
■ MACsec interrupt
■ GPIO
IEEE 1588
PPS_IN 24 PD, I IEEE 1588 PPS input; It can be from GPS or PPS output of another
QCA8081.
PPS_OUT 46 PD, O IEEE 1588 PPS output, generated by digital. Its width can be
configured by the PPSOUT_PUL_WIDTH_0 and
PPSOUT_PUL_WIDTH_1 registers.
RTC_REFCLK 25 PD, I 125 MHz or 200 MHz reference clock input for IEEE 1588 RTC
SYNC_CLKO_PTP 45 PD, O This pin can be configured to the following by the
RTC_EXPANDED_CONFIG[SELECT_OUTPUT_WAVEFORM]
register bit.
■ Variable frequency output, which is synchronized to IEEE 1588 RTC
clock (default).
■ 10 ms pulse output 50% duty cycle, which is synchronized to IEEE
1588 RTC clock.
■ Trigger output
■ A pulse signal indicating trigger of IEEE 1588 event packet in Rx
direction
TOD_IN 30 PD, I ToD input
TOD_OUT 29 PD, O ToD output
CLK125_TDI 27 PD, O This pin can be configured to the following by the
AFE25_CMN_12_DP[AFE25_SYNCE_CLK_CONFIG] register bit.
■ 50 MHz crystal output
■ 125 MHz or 200 MHz PLL output
■ 125 MHz or 200 MHz Sync-E output
EVENT_TRG_I 44 PD, I Event trigger input
EVENT_TRG_O 26 PD, O Event trigger output
Media dependent interface
TRXP0 53 AI, AO MDI pair 0
TRXN0 54 AI, AO
TRXP1 4 AI, AO MDI pair 1
TRXN1 5 AI, AO
TRXP2 9 AI, AO MDI pair 2
TRXN2 10 AI, AO
TRXP3 16 AI, AO MDI pair 3

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QCA8081 Data Sheet Pin definitions

Symbol Pin Type Description

TRXN3 17 AI, AO
Power
AVDD 2 P 1.05 V analog power input (from the VDD_LDO pin)
3
8
11
12
14
15
18
38
39
41
55
56
DVDD 21 P 1.05 V digital power input
32
43
51
AVDD18 1 P 1.8 V analog power input
13
DVDD18 28 P 1.8 V digital power input
47
VDD1P25 6 P 1.25 V to 1.98 V on-chip LDO input
VDD_LDO 7 P 1.05 V LDO power output (to the AVDD pin)
Connect a 1 µF and a 0.1 µF capacitor to stabilize this voltage.
SerDes
TXP 36 AO ■ 1.25 G differential data output for SGMII
TXN 37 AO ■ 3.125 G differential data output for SGMII+

RXP 40 AI ■ 1.25 G differential data input for SGMII

RXN 42 AI ■ 3.125 G differential data input for SGMII+

Other
XTLI 20 AI ■ 50 MHz crystal oscillator input (XTL_SEL = 1)
■ External 50 MHz LVDS reference signal (XTL_SEL = 0, differential
input with XTLO)

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QCA8081 Data Sheet Pin definitions

Symbol Pin Type Description

XTLO 19 AO ■ 50 MHz crystal oscillator output (XTL_SEL = 1)

■ External 50 MHz LVDS reference signal (XTL_SEL = 0, differential
input with XTLI)
NC 52 – –

2.4 Power-on strapping

Pin Power-on Default
Description internal weak
number strapping name pull up/down

Management interface
26 MODE1 MODE[3:1] are latched to select PHY management Pull down
interface.
27 MODE2 Pull down
■ 000 = MDIO
45 MODE3 Pull down
■ 001 = I2C

MDIO PHY address

29 PHYAD4 PHYAD[4:2] are determined by power-on strapping Pull down
configuration. PHYAD[1:0] are fixed: 00 for PHY core,
49 PHYAD3 and 01 for SerDes. Pull down
48 PHYAD2 Pull down
I2C PHY address
29 PHYAD5 PHYAD[5:3] are determined by power-on strapping Pull down
configuration. PHYAD[2:0] are fixed: 000 for PHY core,
49 PHYAD4 and 101 for SerDes. Pull down
48 PHYAD3 Pull down
MDIO pad type
46 OD_SEL_MDIO Control the MDIO pin type Pull down
■ 0 = CMOS
■ 1 = OD

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3 Electrical specifications

3.1 Absolute maximum ratings

The absolute maximum ratings reflect the stress levels that, if exceeded, may cause permanent
damage to the device. No functionality is guaranteed outside the operating specifications.
Functionality and reliability are only guaranteed within the operating conditions described in Operating
conditions.
Table 3-1 Absolute maximum ratings

Symbol Description Max Unit

AVDD18 1.8 V supply voltage 1.98 V

DVDD18 1.8 V supply voltage 1.98 V
VDD1P25 1.25 V to 1.98 V supply voltage 1.98 V
DVDD 1.05 V core supply voltage 1.155 V
AVDD 1.05 V analog supply voltage 1.155 V
Tstore Storage temperature -65 to 150 °C
Vmin Supply voltage min GND-0.5 V

3.2 Operating conditions

Operating conditions include design team-controlled parameters such as power supply voltage and
thermal conditions. The QCA8081 meets all performance specifications listed in SGMII/SGMII+
characteristics, when used within the operating conditions, unless otherwise noted in those sections
(provided the absolute maximum ratings have never been exceeded).
Table 3-2 Operating conditions

Symbol Description Min Typ Max Unit

Power-supply voltages
DVDD18 1.8 V I/O power input 1.7 1.8 1.9 V
AVDD18 1.8 V analog power input 1.7 1.8 1.9 V
VDD1P25 1.25 V to 1.98 V LDO power input for LDO 1.25 1.35 or 1.8 1.98 V
DVDD 1.05 V core supply voltage 0.95 1.05 1.1 V
AVDD 1.05 V analog supply voltage, short to LDO output 0.99 1.05 1.1 V
Thermal conditions

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QCA8081 Data Sheet Electrical specifications

Table 3-2 Operating conditions (cont.)

Symbol Description Min Typ Max Unit

TA Ambient temperature for normal operation (C-temp) 0 – 70 °C

Ambient temperature for normal operation (I-temp) -40 – 85 °C
Tj Junction temperature – – 110 °C

3.3 SGMII/SGMII+ characteristics

Table 3-3 SGMII/SGMII+ transmitter output electrical specifications

Symbol Parameter Min Typ Max Unit

T_Baud Tx baud rate for SGMII 1.25-100 ppm 1.25 1.25+100 ppm GSym/s
Tx baud rate for SGMII+ 3.125-100 ppm 3.125 3.125+100 ppm GSym/s
T_Vdiff Output differential voltage (into Programmable, 1000 by default mV/ppd
floating load Rload = 100 Ω)
T_Rd Differential resistance 80 100 120 Ώ
T_tr, T_tf Output rise/fall time (20% to 80%) 100 – 200 ps
for SGMII
Output rise/fall time (20% to 80%) 60 – 130 ps
for SGMII+
T_Ncm Transmitter common mode noise – – 45 mVppd
for SGMII
Transmitter common mode noise – – 40 mVppd
for SGMII+
T_Vcm Output common mode voltage 400 Half of 600 mV
supply

Table 3-4 SGMII/SGMII+ receiver input electrical specifications

Symbol Parameter Min Typ Max Unit

R_Baud Rx baud rate for SGMII 1.25-100 ppm 1.25 1.25+100 ppm GSym/s
Rx baud rate for SGMII+ 3.125-100 ppm 3.125 3.125+100 ppm GSym/s
R_Vdiff Differential voltage 100 – 2000 mV/ppd
R_Rd Differential resistance 80 100 120 Ώ
R_Vrcm Input common mode voltage (load type 0, -50 – 1150 mV
AC coupling)
Input common mode voltage (load type 1, Not acceptable mV
DC coupling)

Table 3-5 SGMII+ transmit jitter specifications

Symbol Parameters Near end Far end Unit

Max output jitter Total jitter ±0.175 ±0.275 Ul

T_X1 Eye mask 0.175 0.275 Ul

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QCA8081 Data Sheet Electrical specifications

Table 3-5 SGMII+ transmit jitter specifications (cont.)

Symbol Parameters Near end Far end Unit

T_X2 0.39 0.40 Ul

T_Y1 400 100 mV
T_Y2 800 800 mV

T_Y2
T_Y1

Amplitude
0
(mV)

-T_Y1

-T_Y2

0.0 T_X1 T_X2 1-T_X2 1-T_X1 1.0

Time (UI)

Figure 3-1 SGMII+ transmit jitter eye diagram

Table 3-6 SGMII+ receive jitter specifications

Symbol Parameter Min Typ Max Unit

R_DJ Deterministic jitter tolerance 0.37 – – Ulpp

R_DJ_RJ Tolerance to the sum of DJ and RJ 0.55 – – Ulpp
R_SJ_hf Sinusoidal jitter See Figure 3-2 Ulpp

Figure 3-2 SGMII+ receive single tone sinusoidal jitter mask

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QCA8081 Data Sheet Electrical specifications

3.4 AC characteristics
Tmdc

Tmdch Tmdcl

VIH
MDC
VIL

MDIO
VIH
sourced
VIL
by STA

Tmdsu Tmdhold

MDIO VIH
sourced by
QCA8081
VIL
Tmddl

Figure 3-3 MDIO AC timing diagram

Table 3-7 MDIO AC characteristics

Symbol Parameter Min Typ Max Unit

Tmdc MDC period 40 – – ns

Tmdcl MDC low period 16 – – ns
Tmdch MDC high period 16 – – ns
Tmdsu MDIO input setup time to MDC rising 10 – – ns
Tmdhold MDIO input hold time from MDC rising 10 – – ns
Tmddl MDIO output delay from MDC rising 0 6 – ns

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QCA8081 Data Sheet Electrical specifications

Figure 3-4 I2C AC timing diagram

Table 3-8 I2C AC characteristics

Symbol Parameter Min Typ Max Unit

– SCL period 2500 – – ns

– SCL low period 1000 – – ns
– SCL high period 1000 – – ns

3.5 DC characteristics
Table 3-9 MDIO/MDC/I2C/IEEE 1588 v2 DC characteristics — 1.8 V I/O supply

Symbol Parameter Min Max Unit

VIH Input high voltage 1.4 2.1 V

VIL Input low voltage GND - 0.3 0.4 V
VOH Output high voltage 1.6 2.0 V
VOL Output low voltage GND - 0.3 0.3 V
IIH Input high current – 0.1 V
IIL Input low current - 0.1 – V

Table 3-10 RESETn input DC characteristics — 1.8 V I/O supply

Symbol Parameter Min Max Unit

VIH Input high voltage 1.4 2.1 V

VIL Input low voltage GND - 0.3 0.4 V

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3.6 Clock characteristics

The QCA8081 supports crystal, external LVDS differential, and single-ended clock inputs as
reference. The basic principle for selecting crystal and load capacitance is to make the oscillation
stable at 50 MHz ± 50 ppm. Crystal with 50 MHz ± 20 ppm frequency stability is preferred with two
12 pF NPO ceramic capacitors. The capacitors can be changed according to actual crystal selection
and board level test results under full application temperature and voltage ranges.

XTLO
50 MHz XTLI QCA8081
2 1

3
12 pF 12 pF

Table 3-11 Recommended crystal parameters

Symbol Parameter Min Typ Max Unit

FL Nominal frequency 50 MHz

– Oscillation mode Fundamental –
CL Load capacitance 8 pF
– Frequency tolerance (at 25°C ± 3°C) ±10 ppm
– Frequency stability (operating temperature reference 25°C) ±20 ppm
– Operating temperature -40 ~ 85 °C
– Aging (first year) ±1 ppm
DL Drive level – 100 – uW
Rr Effective resistance Rr – – 40 Ω
C0 Shunt capacitance C0 – – 3 pF
– Insulation resistance (at DC 100 V) 500 – – MΩ
– Storage temperature range -40 ~ 85 °C

Table 3-12 External clock input characteristics

Symbol Parameter Min Typ Max Unit

REF_CLK_FREQ Reference clock frequency 50 - 50 ppm 50 50 + 50 ppm MHz

REF_CLK_DC Clock duty cycle, differential 40 50 60 %
REF_CLK_RISE Reference clock rise time measured at 20% to – – 1 ns
80% points, single-ended
REF_CLK_FALL Reference clock fall time measured at 20% to – – 1 ns
80% points, single-ended
VDREF_CLK Differential input swing 0.4 – – V

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Table 3-12 External clock input characteristics (cont.)

Symbol Parameter Min Typ Max Unit

VOLREF_CLK Single-ended input logic low -0.3 – 0.3 V

VOHREF_CLK Single-ended input logic high 0.7 – 1.3 V
JitterRMS Period RMS jitter (10 KHz to 3 MHz) – – 3 ps
Jitterpk-pk Period peak-to-peak jitter (10 KHz to 3 MHz) – – 42 ps

Table 3-13 RTC_REFCLK input characteristics

Symbol Parameter Min Typ Max Unit

FIN Frequency -50 ppm 125 or 200 +50 ppm MHz

DC Duty cycle 40 50 60 %
TRISE Rise time – – 1.5 ns
TFALL Fall time – – 1.5 ns
VIH Input high voltage 1.4 – 2.1 V
VIL Input low voltage GND - 0.3 – 0.3 V
CIN Cin load capacitance – 1 2 V
JitterRMS Period RMS jitter (broadband) – – 10 ps
Jitterpk-pk Period peak-to-peak jitter (broadband) – – 150 ps

Table 3-14 RTC_REFCLK output characteristics

Symbol Parameter Min Typ Max Unit

DC Duty cycle 45 50 55 %
TRISE Rise time (10% to 90%) – – 0.8 ns
TFALL Fall time (10% to 90%) – – 0.8 ns
VOH Output high voltage 1.6 1.8 2.0 V
VOL Output low voltage -0.3 – 0.3 V

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3.7 Power-on sequence

If crystal is used, clock will be present about 2 ms after both AVDD and AVDD18 power-up.

DVDD
10 ms (required for external power)

DVDD18/AVDD18

VDD1P25
0.2 ms (required for LDO to settle)

VDD_LDO

AVDD
2 ms (required for XTL to oscillate)

Crystal 50 MHz

PAD reset 10 ms diglitch

3.8 Power consumption

The power consumption is measured at the following operation condition.
■ Bidirection throughput
■ Full duplex
■ Full speed
■ Random packet
■ Default IPG

Table 3-15 QCA8081 power consumption

Current (mA) Power consumption (W)

Cable Ambient Chip
Mode temperature 1.05 V 1.05 V
(m) 1.8 V (AVDD18/ (DVDD 1.8 V (AVDD18/ (DVDD (W)
(°C) DVDD18+VDD1P25) DVDD18+VDD1P25)
+AVDD) +AVDD)

2.5 G 30 25 225 683 0.41 0.72 1.13

100 261 704 0.47 0.74 1.21
1G 30 288 97 0.52 0.10 0.63
100 288 98 0.52 0.10 0.63
100 M 30 90 57 0.16 0.06 0.23
100 89 56 0.16 0.06 0.23
802.3az, 30 155 71 0.28 0.07 0.36
1G
Link 26 4.79 0.05 0.01 0.05
down

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The chip max power in worst case (100 m cable, T case 110°C) is 1.6 W.
Table 3-16 QCA8081 power consumption (worst case)

Current (mA) Power consumption (W)

Cable Case Chip
Mode temperature 1.05 V 1.05 V
(m) 1.8 V (AVDD18/ (DVDD 1.8 V (AVDD18/ (DVDD (W)
(°C) DVDD18+VDD1P25) DVDD18+VDD1P25)
+AVDD) +AVDD)

2.5 G 100 110 283 1038 0.51 1.09 1.6

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4 Mechanical information

4.1 Device physical dimensions

The QCA8081 device is available in the 7 mm × 7 mm × 0.90 mm 56 MQFN package that includes a
ground pad for improved grounding, mechanical strength, and thermal continuity. Pin 1 is located by
an indicator mark on the top of the package.

Figure 4-1 QCA8081 mechanical dimensions, top and bottom view

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Table 4-1 Mechanical dimensions

Dimension label Min Norm Max Unit

A – – 0.90 mm
A1 0.00 – 0.05 mm
A2 – 0.65 0.70 mm
A3 0.203 REF mm
b 0.15 0.20 0.25 mm
D 7.00 BSC mm
D2 3..50 3.60 3.70 mm
E 7.00 BSC mm
E2 3.50 3.60 3.70 mm
L 0.30 0.40 0.50 mm
e 0.40 BSC mm
R 0.075 – – mm
aaa 0.05 mm
bbb 0.07 mm
ccc 0.10 mm
ddd 0.05 mm
eee 0.08 mm
fff 0.10 mm
Package outline drawing: NT90-ND500-3 Rev. A

4.2 Part marking

Figure 4-2 Device marking (top view, not to scale)

Table 4-2 Device marking line definitions

Line Marking Description

P1 Qualcomm Qualcomm name

P2 [PRODUCT] QTI product name
■ QCA8081
P3 [VARIANT] Device variant information

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Table 4-2 Device marking line definitions (cont.)

Line Marking Description

T1 FAYWWXXX ■ F = supply source code

□ F = F (TSMC)
■ A = assembly site code
□ A = E (ASE, Taiwan)
□ A = K (SPIL, Taiwan)
■ Y = single/last digit of year
■ WW = two-digit work week of year specified by Y
■ XXX = traceability number
• Pin 1 indicator

NOTE Only the last 3 digits (YWW) of date code are marked on the device due to space
limitation, the complete date code information can be found on the product label of device
and the product label definition can be referred to IC Products Packing Method document
(80-VK055-1).

4.3 Device ordering information

The Oracle short description is used to order QTI products, and is present on both the customer label
and this document. The short description includes the product name, configuration code, package
type, product revision code, and source code of the part.
This device can be ordered using the identification code.

Device ID
AAA-AAAA — P — CCC DDDD — EE — RR — S
code

Symbol Product Config Number Package Shipping Product Source

definition name code of pins type package revision config

Example QCA-8081 — 0 — 56 MQFN — MT — 02 — 0

Figure 4-3 Device identification code

Device identification details for all sample available to date are summarized.
Table 4-3 Device identification details

Device Sample type Variant (PRR) Shipping package S value

QCA8081 CS 002 TR 0
C-temp 002 MT 0
002 SR 0
CS 102 TR 0
I-temp 102 MT 0

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Table 4-3 Device identification details (cont.)

Device Sample type Variant (PRR) Shipping package S value

102 SR 0
■ P = product configuration code, RR = product revision code
■ TR = tape and reel, MT = matrix tray, SR = short reel
■ S is the source configuration code that identifies all the qualified die fabrication-source combinations
available at the time a particular sample type was shipped.

Table 4-4 Source configuration code

S value Die F value = F

0 Digital TSMC

Table 4-5 Ordering numbers

Ordering numbers

QCA-8081-0-56MQFN-MT-02-0 CS C-temp
QCA-8081-0-56MQFN-TR-02-0
QCA-8081-0-56MQFN-SR-02-0
QCA-8081-1-56MQFN-MT-02-0 CS I-temp
QCA-8081-1-56MQFN-TR-02-0
QCA-8081-1-56MQFN-SR-02-0

4.4 Device moisture-sensitivity level

Plastic-encapsulated surface mount packages are susceptible to damage induced by absorbed
moisture and high temperature. A package’s moisture-sensitivity level (MSL) indicates its ability to
withstand exposure after it is removed from its shipment bag, while it is on the factory floor awaiting
PCB installation. A low MSL rating is better than a high rating; a low MSL device can be exposed on
the factory floor longer than a high MSL device.
Qualcomm Technologies Inc. follows the latest IPC/JEDEC J-STD-020 standard revision for moisture-
sensitivity qualification. The QCA8081 is classified as MSL3; the qualification temperature was 255ºC.

4.5 Thermal characteristics

Table 4-6 Thermal resistance

Symbol Parameter Comment Typical Unit

θJA Junction-to-Ambient ■ Jedec JESD51-2A 32.8 °C/W

■ Jedec JESD51-7
θJB Junction-to-Board ■ Jedec JESD51-7 20 °C/W
■ Jedec JESD51-8
■ Cold plate ring maintained at 25°C at top and bottom of
PCB

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Table 4-6 Thermal resistance (cont.)

Symbol Parameter Comment Typical Unit

θJC Junction-to-Case ■ No thermal vias 17.5 °C/W

■ Jedec JESD51-7
■ Jedec JESD51-8
■ Cu block at top of package maintained at 25°C
ΨJT Junction-to-Top ■ Jedec JESD51-2A 0.6 °C/W
■ Jedec JESD51-7

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5 Carrier, handling, and storage

5.1 Carrier

5.1.1 Tape and reel information

All QTI tape carrier systems conform to EIA-481 standards.
Simplified sketches of the QCA8081 tape carrier is shown, including the proper part orientation. Tape
and reel details for the QCA8081 are as follows:
■ Reel diameter: 330 mm
■ Hub diameter: 178 mm
■ Tape width: 16 mm
■ Pocket pitch: 12 mm
■ Tape feed: Single
■ Units per reel: 2000 (TR), 500 (SR)

Figure 5-1 Tape orientation on reel

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Figure 5-2 Part orientation in tape

5.1.2 Matrix tray information

All QTI matrix tray carriers confirm to JEDEC standards.
The device pin 1 is oriented to the chamfered corner of the matrix tray.
Each tray of the QCA8081 contains up to 260 devices. Production orders of the QCA8081 that are
shipped in matrix tray carriers will be in 10 + 1 tray stacks of 2600 units. The stacking configuration
and quantity for sample orders will vary.

Figure 5-3 Matrix tray part orientation

Table 5-1 Matrix tray key attributes and dimensions

Array 10 × 26 = 260
M 10.35 mm
M1 10.00 mm
M2 11.80 mm
M3 12.80 mm

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5.2 Storage

5.2.1 Bagged storage conditions

QCA8081 devices delivered in tape and reel carriers must be stored in sealed, moisture barrier,
antistatic bags. See IC Products Packing Method (80-VK055-1) for the expected shelf life.

5.2.2 Out-of-bag duration

The out-of-bag duration is the time a device can be on the factory floor before being installed onto a
PCB. It is defined by the device MSL rating, as described in Device moisture-sensitivity level.

5.3 Handling
Tape handling is described in Tape and reel information. Other (IC-specific) handling guidelines are
presented in the following subsections.

5.3.1 Baking
It is not necessary to bake the QCA8081 if the conditions specified in Bagged storage conditions and
Out-of-bag duration have not been exceeded.
It is necessary to bake the QCA8081 if any condition specified in Bagged storage conditions and Out-
of-bag duration has been exceeded. The baking conditions are specified on the moisture-sensitive
caution label attached to each bag; see IC Products Packing Method (80-VK055-1) for details.

CAUTION If baking is required, the devices must be transferred into trays that can be baked to at
least 125°C. Devices should not be baked in tape and reel carriers at any
temperature.

5.3.2 Electrostatic discharge

Electrostatic discharge (ESD) occurs naturally in laboratory and factory environments. An established
high-voltage potential is always at risk of discharging to a lower potential. If this discharge path is
through a semiconductor device, destructive damage may result.
ESD countermeasures and handling methods must be developed and used to control the factory
environment at each manufacturing site.
QTI products must be handled according to the ESD Association standard: ANSI/ESD S20.20-1999,
Protection of Electrical and Electronic Parts, Assemblies, and Equipment.

5.4 Bar code label and packing for shipment

See IC Products Packing Method (80-VK055-1) for all packing-related information, including bar code
label details.

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6 PCB mounting guidelines

6.1 RoHS compliance

The device is externally lead-free and RoHS-compliant. Qualcomm defines its lead-free (or Pb-free)
semiconductor products as having a maximum lead concentration of 1000 ppm (0.1% by weight) in
raw (homogeneous) materials and end products. Qualcomm package environmental programs, RoHS
compliance details, and tables defining pertinent characteristics of all Qualcomm IC products are
described in the IC Package Environmental Roadmap (80-V6921-1).

6.2 SMT parameters

The information presented in this section describes Qualcomm board-level characterization process
parameters. It is included to assist customers when starting their SMT process development; it is not
intended to be a specification for customer SMT processes.

NOTE Qualcomm recommends that customers follow their solder paste vendor
recommendations for the screen-printing process parameters and reflow profile
conditions.

Qualcomm characterization tests attempt to optimize the SMT process for the best board-level
reliability possible. This is done by performing physical tests on evaluation boards, which may include:
■ Drop shock
■ Temperature cycling
■ Bend cycle (optional)

6.2.1 Land pad and stencil design

Qualcomm recommends characterizing the land patterns according to each customer's processes,
materials, equipment, stencil design, and reflow profile prior to PCB production. Optimizing the
solder stencil-pattern design and print process are critical to ensure print uniformity, decrease voiding,
and increase board-level reliability. See QCA DRQFN Surface Mount Requirements (80-Y7781-1) for
characterization.

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6.2.2 Reflow profile

Table 6-1 Typical SMT reflow profile conditions (for reference only)

Lead-free (high temperature

Profile stage Description Temp range condition limits)

Preheat Initial ramp < 150°C 3°C/sec max

Soak Dry out and flux activation 150°C to 190°C 60 to 120 sec
Ramp Transition to liquidus (solder- 190°C to 220°C < 30 sec
paste melting point)
Reflow Time above liquidus 220°C to 245°C 50 to 70 sec
Cool down Cool rate – ramp to ambient < 220°C 6°C/sec max
NOTE During the reflow state, the peak temperature should not exceed 245°C. This temperature should
not be confused with the peak temperature reached during MSL testing.

Figure 6-1 Typical SMT reflow profile

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6.2.3 SMT peak package-body temperature

During a production board’s reflow process, the temperature for the package must be controlled. The
recommended peak temperature during production assembly is 245°C. This is comfortably above the
solder melting point (220°C), yet well below the proven temperature reached during qualification
(255°C or more).
Although the solder-paste manufacturer’s recommendations for optimum temperature and duration for
solder reflow must be followed, the Qualcomm recommended limits must not be exceeded.

6.2.4 SMT process verification

Qualcomm recommends verification of the SMT process prior to high-volume PCB fabrication,
including:
■ Electrical continuity
■ X-ray inspection of the package installation for proper alignment, solder voids, solder balls, and
solder bridging
■ Visual inspection
■ Cross-section inspection of solder joints to confirm registration, fillet shape, and print volume

6.3 Board-level reliability

Qualcomm conducts characterization tests to assess the device’s board-level reliability, including the
following physical tests on evaluation boards:
■ Drop shock (JESD22-B111)
■ Temperature cycling (JESD22-A104)
■ (Optional) Cyclic bend testing (JESD22-B113)
See Board-level Reliability (BR80-NT096-1) for details.

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7 Part reliability

7.1 Reliability qualification summary

Table 7-1 Silicon reliability results

Tests, standards, and conditions Sample size Result

ELFR in DPPM Cumulative from Pass

other TSMC 28nm
HTOL: JESD22-A108-A LPP products DPPM < 1000
(Total samples from three different wafer lots)
HTOL in FIT (λ) failure in billion device hours 77x3 lots Pass
HTOL: JESD22-A108-A FIT < 50
(Total samples from three different wafer lots)
Mean time to failure (MTTF) t = 1/λ in million hours 77x3 lots > 20
(Total samples from three different wafer lots)
ESD – Human-body model (HBM) rating 3 Pass +/-2kV
JESD22-A114-F
(Total samples from one wafer lot)
ESD – Charged-device model (CDM) rating 3 Pass +/-500V
JESD22-C101-D
(Total samples from one wafer lot)
Latch-up (I-test): EIA/JESD78A 3 Pass
Trigger current: ±100 mA; temperature: 85°C
(Total samples from one wafer lot)
Latch-up (Vsupply overvoltage): EIA/JESD78A 3 Pass
Trigger voltage: Each VDD pin, stress at 1.5 × Vddmax per device
specification; temperature: 85°C
(Total samples from one wafer lot)

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Table 7-2 Package reliability results

Tests, standards, and conditions SPIL ASE KH Result

Moisture resistance test (MRT): J-STD-020/JESD22-A113-F 231x6 lots 231x6 lots Pass
Reflow at 260 +0/-5°C
(Total samples from three different assembly lots)
Temperature cycle: JESD22-A104 77x6 lots 77x6 lots Pass
Temperature: -65°C to 150°C; number of cycles: 1000
Soak time at minimum/maximum temperature: 8–10 minutes
Cycle rate: 2 cycles per hour (CPH)
Preconditioning: JESD22-A113-F
MSL 3, reflow temperature: 260 +0/-5°C
(Total samples from three different assembly lots)
Unbiased highly accelerated stress test: JESD22-A118 77x6 lots 77x6 lots Pass
130°C/85% RH and 96-hour duration
Preconditioning: JESD22-A113
MSL 3, reflow temperature: 260 +0/-5°C
(Total samples from three different assembly lots)
Biased highly accelerated stress test: JESD22-A110 77x3 lots 77x3 lots Pass
130°C/85% RH and 96-hour duration
Preconditioning: JESD22-A113
MSL 3, reflow temperature: 260 +0/-5°C
(Total samples from three different assembly lots)
High-temperature storage life: JESD22-A103 77x6 lots 77x6 lots Pass
Temperature 150°C, 500, 1000 hours
(Total samples from three different assembly lots)
Physical dimensions: JESD22-B100-A 5x3 lots 5x3 lots Pass
(Total samples from three different assembly lots at each SAT)
Die shear 5x3 lots 5x3 lots Pass
MIL-STD-883E, Method 2019
(Total samples from three different assembly lots at each SAT)

7.2 Qualification sample description

Table 7-3 Device characteristics

Category Definition

Device name QCA8081

Package type 56 MQFN
Package body size 7.0 × 7.0 × 0.90 mm

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Table 7-3 Device characteristics (cont.)

Category Definition

Pin count 56
Fab process 28 nm LPP

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