CSE-3103: Microprocessor and Microcontroller

Dept. of Computer Science and Engineering

University of Dhaka

Prof. Sazzad M.S. Imran, PhD

Dept. of Electrical and Electronic Engineering
sazzadmsi.webnode.com
 Course Outline
Syllabus:
8086 microprocessor: Microcontrollers:
architecture, 8051 microcontroller,
instruction set, architecture,
interrupts and 8259A, operation and instruction set,
higher versions of 8086. interfacing: memory, I/O,
external devices.
Pentium microprocessor:
architecture, Programmable Logic Controller (PLC):
register sets, structures,
addressing modes, programming,
instruction set, relays and counters,
interrupt. data control,
I/O control.
Next generation microprocessors:
Intel core architecture,
Intel dual core,
core 2 duo/2 quad/i,
ARM.
 Course Outline
Reference Books:
(1) Intel Microprocessor: Architecture, Programming and Interfacing, B. Brey.
(2) ARM System-on-Chip Architecture; Steve Furber.
(3) The 8051 Microcontroller A Systems Approach; Mazidi & McKinlay.
(4) Programmable Logic Controllers; Frank D. Petruzella.

Class Hour: Notices:

Sunday: 08.30am ~ 10.00am Available at- sazzadmsi.webnode.com
Wednesday: 08.30am ~ 10.00am Class code @google-classroom- r3h2ukwc

Marks Distribution:
Place: (1) Attendance: 5
Room #429, Dept. of CSE, DU (2) Incourse: 25
(3) Final: 70 (5 out of 7; 5×14=70; 3 hours)
Incourse Exam:
Only one compulsory incourse exam will be taken.
5 questions will be given from any consecutive 6 lectures.
Students have to answer all 5 questions in 1.30 hour (marks- 5×5=25).
 Microprocessors and Microcontrollers
Microprocessor executes lists of instructions, called programs.

2 types of processors  i) Microprocessor,

ii) Microcontroller.

Microprocessors 
CPU on single chip,
requires  external memory devices,
I/O ports to connect I/O devices.

2 types of memories  i) RAM- storage of data.

ii) ROM- storage of programs, start-up program.

Microcontrollers 
inside single chip  CPU,
memory units,
I/O ports.
used to control and operate smart machines.
 Evolution of Microprocessor
1930 mechanical calculating devices, used mechanical relays.
1950 vacuum tubes, quickly replaced by transistors.
1960 introduction of minicomputers.
1970 introduction of personal computer.

6 generations of microprocessors evolution 

1st generation (1971-1973):
Processed instructions serially.
4-bit 4004 microprocessors by Busicom and Intel.
Ran at 108 kHz, contained 2300 transistors.
Used PMOS technology- low cost, slow speed, low output currents.
Not compatible with TTL.
8-bit 8008 and 8080 microprocessors by Intel.

2nd generation (1974-1978):

Efficient 8-bit microprocessors- Motorola’s 6800, 6809, Intel’s 8085, Zilog’s Z80.
Used NMOS technology- faster speed, higher density.
 Evolution of Microprocessor
3rd generation (1978-1980):
Dominated by Intel’s 8086 and Zilog’s Z8000.
16-bit processors with minicomputer-like performance.
16-bit arithmetic and pipelined instruction processing.
IC transistor counts ≈ 250,000.
Used high density MOS (HMOS) technology.

4th generation (1981-1995):

Contained ≥ 1 million transistors.
Beginning of 32-bit microprocessors- Intel 80386, Motorola 68020/68030.
Used high density, high speed CMOS (HCMOS).

5th generation (1996-2000):

Employ decoupled superscalar processing.
Contain ≥ 10 million transistors.
Devices carry on-chip functionalities.
Introduced high speed memory and I/O devices.
64-bit microprocessors- Intel Pentium, Celeron, AMD Athlon.
 Evolution of Microprocessor
6th generation (2000-till date):
High-speed cache, advanced pipelining, parallel execution.
Multi-core processors- Intel Core i3/i5/i7/i9, AMD Ryzen, Apple M1/M2.
Used in PCs, laptops, smartphones, servers, AI applications.

Timeline of microprocessor 
1971 Intel 4004 4-bit processor 2300 transistors 108 kHz
1971 Intel 8008 3500 transistors 200 kHz
1974 Intel 8080 8-bit processor 6000 transistors Up to 2 MHz
1976 Intel 8085 6500 transistors 3-5 MHz
1978 Intel 8086 16-bit processor
1979 Intel 8088 29,000 transistors 5 MHz, 8 MHz, 10 MHz
1985 Intel 80386 32-bit chip 275,000 transistors 5 MIPS
1989 Intel 80486 8 KB shared cache memory 25 to 100 MHz
1993 Intel Pentium 32-bit address bus Two 8 KB dedicated cache Superscalar architecture
64-bit data bus 20-stage pipeline Up to 1.75 GHz
3-level cache memory
 Evolution of Microprocessor
Timeline of microprocessor 
1997 Intel Pentium II Processes video, MMX audio, graphics data 200 MHz, 233 MHz,
266 MHz, 300 MHz
1999 Intel Celeron 512 KB L2 cache 9.5 million transistors 600 MHz
Pentium III
2000 Intel Pentium 4 42 million transistors 1.4-3.8 GHz
2005 Intel Pentium-D Dual-core chips 233 million transistors
2008 Intel Core i3, i5, Up to 8 cores on single chip 995 million transistors
i7, i9 Large L2 cache (2-12 MB)
Introduction of L3 cache
2023 Apple M2 Advanced 5 nm, 7 nm fabrication Up to 80 billion
AMD Ryzen AI and GPU integration improving transistors
Intel Raptor Lake
 Technological Improvement
Technological improvements  taking place rapidly,
microprocessor,
microcomputer,
personal computer systems.
1) Increase in data bus/address bus width.
2) Increase in processing speed.
3) Reduction in size and increase in capability.
4) Increase in transistor count and integration.
5) Development of external peripherals.
6) Increase in memory unit size and speed.
7) On-chip cache memory introduction and enhancement.
8) Reduction of power consumption.
9) Multi-core architecture and parallel processing.
10) Integration of peripherals and controllers.
11) Integration of GPU cores, AI accelerators and neural engines.
CSE-3103: Microprocessor and Microcontroller
Dept. of Computer Science and Engineering
University of Dhaka

Prof. Sazzad M.S. Imran, PhD

Dept. of Electrical and Electronic Engineering
sazzadmsi.webnode.com
Basic Architecture of 8086
8086 microprocessor 
2 separate functional units.
1) Bus Interface Unit (BIU),
2) Execution Unit (EU).
employs parallel processing.

BIU  segment registers,

instruction pointer,
address generation and
bus control logic block,
instruction queue.

EU  general purpose registers,

ALU,
control unit,
instruction register,
flag (or status) register.
Basic Architecture of 8086
Main jobs of BIU 
external bus operations.
instruction fetching,
reading/writing of data/operands for memory,
inputting/outputting of data for peripheral devices.
filling instruction queue.
address generation.

Main jobs of EU 
decoding/execution of instructions.
accepts instructions from instruction queue,
data from  general purpose registers,
or memory.
generates operand addresses, hands them to BIU.
tests and updates status of flags in control register
when executing instructions.
waits for instructions from empty instruction queue.
 Operations of Instruction Queue
Pipelining procedure saves time 
 Operations of Instruction Queue
Queue operation 

CS:IP = odd  1 byte instruction

even  2 bytes instruction
 Registers of 8086
Fourteen 16-bit registers 

Register groups 
data group 
AX, BX, CX, DX.
use bytewise or wordwise.
source or destination of operand.
pointers and index group 
SP, BP, SI, DI, IP.
segment group 
ES, CS, DS, SS.
status and control flag group 
single 16-bit flag register.

registers for specific operations 

CX = count register in string operations.
DX = hold address of I/O port.
AX = hold data for I/O operations.
BX = hold offset address.
 CPU Registers
Fourteen 16-bit registers 