Microcontroller-8051

by Dr. Rashmi Panda

Dept. of Electronics and communication Engineering
INDIAN INSTITUTE OF INFORMATION TECHNOLOGY, RANCHI
Microprocessor Based System

CPU
External RAM, ROM, I/O
(No internal RAM, ROM, I/O ports in the CPU)

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Microcontroller

 A smaller computer on a CHIP

 On-chip RAM, ROM, I/O Ports, Timer, Serial Controller…
 Example: Motorola’s 6811, Intel’s 8051, Atmel 32

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 Microprocessor vs. Microcontroller

Microprocessor Microcontroller
 CPU is stand-alone, RAM,  CPU, RAM, ROM, I/O and
ROM, I/O, timer are timer are all on a single
separate chip

 Designer can decide on the  Fixed amount of on-chip

amount of ROM, RAM and ROM, RAM, I/O ports df
I/O ports. dfdfdfdfdfdfdf

 Expansive  Not Expansive

 Versatility  Single-purpose

 General-purpose  Special Purpose.

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C based Embedded Systems

 Special purpose computing system usually completely

inside the device it controls
 Has specific requirements and performs pre-defined
tasks
 Cost reduction compared to general purpose processor
 Different design criteria
 Performance
 Reliability
 Availability
 Safety

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Examples

8051
6 Microcontroll
er
8051 Microcontoller

 Intel introduced 8051, referred as MCS- 51, in 1981.

 The 8051 is an 8-bit processor

 The CPU can work on only 8 bits of data at a time

 The 8051 became widely popular after allowing other

manufactures to make and market any flavor of the
8051.
Features of 8051
 8 bit Processor
 4KB Internal ROM
 128 Bytes Internal RAM
 Four 8 BIT I/O PORTS (32 I/O LINES)
 Two 16 Bit Timers/Counters
 On Chip Full Duplex UART for Serial Communication
 5 Vector Interrupts
 On Chip Clock Oscillator
 16 bit Address bus
 64k External Code Memory
 64k External Data Memory
 16-bit program counter to access external Code Memory and
 16 bit Data Pointer to access external Data Memory
 128 user defined flags
 32 General Purpose Registers each of 8 bits
 Harvard architecture
Harvard Architecture

In Harvard Architecture the data and instructions are stored

in separate memory units each with their own bus.
Advantages:
▪ Speeding up the data transfer rate,
▪ Permits the designer to implement different bus widths and
word sizes for program and data memory space.
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Pin Diagram

8051 family members (e.g., 8751, 89C51, 89C52,

DS89C4x0)
Have 40 pins dedicated for various functions such as
I/O, RD, WR, address, data, and interrupts.
Come in different packages, such as
DIP(dual in-line package),
QFP(quad flat package), and
LLC(leadless chip carrier)

Some companies provide a 20-pin version of the 8051

with a reduced number of I/O ports for less demanding
applications
XTAL1 and XTAL2
 The 8051 has an on-chip oscillator but requires an external crystal to run it
 A quartz crystal oscillator is connected to inputs XTAL1 (pin19) and XTAL2 (pin18)
 The quartz crystal oscillator also needs two capacitors of 30 pF value
 The original 8051 operates at 12 MHZ

8051
11 Microcontroll
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RST
 RESET pin is an input and is active high
 Upon applying a high pulse to this pin, the microcontroller will
reset and terminate all activities
 This is often referred to as a power-on reset
 Activating a power-on reset will cause all values in the registers
to be lost

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EA’

 EA’, “external access’’, is an input pin and must be connected to Vcc or

GND

 The 8051 family members all come with on-chip ROM to store programs and
also have an external code and data memory.

 Normally EA pin is connected to Vcc (Internal Access)

 EA pin must be connected to GND to indicate that the code or data is

stored externally.

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PSEN’ and ALE

 PSEN (Program Status Enable), “program store enable’’, is an output pin

 This pin is connected to the OE pin of the external memory.

 For External Code Memory, PSEN’ = 0

 For External Data Memory, PSEN’ = 1

 ALE pin is used for demultiplexing the address and data.

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I/O Port Pins

 The four 8-bit I/O ports P0, P1, P2

and P3 each uses 8 pins.

 All the ports upon RESET are

configured as output, ready to be
used as input ports by the external
device.
Port 0

 Port 0 is also designated as AD0-AD7.

 When connecting an 8051 to an external memory, port 0

provides both address and data.

 The 8051 multiplexes address and data through port 0 to save

pins.

 ALE indicates if P0 has address or data.

 When ALE=0, it provides data D0-D7
 When ALE=1, it has address A0-A7

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 Port 1 and Port 2

 In 8051-based systems with no external memory

connection:
 Both P1 and P2 are used as simple I/O.
 In 8051-based systems with external memory connections:
 Port 2 must be used along with P0 to provide the 16-bit
address for the external memory.
 P0 provides the lower 8 bits via A0 – A7.
 P2 is used for the upper 8 bits of the 16-bit address,
designated as A8 – A15, and it cannot be used for I/O.

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 Port 3

 Port3 can be used as input or

output.

 Port
3 has the additional function
of providing some extremely
important signals

8051
18 Microcontroll
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 Pin Description Summary
PIN TYPE NAME AND FUNCTION
Vss I Ground: 0 V reference.
Vcc I Power Supply: This is the power supply voltage for normal,
idle, and power-down operation.
P0.0 - P0.7 I/O Port 0: Port 0 is an open-drain, bi-directional I/O port. Port
0 is also the multiplexed low-order address and data bus
during accesses to external program and data memory.
P1.0 - P1.7 I/O Port 1: Port I is an 8-bit bi-directional I/O port.

P2.0 - P2.7 I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the
high order address byte during fetches from external
program memory and during accesses to external data
memory that use 16 bit addresses.
P3.0 - P3.7 I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also
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serves special features as explained. 8051
Microcontroll
er
 Pin Description Summary
PIN TYPE NAME AND FUNCTION
RST I Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device.
ALE O Address Latch Enable: Output pulse for latching the low byte
of the address during an access to external memory.
PSEN* O Program Store Enable: The read strobe to external program
memory. When executing code from the external program
memory, PSEN* is activated twice each machine cycle,
except that two PSEN* activations are skipped during
each access to external data memory.
EA*/VPP I External Access Enable/Programming Supply Voltage: EA*
must be externally held low to enable the device to fetch
code from external program memory locations. If EA* Is
held high, the device executes from internal program
memory. This pin also receives the programming supply
20
voltage Vpp during Flash programming.8051
Microcontroll
(applies for 89c5x
MCU's) er
Block Diagram
8051 Memory Structure
 SPECIAL FUNCTION REGISTERS
(SFRs)
 SFR, which occupies upper 128 bytes of internal memory
are the registers, that control the entire processor
 They can be accessed by DIRECT addressing.
 The registers available in the 8051 are as follows :
 LIST OF REGISTERS
 Accumulators - A and B
 Process Status Word - PSW
 I/O port registers - P0, P1, P2, P3
 Data pointers - DPH and DPL
 Serial data buffer register - SBUF
 Stack pointer - SP
 Timer registers - TH0, TH1 and TL0, TL1
 Timer Control Registers - TCON, TMOD
 Power and Port control - PCON, SCON
 Interrupt Control Registers - IP, IE.
 Special Function Registers [SFR]

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 Program Status Word [PSW]
C AC F0 RS1 RS0 OV F1 P
Carry Parity
Auxiliary Carry User Flag 1

User Flag 0 Register Bank Select Overflow

RS1 RS0 Selected Bank Address Range

0 0 Bank 0 00h to 07h
0 1 Bank 1 08h to 0Fh
1 0 Bank 2 10h to 17h
1 1 Bank 3 18h to 1Fh
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 Power control Register

The 8051 has various power control modes, which are used to control the
power consumed by the microcontroller chip.

Some of these modes let the microcontroller go into a ‘sleep’ mode, which
makes it consume lesser power than during normal operation.

The power control modes are selected through the Special Function Register
PCON.
Bit Pattern for PCON register
Bit Name Explanation of Function

7 SMOD Serial port Baud rate set bit

6 - Reserved

5 - Reserved

4 - Reserved

3 GF1 General Purpose Flag 1

2 GF0 General Purpose Flag 0

1 PD Power Down mode set bit

0 IPL Idle Mode Set bit

 IDLE MODE
 The micro-controller enters the idle mode whenever the
PCON.0 bit is set to 1.
 In the idle mode, the clock pulses applied to the CPU are
masked while all other units like interrupt controller etc.,
will be kept active.
 The contents of the CPU are not affected in this idle mode.
 The processor can be revoked -idle mode -hardware
interrupt or by giving a hardware reset signal.
 These two actions - reset PCON.0 and the processor
execution -resumed to the instruction following the
instruction that set idle mode.
POWER DOWN MODE
 The Power down mode is initiated by making PCON.1 bit to
1.

 In this mode, the clock generator -switched off and only

the internal memory is active.

 the supply voltage Vcc can be reduced to 2V and the power

consumption –reduced.

 Only way to revoke the processor from power down mode -

reset the system.
INTERNAL RAM STRUCTURE
• The 8051 has 128 bytes of internal data RAM, which is accessible as bytes or

sometimes as bits.

• The address of the internal RAM starts at 00H and occupies space up to 7FH.

The RAM space is divided into three blocks—the register banks, the bit-

addressable memory, and the scratch pad memory.

• The 8051 has four register banks of eight registers each, with addresses from

00H to 1FH. In assembly language, they are addressed by the names R0–R7.
INTERNAL RAM STRUCTURE:
1F R7 7F
1E R6
1D R5
1C R4
BANK 3
1B R3
1A R2
19 R1
18 R0
17 R7
16 R6
15 R5
14 R4
BANK2
13 R3
12 R2
11 R1
10 R0
0F R7 2F 7F 78
0E R6 2E 77 70
0D R5 2D 6F 68
0C R4 2C 67 60
BANK1
0B R3 2B 5F 58
0A R2 2A 57 50
09 R1 29 4F 48
08 R0 28 47 40
07 R7 27 3F 38
06 R6 26 37 30
05 R5 25 2F 28
04 R4 24 27 20
BANK 0
03 R3 23 1F 18
02 R2 22 17 10
01 R1 21 0F 08
00 R0 20 07 00 30

register banks bit-addressable memory scratch pad memory.

 Internal RAM Structure
 The register banks are identified with 2 bits in the processor status word.

 The PSW has two bits for identifying the register bank, i.e., 00 represents
bank 0, 01 represents bank 1, 10 represents bank 2, and 11 represents bank
3.

 In the 8051, bitwise operations are also possible with special instructions
using the bit addresses. The bit-addressable memory is both bit-addressable
(from 00H to 7FH) and byte-addressable (from 20H to 2FH). Bit operations
are helpful in many control algorithms.

 Using general-purpose scratch pad memory, programmers can read and

write data at any time for any purpose. This memory ranges from the byte
address 30H to the address 7FH.
Addressing modes
 Immediate Addressing Mode
 The data to be manipulated is directly given in the
instruction itself.
 The data is preceded by a # symbol.
 E.g. ADD A, #80h.
 This instruction adds the data 80h to the contents of the
accumulator and the result is stored in the accumulator
itself.
 This addressing mode will be used when the data for the
arithmetic and logical operation is needed only once and is
a constant.
Register Direct Addressing
 Theregister, that contains the data to be manipulated, is
specified in the instruction.
E.g. ADD A, R0.
 This
instruction will add the contents stored in register R0
with the accumulator contents and store the result in
accumulator.
 Theregisters A, DPTR and R0 to R7 are used in Register
direct addressing.
 Thisaddressing mode uses temporary registers which hold
the data for the operation.
Memory Direct Addressing
 The memory address that contains the data to be operated is specified
here in the instruction.
 E.g. ADD A, 74h.
 This instruction adds the data in accumulator with that stored in
memory address 74h.
 All internal RAM addresses including that of special function registers
can be used in memory direct addressing instructions.
 This addressing mode is used when the data stored in memory is to be
used in arithmetic and logical instructions.
 The data in memory used in the direct addressing can be changed at any
other point in the program.
Memory Indirect Addressing
 The register, which contains the actual memory
address of the data, is specified in the instruction.

 The register specified is preceded by @ symbol in

assembly language format. E.g. ADD A, @R0.

 The value stored in the register R0 is now the

address of the memory location of the data to be
fetched.
Memory Indirect Addressing
 From this memory location, the data is fetched and the
instruction is executed.

 The data pointer register (DPTR) is used to access the data

in the external memory with 16-bit addresses.

 The indirect addressing mode is very much useful for

accessing data which are continuously stored in memory and
accessed consecutively in program.
Indexed Addressing
 In this type of addressing, the instruction consists of two
parts - a base address and an offset.
 This type of addressing is useful in relative memory
accessing and relative jumping.
 The base address is stored in data pointer (DPTR) or any
other register.
 The offset value is stored in Accumulator
 e.g. MOVC A, @A+DPTR.
Indexed Addressing
 This instruction adds the contents of the accumulator with
the contents of the data pointer and the result forms the
actual address of the data from where it is fetched. This
data is moved on to the accumulator.

 The indexed addressing mode is useful in accessing data

structures similar to lookup tables. The base address will
hold the address of the starting point of the table and the
offset will point the particular entry in the table.
Instructions of 8051
Structure of Assembly Language

[ label: ] mnemonic [operands] [ ;comment ]

Example:

MOV R1, #25H ; load data 25H into R1

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8051 Assembly Language
 Registers

MOV Instruction:

MOV destination, source

Example:
1. MOV A, #55H
2. MOV R0, A
3. MOV A, R3 55
Instruction Groups

 The 8051 has 255 instructions

 Every 8-bit opcode from 00 to FF is used except for A5.

 The instructions are grouped into 5 groups

 Arithmetic
 Logic
 Data Transfer
 Boolean
 Branching
 INSTRUCTION SET OF 8051
 Instruction supported by 8051 can be classified into
different types depending upon their operational
functions.

 The instruction set classification is as followed.

Data Transfer Instructions
 As the name indicates, instructions in this set are used to
transfer data.
 The data can be transferred from or to external RAM or
within the internal memory itself.
 The instruction MOV is used to transfer the data between
internal registers/memory.
 The general format is
 MOV Reg destination, Reg source.
 The source and destination registers within the 8051 chip
can be addressed by any one of the addressing modes
except indexed addressing mode discussed earlier.
Data Transfer Instructions
Addressing Modes

Mnemonic Operation
Direct Indirect Register Immediate

MOV A,
A = <src> √ √ √ √
<src>
MOV <dest>,
<dest> = A √ √ √
A
MOV <dest>,
<dest> = <src> √ √ √ √
<src>

MOV DPTR, DPTR = 16-bit

√
# data 16 immediate data

INC SP:
PUSH <src> √
MOV “@SP”, <scr>

MOV <dest>, “@SP”:

POP <dest> √
DEC SP
 Data Transfer Instructions
XCH A, ACC and <byte> Exchange
√ √ √
<byte> Data

XCHD A, ACC and @ Ri exchange

√
@Ri low nibbles

Copy 8 bit data from the

MOVX A, external RAM location
Only Indirect Addressing mode
@Ri pointed to by Ri to register
A

Copy 8-bit data from

MOVX @ Ri,
register A to the external Only Indirect Addressing mode
A
RAM location pointed to
by Ri
Data Transfer Instructions

Copy 8-bit data from the

MOVX A, @
external RAM location Only Indirect Addressing mode
DPTR
pointed to by the 16-bit
DPTR to register A

Copy 8-bit data from

MOVX @
register A to the external Only Indirect Addressing mode
DPTR, A
RAM location pointed to by
the 16-bit DPTR

MOVC A, Read Program Memory at Only Indirect Addressing mode

@A + DPTR (A + DPTR)

MOVC A, Read Program Memory at Only Indirect Addressing mode

@A + PC (A + PC)
 Data Transfer Instructions
 The instructions with the mnemonic MOVX is used to access
data from external memory locations using indirect
addressing only.
 MOVX instruction must use Accumulator (A) register as -
destination or source and the other is indirectly accessed
external memory.
 MOVX can be used -8 bit external memory address and 16
bit external memory address. It can be noted that the
external memory -interfaced with 8051 with either 8 bit
address or 16 bit address.
 Data Transfer Instructions
 If the 8 bit address is used-internal register (any location in
Internal RAM) -hold the address of the memory. If 16 bit
address is used-Data Pointer (DPTR) is used to hold the
address.

 The instructions MOVC A,@A+DPTR and MOVC A,@A+PC are

the two instructions meaning MOVE CODE MEMORY and are
used to transfer data from program memory using indexed
addressing
 Data Transfer Instructions
 The program memory addressing using MOVC instruction
needs 16 bit address. So, the Data Pointer register (DPTR)
and Program Counter (PC) -base registers -instructions.

 Data can only be read from the program memory and not
written into because the program memory is generally ROM.

 PUSH instruction is used to copy data in any internal RAM

location to the stack
 Data Transfer Instructions
 The POP instruction is used to copy data from the top of the
stack to the RAM location specified in the instruction.

 XCHD is used to transfer only the lower-order nibble

between the accumulator and the indirectly addressed
internal RAM.

 XCH is used to exchange the contents of the accumulator

and a register or the internal memory of the 8051.
 Arithmetic Instructions
 These instructions are used to do arithmetic operations.

 The common arithmetic operations like addition,

subtraction, multiplication and division are possible with
8051.

 All the data used in arithmetic instructions must be

available inside the controller i.e. in the internal RAM area
only.
 Arithmetic Instructions
 ADD instruction is used to add any 8 bit data with
Accumulator and the result is stored in Accumulator (A)
register. The carry generated if any is stored in Carry flag of
the processor status word.

 The ADDC instruction is also used to add any 8 bit data with
Accumulator along with Carry bit.
 Arithmetic Instructions
 The SUBB instruction -subtract contents of a register from
the Accumulator content and during this subtraction, the
Carry bit is also subtracted from the accumulator.

 For ADD and SUB instructions, one of the data must be in

Accumulator and the other data - in any direct addressed or
indirect addressed internal memory location or can be an
immediate data.
 Arithmetic Instructions
 In addition to - ADD, ADDC and SUBB instructions, 8051 has
instructions MUL and DIV.

 The register B is exclusively used for these two instructions.

The operands should be stored in the registers A and B for
the MUL and DIV instructions.
 Arithmetic Instructions
 The MUL instruction multiplies the contents of A and B
registers and stores the 16 bit result in the combined A and
B registers.

 The lower order byte -result is stored in A register and the

higher order byte - stored in B register.

 The DIV instruction upon execution will divide the contents

of A register by the contents of B register.
 Arithmetic Instructions
 The quotient of the result - stored in A register and the
remainder is stored in B register.

 A division by 0 i.e. 0 in the B register before executing DIV

AB will result in the overflow flag (OV) set to 1.

 DA A instruction -to convert binary sum obtained after

adding two BCD numbers into BCD number.
Arithmetic Instructions
Addressing Modes
Mnemonic Operation
Direct Indirect Register Immediate
ADD A, A=A+
√ √ √ √
<byte> <byte>
ADDC A=A+
√ √ √ √
A,<byte> <byte>+C
SUBB A, A=A–
√ √ √ √
<byte> <byte>–C
INC A A=A+1 Accumulator Only
DEC A A=A- 1 Accumulator Only
<byte> =
DEC <byte> √ √ √ √
<byte>– 1
MUL AB B:A= B  A Accumulator Only
A = Int
[A/B]
DIV AB Accumulator Only
B = Mod
[A/B]
Decimal
DA A Adjust Accumulator Only
Accumulator
 Logical Instructions
 In addition to logical AND, OR and XRL operation, 8051 has
additional instructions - CLR, CPL. All the data for the
logical instructions -available in the internal RAM only.

 The instruction CLR A -to clear the contents of A register,

CPL is used to complement or logically invert the contents
of the A register and SWAP - to swap the nibbles of A
register.

 8051 supports four rotate operations with the options –

rotating left or right and rotating through carry or not.
Logical Instructions
Addressing Modes
Mnemonic Operation
Direct Indirect Register Immediate
ANL A, A = A AND
√ √ √ √
<byte> <byte>
<byte> =
ANL <byte>,
<byte> AND √
A
A
<byte> =
ANL <byte>,
<byte> AND √
# data
# data
ORL A, A = A OR
√ √ √ √
<byte> <byte>

ORL <byte>, <byte> =

√
A <byte> OR A

<byte> =
ORL <byte>,
<byte> OR # √
# data
data
Logical Instructions
XRL A, A = A XOR
√ √ √ √
<byte> <byte>
<byte> =
XRL <byte>,
<byte> XOR √
A
A
<byte> =
XRL <byte>,
<byte> XOR √
# data
# data
CLR A A = 00H Accumulator only
CLP A A = NOT A Accumulator only
Rotate ACC
RL A Accumulator only
Left 1 bit
Rotate Left
RLC A through Accumulator only
Carry
Rotate ACC
RR A Accumulator only
Right 1 bit
Rotate Right
RRC A through Accumulator only
Carry
 Branching Instructions

 8051 supports unconditional jumping and subroutine calling

in three different ways.

 They are Absolute jump AJMP, ACALL, long jump LJMP,

LCALL, and short jump SJMP.
Un Conditional Branching Instructions
Conditional Branching
Instructions
Addressing Modes
Mnemoni
Operation Immediat
c Direct Indirect Register
e
CJNE Jump if A
A,<byte> ≠= √ √
,rel <byte>
CJNE Jump if
<byte>,# <byte> = √ √
data,rel #data
Jump if A
JZ rel Accumulator only
=0
Jump if A
JNZ rel Accumulator only
≠0
 Branching Instructions
 The syntax for short jump instruction- SJMP 8-bit address.
 This 8 bit address is a relative address- to the program
counter.
 The branching address -by adding the address given in the
instruction with the program counter content.
 The 8-bit address is a 2's complement number i.e., the most
significant bit -sign + or -. The remaining 7 bits - specify the
address. using SJMP -branch to anywhere between 127 bytes
after the program counter content and 128 bytes before
it.(From (PC-128 bytes) to (PC+127 bytes))
 Branching Instructions
 Forexample,
8800: SJMP 06h
 This instruction shift the execution to the location 8808h.
The program counter content after fetching the 2 byte -
SJMP instruction is 8802h. So, 06h added to 8802H results in
8808h.
 The syntax for LJMP -“LJMP 16-bit address”.
 After the execution of this instruction the Program counter -
loaded with the 16 bit address and the execution shifts to
that location.
 The syntax for AJMP instruction is “AJMP 11 bit jump
address”.
 Branching Instructions
 The destination branching address -absolute jumping is
calculated -keeping MSB 5 bits of the Program counter as it
is and changing the LSB 11 bits to that as given -instruction.
 For example,
8800: AJMP 7F0h
 Thisinstruction branch the execution address 8FF0h. After
fetching- program counter content will be 8802h. Keeping
the MSB 5 bits of the PC (10001) as it is, and changing the
LSB 11 bits to that given in the instruction (111 1111 0000) ,
the branching address becomes 8FF0h.
 Branching Instructions
 The micro controller 8051 -single instruction for counter
operation to decrement -result (DJNZ). -very useful in
looping using a counter similar to “for loop” in high level
languages.

 Similarly, jumping after checking the result of a comparison

-done by a single instruction (CJNE) -very useful for looping
of instruction execution based on a condition.

 Used in programming constructs similar to “do while” in

high level languages.
 Bit Manipulation Instructions
 The special feature of the 8051 micro controller is that it
can handle bit data also like that of byte data.

 The internal data memory map of 8051 has a bit-

addressable area also.

 The special function registers that have the address with 0

or 8 as last digit in their hex address, are also bit
addressable.

 The bit manipulation instructions include logical

instructions and conditional branching.
Bit Manipulation Instructions
Mnemonic Operation
ANL C,bit C = C AND bit
ANL C,/bit C = C AND (NOT bit)
ORL C,bit C = C OR bit
ORL C,/bit C = C OR (NOT bit)
MOV C,bit C = bit
MOV bit,C bit = C
CLR C C=0
CLR bit bit = 0
SETB C C=1
SETB bit bit = 1
CPL C C = NOT C
CPL bit bit = NOT bit
JC rel Jump if C = 1
JNC rel Jump if C = 0
JB bit,rel Jump if bit = 1
JNB bit,rel Jump if bit = 0
JBC bit,rel Jump if bit = 1 ; CLR bit
 Bit Manipulation Instructions
 The logical instructions - ANL and ORL. Conditional branching -
JC, JNC, JB, JNB, JBC.

 The other instructions available -CLR, SETB, CPL, and MOV.

 There are no instructions for halting the machine execution.

 Figure 10.6 shows the flag bits affected by the various

instructions.

 Increment and decrement instructions do not affect the flag

register.
 8051 instructions that affects flag

86