CXA1782CQ/CR

RF Signal Processing Servo Amplifier for CD players

Description
CXA1782CQ CXA1782CR
The CXA1782CQ/CR is a bipolar IC with built-in
48 pin QFP (Plastic) 48 pin LQFP (Plastic)
RF signal processing and various servo ICs. A CD
player servo can be configured by using this IC,
DSP and driver.

Features
• Low operating voltage (VCC – VEE = 3.0 to 11.0V)
• Low power consumption (39mW, VCC = 3.0V)
• Supports pickup of either current output, voltage
Absolute Maximum Ratings (Ta = 25°C)
output
• Supply voltage VCC 12 V
• Automatic adjustment comparator for tracking
• Operating temperature Topr –20 to +75 °C
balance gain
• Storage temperature Tstg –65 to +150 °C
• Single power supply and positive/negative dual
• Allowable power dissipation
power supplies
PD 833 (CXA1782CQ) mW
457 (CXA1782CR) mW
Applications
• RF I-V amplifier, RF amplifier
Recommended Operating Condition
• Focus and tracking error amplifier
Operating supply voltage
• APC circuit
VCC – VEE 3.0 to 11.0 V
• Mirror detection circuit
• Defect detection and prevention circuits
• Focus servo control
• Tracking servo control
• Sled servo control
• Comparators of tracking adjustment for balance
and gain

Structure
Bipolar silicon monolithic IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–
E95908C78
 CXA1782CQ/CR

Block Diagram

RF_M

RF_O
PHD2

PHD1

PHD

RF_I

FOK
CC1

CC2
CP
LD

CB
36 35 34 33 32 31 30 29 28 27 26 25

APC
LEVEL S
I IL 24 SENS

TTL 23 C.OUT

RF IV AMP1
MIRR 22 XRST
FOK DFCT

TTL 21 DATA
RF IV AMP2
FE_BIAS 37
•I IL DATA REGISTER •INPUT SHIFT REGISTER
TTL
•ADRESS.DECODER 20 XLT
I IL

FE AMP I IL
F 38 •OUTPUT DECODER 19 CLK
F IV AMP

E 39 TOG1 to 3 FS1 to 4 TG1 to 2 TM1 to 7 PS1 to 4

FZC COMP BAL1 to 3
E IV AMP 18 Vcc
EI 40

TE AMP
•TRACKING
BAL2

HPF COMP LPF COMP

BAL1

BAL3

PHASE COMPENSATION •I SET 17 ISET

TM6
VEE 41
TEO 42 16 SL_O
TG1
TM5
15 SL_M
TOG2
TOG3
TOG1

TM4
TZC COMP
LPFI 43
•FCS PHASE COMPENSATION TM2 14 SL_P
DFCT TM3
TEI 44
TM1 FS1
ATSC 45 •WINDOW COMP. TM7 13 TA_O

ATSC
TZC 46
FS2
TDFCT 47
TG2
•F SET

DFCT
VC 48 FS4

1 2 3 4 5 6 7 8 9 10 11 12
TGU
FE_M

SRCH
FE_O
FDFCT

FSET
FLB
FEI
FEO

TA_M
FGD

TG2

• The switch state in Block Diagram is for initial resetting.

• Switch turns to ° side for 1 and to • side for 0 in Serial Data Truth Table.
• DFCT switch turns to ° side when defect signal generates for DEFECT = E in Serial Data Truth Table.
• TG1 switch turns to ° side and TG2 switch is left open when TG1 and TG2 (address 1 : D3) is 1.

–2–
 CXA1782CQ/CR

Pin Description
Pin
Symbol I/O Equivalent circuit Description
No.

25p
147
1 Focus error amplifier output.
1 FEO O 174k Connected internally to the FZC
51k comparator input.
300µ
10k
9k

2 FEI I 147 Focus error input.

2
100k

147
3 Capacitor connection pin for defect
3 FDFCT I
time constant.

68k
147 Ground this pin through a capacitor
4 FGD I 4 when decreasing the focus servo
130k high-frequency gain.
20µ

40k
External time constant setting pin
5 FLB I 5 for increasing the focus servo low-
frequency.

6 FE_O O Focus drive output.

6
13 TA_O O 13 Tracking drive output.
16

250µ
16 SL_O O Sled drive output.

90k
147
7 FE_M I 7 Focus amplifier inverted input.
50k

–3–
 CXA1782CQ/CR

Pin
Symbol I/O Equivalent circuit Description
No.

147 External time constant setting pin for

8 SRCH I 8
generating focus servo waveform.
11µ
50k

110k
External time constant setting pin for
20k
9 TGU I 9 switching tracking high-frequency
gain.
82k

External time constant setting pin for

10 TG2 I 10 switching tracking high-frequency
470k gain.
2µ

147k High cut-off frequency setting pin for

11 FSET I 11 focus and tracking phase
compensation amplifier.
15k 15k

100k
147
12 TA_M I 12 Tracking amplifier inverted input.

11µ

147
14 SL_P I 14 Sled amplifier non-inverted input.

147
15 SL_M I 15 Sled amplifier inverted input.

22µ

–4–
 CXA1782CQ/CR

Pin
Symbol I/O Equivalent circuit Description
No.

147 Setting pin for Focus search, Track

17 ISET I 17
jump, and Sled kick current.

Serial data transfer clock input from

19 CLK I
15µ
CPU. (no pull-up resistance)
Latch input from CPU.
20 XLT I 19
147 1k (no pull-up resistance)
20
Serial data input from CPU.
21 DATA I 21
(no pull-up resistance)
22
Reset input; resets at Low.
22 XRST I
(no pull-up resistance)

23 C. OUT O Track number count signal output.

20k
147
23
24 Outputs FZC, DFCT, TZC, gain,
24 SENS O 100k
balance, and others according to
the command from CPU.

20k
147
25 FOK O 25 40k Focus OK comparator output.

100k

Input for the DEFECT bottom hold

26 CC2 I
147 147 output with capacitance coupled.
28 27

27 CC1 O DEFECT bottom hold output.

147
26

Connection pin for DEFECT bottom

28 CB I hold capacitor.

–5–
 CXA1782CQ/CR

Pin
Symbol I/O Equivalent circuit Description
No.

147
29 Connection pin for MIRR hold
capacitor.
29 CP I
MIRR comparator non-inverted
input.

Input for the RF summing amplifier

30 RF_I I
output with capacitance coupled.
147
30
RF sunning amplifier output.
31 RF_O O
Eye-pattern check point.

147
31 147 RF summing amplifier inverted
32 input.
32 RF_M I The RF amplifier gain is determined
by the resistance connected
between this pin and RFO pin.

10k
1k
33 LD O 33 APC amplifier output.

17µ

147
34 PHD I 34 APC amplifier input.

10k

35 147 RF I-V amplifier inverted input.

PHD1 I
36
35 Connect these pins to the photo
PHD2 I
36 diode A + C and B + D pins.
100µ 11.6k

–6–
 CXA1782CQ/CR

Pin
Symbol I/O Equivalent circuit Description
No.

32k

164k Bias adjustment of focus error

37 FE_BIAS I 37
amplifier.
25p
8µ

12p

260k
F I-V and E I-V amplifier inverted
38 F I 147 input.
38
39 E I Connect these pins to photo diodes
39 F and E.
513
10µ

6.8k 102k 57k 28k

260k I-V amplifier E gain adjustment.

40 EI — 40 (When not using automatic balance
20.3k
adjustment)

147 12k 23k 11k 4.8k

42 Tracking error amplifier output.
42 TEO O 150k
E-F signal is output.
10k
150k

147 Comparator input for balance

43 LPFI I 43 adjustment.
(Input from TEO through LPF)

–7–
 CXA1782CQ/CR

Pin
Symbol I/O Equivalent circuit Description
No.

44 TEI I Tracking error input.

147 100k
44

147
47 Capacitor connection pin for defect
47 TDFCT I
time constant.

1k 100k
10k Window comparator input for ATSC
45 ATSC I 45
detection.
100k 1k

10k Tracking zero-cross comparator

46 TZC I 46
input.
75k

50 120
48 VC O 48 (VCC + VEE)/2 DC voltage output.
120

VC

–8–
 Electrical Characteristics (VCC = 1.5V, VEE = –1.5V, Ta = 25°C)

SW conditions Ratings
Measure- Measurement conditions
Item SD ment pin Unit
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Min. Typ. Max.

T1 Current consumption 1 RST 18 10 14 20 mA

T2 Current consumption 2 41 –20 –14 –10 mA

T3 Offset 31 –50 0 50 mV

T4 Voltage gain O O 1kHz input ratio 25.1 28.1 31.1 dB

T5 Max. output voltage-High O V1 = 100mVDC 1.2 1.3 — V

RF amplifier
T6 Max. output voltage-Low O V1 = –100mVDC — –0.9 –0.3 V

T7 Offset 1 –120 0 120 mV

T8 Voltage gain 1 O V1 = 1kHz I/O ratio 27.0 30.0 33.0 dB

T9 Voltage gain 1 O V1 = 1kHz I/O ratio 27.0 30.0 33.0 dB

T10 Voltage gain difference –3.0 0 3.0 dB

FE amplifier
T11 Max. output voltage-High O V1 = 100mVDC 1.0 1.3 — V

–9–
T12 Max. output voltage-Low O V1 = 100mVDC — –1.3 –1.0 V

T13 Offset 42 –25 0 25 mV

T14 Voltage gain F0 O 3F V1 = 1kHz TOG1, 2, 3: OFF 0.5 3.5 6.5 dB

V1 = 1kHz TOG1: ON
T15 Voltage gain F1 O 3E –2.33 –1.83 –1.33 dB
Reference to F0

V1 = 1kHz TOG2: ON
T16 Voltage gain F2 O 3D –3.93 –3.43 –2.93 dB
Reference to F0

V1 = 1kHz TOG3: ON
T17 Voltage gain F3 O 3B –6.69 –6.19 –5.69 dB
Reference to F0

TE amplifier
T18 Voltage gain E0 O 37 V1 = 1kHz TOG1, 2, 3: OFF –0.6 2.4 5.4 dB

V1 = 1kHz BAL1: ON
T19 Voltage gain E1 O 36 0.1 0.4 0.7 dB
Reference to E0

T20 V1 = 1kHz BAL2: ON

Voltage gain E2 O 35 0.4 0.7 1.0 dB
Reference to E0
CXA1782CQ/CR
 SW conditions Ratings
Measure- Measurement conditions
Item SD ment pin Unit
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Min. Typ. Max.

V1 = 1kHz BAL3: ON
T21 Voltage gain E3 O 33 42 1.08 1.38 1.68 dB
Reference to E0

T22 Max. output voltage-High O 3F V1 = 1VDC BAL2: ON 0.5 0.6 — V

TE amplifier
T23 Max. output voltage-Low O 3F V1 = 1VDC BAL2: ON — –0.6 –0.5 V

T24 Output voltage 1 O 33 V2 = 120mV –900 –480 mV

T25 Output voltage 2 O V2 = 145mV –900 380 mV

APC
T26 Output voltage 3 O V2 = 170mV –180 1120 mV

T27 Output voltage 4 O O 0.8mA sink –200 500 mV

Center amplifier output

T28 O 48 –100 100 mV
offset

T29 DC voltage gain O 08 6 18 21.0 24 dB

T30 FCS total gain T29 + T8 (or T9) 49 51 53 dB

Output gain difference between

– 10 –
T31 Feed through O 00 –35 dB
SD = 00 and SD = 08.

T32 Max. output voltage-High O O 08 V1 = 200mVDC 1.0 1.3 — V

FCS servo
T33 Max. output voltage-Low O O 08 V1 = –200mVDC — –1.3 –1.0 V

T34 Search voltage (–) 02 –640 –500 –360 mV

T35 Search voltage (+) 03 360 500 640 mV

T36 FZC threshold O 00 24 Pin 1 threshold (preliminary) 185 225 265 mV

T37 DC voltage gain O 25 13 12.25 14.6 17.6 dB

T38 TRK total gain T37 + T14 16.1 18.1 20.1 dB

Output gain difference between

T39 Feed through O –39 dB

TRK servo
SD = 20 and SD = 25.

T40 Max. output voltage-High O O V1 = –0.5VDC 1.0 1.3 V

CXA1782CQ/CR
 SW conditions Ratings
Measure- Measurement conditions
Item SD ment pin Unit
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Min. Typ. Max.

T41 Max. output voltage-Low O O 25 13 V1 = +0.5VDC –1.3 –1.0 V

T42 Jump output voltage (–) 2C –640 –500 –360 mV

T43 Jump output voltage (+) 28 360 500 640 mV

T44 ATSC threshold (–) O 25 10 –25 –15 –7 mV

T45 ATSC threshold (+) O 25 7 15 25 mV

TRK Servo
T46 TZC threshold O 25 24 –20 0 20 mV

T47 BAL COMP threshold O 30 12 17 22 mV

T48 GAIN COMP threshold O 38 120 130 140 mV

T49 FOK threshold O 25 –400 –356 –330 mV

T50 DC open gain O 25 16 50 dB

Output gain difference between

T51 Feed through O 20 –34 dB
SD = 20 and SD = 25.

– 11 –
T52 Max. output voltage-High O 25 V1 = +0.4VDC 1.0 1.3 V

Sled
T53 Max. output voltage-Low O V1 = –0.4VDC –1.3 –1.0 V

T54 Kick voltage (–) 23 –750 –600 –450 mV

T55 Kick voltage (+) 22 450 600 750 mV

T56 Max. operating frequency O O 14 23 Measures at C. OUT pin. 30 kHz

T57 Min. input operating voltage O O Measures at C. OUT pin. 0.3 Vp-p

MIRR
T58 Max. input operating voltage O O Measures at C. OUT pin. 1.8 Vp-p

T59 Min. operating frequency O O 10 24 Measures at SENS pin. 1 kHz

T60 Max. operating frequency O O Measures at SENS pin. 2.5 kHz

T61 Min. input operating voltage O O Measures at SENS pin. 0.5 Vp-p

DEFECT
T62 Max. input operating voltage O O Measures at SENS pin. 1.8 Vp-p
CXA1782CQ/CR
 CXA1782CQ/CR

Electrical Characteristics Measurement Circuit

VEE Vcc

V2

10k
S17

S16

3000p
S2

1000p
S1
3300p

10k
S15
22k

10k
10k

36 35 34 33 32 31 30 29 28 27 26 25

FOK
CC2
RF_I

CP
PD

CB
RF_M
PD2

RF_O
PD1

CC1
LD
37 24 Vcc
10k FE_BIAS SENS 10k
S3
38 F C. OUT 23 Vcc
390k 10k
S4
39 E XRST 22 XRST
390k
40 EI DATA 21 DATA

VEE A 41 VEE XLT 20 XLT

S18
42 TEO CLK 19 CLK
S5
43 LPFI Vcc 18 A Vcc
V1 S6
44 TEI ISET 17
240k VEE
S7
AC 45 ATSC SL_O 16

60k
DC 13k
S8
46 TZC SL_M 15
5.1k
S14
47 TDFCT SL_P 14
0.1µ 10k
FDFCT

TA_O
SRCH

V S9
FE_M

TA_M
FE_O

48 VC
FSET

13
TGU
FEO

FGD

TG2
FLB
FEI

200k

100k
1 2 3 4 5 6 7 8 9 10 11 12
S12
S13
0.1µ

47k
10k

100k
S10

S11
0.015µ
510k

200k
10k

– 12 –
 CXA1782CQ/CR

Application Circuit (Dual ±5V power supplies)

Vcc
1µ/6.3V

100µ/6.3V
Vcc
10
1k 1µ/0.3V

COMPUTER
10µH

MICRO
A
C
VEE 100
500
22k 0.01µ 0.033µ

0.033µ
B

0.01µ
D
36 35 34 33 32 31 30 29 28 27 26 25
Vcc

CP

FOK
PD1

CC2
LD
PD2

RF I

CB

CC1
PD

RF M

RF O
47k 37 24 DSP
SENS
VEE FE_BIAS
F
38 F C. OUT 23 DSP
E MICRO
39 E XRST 22
COMPUTER
40 EI DATA 21 DSP

41 VEE XLT 20 DSP

VEE
42 TEO CLK 19 DSP
100k 150k Vcc
43 LPFI Vcc 18
0.01µ
0.01µ

120k
44 TEI ISET 17
VEE
BPF 45 ATSC SL O 16 Driver
0.022µ

8.2k 100k

0.015µ
46 TZC SL M 15

47 TDFCT SL P 14
0.1µ 3.3µ
FDFCT

TA O
SRCH

FSET
48 VC

TA M
FE M

13
FE O
FGD

TGU
FEO

TG2
FLB
FEI

10µ
22µ 15k
1 2 3 4 5 6 7 8 9 10 11 12

82k
680k
2200p 0.1µ

0.1µ

4.7µ

22k
100k
Driver
510k

100k 0.033µ
0.015µ
0.1µ

Driver

Vcc

Application Circuit (Single +3V power supply)

Vcc
1µ/6.3V
100µ/6.3V

Vcc
10
1k 1µ/0.3V
COMPUTER

10µH
MICRO

A
C
100
500
0.033µ

22k 0.01µ 0.033µ

0.01µ

B
D
36 35 34 33 32 31 30 29 28 27 26 25
Vcc
CP

FOK
PD1

CC2
LD
PD2

RF I

CB

CC1
PD

RF M

RF O

47k 37 24 DSP
FE_BIAS SENS
F
38 F C. OUT 23 DSP
E MICRO
39 E XRST 22
COMPUTER

40 EI DATA 21 DSP

41 VEE XLT 20 DSP

42 TEO CLK 19 DSP

100k 150k Vcc
43 LPFI Vcc 18
0.01µ

0.01µ

120k
44 TEI ISET 17

BPF 45 ATSC SL O 16 Driver

0.022µ

8.2k 100k

0.015µ

46 TZC SL M 15

47 TDFCT SL P 14
0.1µ 3.3µ
FDFCT

TA O
SRCH

FSET

48 VC
TA M
FE M

13
FE O
FGD

TGU
FEO

TG2
FLB
FEI

10µ 10µ
22µ 15k
1 2 3 4 5 6 7 8 9 10 11 12
82k
2200p 0.1µ

0.1µ 680k

0.1µ

Vcc
4.7µ

22k
100k
Driver
510k

100k 0.033µ
0.015µ
Driver

Vcc

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 13 –
 CXA1782CQ/CR

Description of Functions

RF Amplifier
The photo diode currents input to the input pins (PD1 and PD2) are each I-V converted via a 58kΩ equivalent
resistor by the PD I-V amplifiers. these signals are added by the RF summing amplifier, and the photo diode
(A + B + C + D) current-voltage converted voltage is output to the RFO pin. An eye-pattern check can be
performed at this pin.

1k
3.3µ 22k

RF_M RF_O
A 32 31
58k

PD1
C 10k
35 VA
iPD1→

B PD1 IV AMP
VC RF SUMMING AMP
58k
VC
PD2
D 10k
36 VB
iPD2→

PD2 IV AMP
VC

The low frequency component of the RFO output voltage is VRFO = 2.2 × (VA + VB) = 127.6kΩ × (iPD1 + iPD2).

Focus Error Amplifier

The focus error amplifier calculates the difference between output VA and VB of the RF I-V amplifier, and
output current-voltage converted voltage of the photo diode (A + C – B – D).

25p

174k

VB 32k
– (B + D)
1 FEO
– (A + C)
VA FE AMP
32k
25p 87k
164k

VC FE_BIAS
37

VEE VCC
47k

The FEO output voltage (low frequency) is VFEO = 5.4 × (VA – VB) = (iPD2 – iPD1) × 315kΩ.

Be aware that the rotation of the focus bias volume has reversed for the usual CD RF IC.

– 14 –
 CXA1782CQ/CR

Tracking Error Amplifier

The photo diode currents input to E and F pins are each current-voltage converted by the E I-V and F I-V
amplifiers.

1k RF1
3.3µ
260k
12p
TE AMP
F
30k 96k
→ 38 VF
iF
RF2
13k

12k
30k
F I-V AMP

96k
VC
42
RF3
26k

TOG3 4.8k
TOG1 22k

TOG2 10k
10k
TEO
RE1 VC VC

260k
12p
E
6.8k

RE2

→ 39 VE VC
iE
20.3k

BAL1 102k

28k
57k

E I-V AMP
VC
RE3
BAL3
BAL2

VC
40
EI

The CXA1782 tracking block has built-in circuits for balance and gain adjustments to enable software-based
automatic adjustment.
The balance adjustment is performed by varying the combined resistance value of the T-configured feedback
resistance at E I-V AMP.

F I-V AMP feedback resistance = RF1 + RF2 + RF1 x RF2 = 403kΩ

RF3
RE1 x RE2
E I-V AMP feedback resistance = RE1 + RE2 +
RE3

Vary the value of RE3 in the formula above by using the balance adjustment switches (BAL1 to BAL3).
For the gain adjustment, the TE AMP output is resistance-divided by the gain adjustment switches (TOG1 to
TOG3), and it is output at Pin 42.
These balance and gain adjustment switches are controlled through software commands.

– 15 –
 CXA1782CQ/CR

Tracking Automatic Adjustment for Gain/Balance

µ-CON

TZC DFCT FZC

BUFFER SENS Balance OK

AMP 24
100k 150k Gain OK
42 43 LPF
0.01µ
0.01µ

TEO LPFI
HPF C. OUT
Frequency
23 check
LPF –

Balance Gain

Resistance
switching

The CXA1782 has balance control, gain control, and comparator circuits required to perform tracking
automatic adjustment. LPF is set externally at approximately 100Hz.

• Balance adjustment
This adjustment is performed by routing the tracking error signal (TE signal) through the LPF, extracting the
offset DC, and comparing it to the reference level.
However, the TE signal frequency distribution ranges form DC to 2kHz. Merely sending the signal through
the LPF leaves lower frequency components, and the complete DC offset can not be extracted. To extract it,
monitor the TE signal frequency at all times, and perform adjustment only when, a frequency that can lower a
sufficient gain appears on the LPF. Use the C. OUT output to check this frequency.

• Gain adjustment
This adjustment is performed by passing the TE signal through the HPF and comparing the AC component to
the reference level. The HPF signal is implemented by taking the difference between the TE signal and the
LPF component input to Pin 43.
The comparison signal is output from Pin 24 (SENS). Address 3 selects the automatic adjustment
comparator output, and HPF for data (D3) = 1 or LPF for data (D3) = 0 is selected.

• The anti-shock circuit always operates in the CXA1782 so that TG1 and TG2 (address 1 : D3) should be set
to 1 for tracking adjustment to prevent this effect.
When the anti-shock function is not used, Pin 45 (ATSC) should be fixed to VC.

– 16 –
 CXA1782CQ/CR

Center Voltage Generation Circuit

(Single voltage application; Connect to GND when it’s positive/negative dual power supplies.)
Maximum current is approximately ±3mA. Output impedance is approximately 50Ω.

Vcc
30k

VC

50 VC
48
30k

VEE

APC Circuit
When the laser diode is driven with constant current, the optical output possesses large negative temperature
characteristics. Therefore, the current must be controlled with the monitor photo diode to ensure the output
remains constant.
Vcc
100µ/6.3V

LD
33
1k Vcc

10µH 56k
PD
34
10k

55k 56k
1µ/6.3V

10k 10k
VREF
1.25V

VEE VEE
LD

PD

VEE
GND

– 17 –
 CXA1782CQ/CR

Focus Servo

FE
9k

51k

FEO FZC
1
10k
22k 2
FEI
DFCT
2200p 100k FS4 68k
FE_O FOCUS COIL
Focus 100k
3 phase 6
FDFCT
0.47µ Compensation

FGD
4 50k FE_M 100k
7
680k
40k 11µ 22µ
0.1µ
ISET 120k
17
50k
FS2 FS1
FLB FSET SRCH
5 11 8

0.1µ 510k 0.01µ 4.7µ

The above figure shows a block diagram of the focus servo.

Ordinarily the FE signal is input to the focus phase compensation circuit through a 68kΩ resistance; however,
when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal
100kΩ resistance and the capacitance connected to Pin 3. When this DFCT prevention circuit is not used,
leave Pin 3 open. The defect switch operation can be enabled and disabled with command.

The capacitor connected between Pin 5 and GND is a time constant to raise the low frequency in the normal
playback state.
The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510Ω is
connected to Pin 11.
The focus search height is approximately ±1.1Vp-p when using the constants indicated in the above figure.
This height is inversely proportional to the resistance connected between Pin 17 and VEE. However, changing
this resistance also changes the height of the track jump and sled kick as well.
The FZC comparator inverted input is set to 15% of VCC and VC (Pin 48); (VCC – VC) × 15%.
∗ 510kΩ resistance is recommended for Pin 11.

– 18 –
 CXA1782CQ/CR

Tracking Sled Servo

TE
+
42
TEO
– HPF
130mV

BUFFER AMP
100k 150k
43
LPFI LPF
0.01µ

0.01µ

17mV

SLED MOTOR
SL_O
16 M
TEI DFCT

0.015µ
120k
44 TM1 680k TG1

100k SL_M
680k 15
TDFCT 100k 66p TM6
22µA
47
8.2k
TM2 SL_P
0.47µ

TM5
22µA 14
0.047µ 470k 1k
ATSC
45 3.3µ
ATSC
330k

47p

1k

82k 22µ
100k TM4 11µA
0.022µ TZC TA_M 100k
15k
46 12
TM3
TZC 11µA

20k TRACKING
TGU Tracking Phase 10k 90k COIL
9 TA_O
Compensation 13
0.033µ TG2
TG2
10 TM7
470k
FSET
11

510k

0.01µ

The above figure shows a block diagram of the tracking and sled servo.
The capacitor connected between Pins 9 and 10 is a time constant to decrease the high-frequency gain when
TG2 is OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510kΩ
resistance connected to Pin 11. In the CXA1782, TG1 and TG2 are inter-linked switches.
To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to
the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 12. To be
more specific,
Track jump peak voltage = TM3 (or TM4) current × feedback resistance value
The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage
applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 15;
Sled kick peak voltage = TM5 ( or TM6) current × feedback resistance
The values of the current for each switch are determined by the resistance connected between Pin 17 and
VEE. When this resistance is 120kΩ:
TM3 ( or TM4) = ±11µA, and TM5 (or TM6) = ±22µA.
As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the
internal resistance (100kΩ) and the capacitance connected to Pin 47.

– 19 –
 CXA1782CQ/CR

Focus OK Circuit
RF VCC

RF_O 20k
31 54k
C5 ×1
0.01µ 25 FOK
30 VG
RF_I
15k 92k

0.625V

FOCUS OK AMP FOCUS OK

COMPARATOR

The focus OK circuit creates the timing window okaying the focus servo from the focus search state.
The HPF output is obtained at Pin 30 from Pin 31 (RF signal), and the LPF output (opposite phase) of the
focus OK amplifier output is also obtained.
The focus OK output reverses when VRFI – VRFO ≈ –0.37V.
Note that, C5 determines the time constant of the HPF for the EFM comparator and mirror circuit and the LPF
of the focus OK amplifier. Ordinarily, with a C5 equal to 0.01µF selected, the fc is equal to 1kHz, and block
error rate degradation brought about by RF envelope defects caused by scratched discs can be prevented.

DEFECT Circuit
After the RFI signal is reverted, two time constants, long and short, are held at bottom. The short time constant
bottom hold responds to 0.1ms or greater disc mirror defects, and the long time constant bottom hold holds the
pre-defect mirror level. By differentiating and level-shifting these constants with capacitor coupling and
comparing both signals, the mirror defect detection signal is generated.

0.033µ
CC1 CC2
27 26

a
RF_O 31 b c
×2 e
24 SENS
DEFECT AMP d
DEFECT SW

DEFECT BOTTOM DEFECT COMPARATOR

28 HOLD
CB
0.01µ

a RFO

b DEFECT
AMP

BOTTOM
c HOLD (1) ; d BOTTOM
solid Line: HOLD (2) ;
CC1 dotted Line:
CC2
H
e DEFECT
L

– 20 –
 CXA1782CQ/CR

Mirror Circuit
The mirror circuit performs peak and bottom hold after the RFI signal has been amplified.
The peak and bottom holds are both held through the use of a time constant. For the peak hold, a time
constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope
fluctuation.

RF_O
31 RF MIRROR HOLD AMP
0.033µ
29
H CP
30 PEAK&
RF_I × 1.4 BOTTOM ×1
G HOLD I J
K
MIRROR AMP

20k LOGIC
MIRROR
COMPARATOR

RF_O

0V

G
(RF_I) 0V

H
(PEAK HOLD)
0V

I
(BOTTOM HOLD) 0V

J
K
(MIRROR HOLD)

MIRR H

The DC playback envelope signal J is obtained by amplifying the difference between the peak and bottom hold
signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by
comparing it to the peak hold signal K. Accordingly, when on the disc track, the mirror output is Low; when
between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time
constant must be sufficiently large compared with the traverse signal.
In the CXA1782, this mirror output is used only during braking operations, and no external output pin is
attached. Accordingly, when connecting DSP such as the CXD2500 with MIRR input pin, input the C. OUT
output to the MIRR input of the DSP.

– 21 –
 CXA1782CQ/CR

Commands
The input data to operate this IC is configured as 8-bit data; however, below, this input data is represented by
2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0 and F.
Commands for the CXA1782 can be broadly divided into four groups ranging in value from $0X to $3X.

1. $0X (“FZC” at SENS pin (Pin 24))

These commands are related to focus servo control.

The bit configuration is as shown below.

D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 FS4 DEFECT FS2 FS1

Four focus-servo related switches exist: FS1, FS2, FS4, and DEFECT corresponding to D0 to D3, respectively.

$00 When FS1 = 0, Pin 8 is charged to (22µA – 11µA) × 50kΩ = 0.55V.

If, in addition, FS2 = 0, this voltage is no longer transferred, and the output at Pin 6 becomes 0V.
$02 From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output
to Pin 6. This voltage level is obtained by equation 1 below.

(22µA – 11µA) × 50kΩ × resistance between Pins 6 and 7 .... Equation 1

50kΩ

$03 From the state described above, FS1 becomes 1, and a current source of +22µA is split off.
Then, a CR charge/discharge circuit is formed, and the voltage at Pin 8 decreases with the time as
shown in Fig. 1 below.

0V

Fig. 1. Voltage at Pin 8 when FS1 gose from 0 → 1

This time constant is obtained with the 50kΩ resistance and an external capacitor.

By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)

0V

$ 00 02 03 02 03 02 00

Fig. 2. Constructing the search voltage by alternating between $02 and $03. (Voltage at Pin 6)

$04 When the fact that the RF signal is missing is detected and the scratches on the disc are detected with
DEFECT = 0, DFCT (FS3) is turned ON.

– 22 –
 CXA1782CQ/CR

1-1. FS4
This switch is provided between the focus error input (Pin 2) and the focus phase compensation, and is in
charge of turning the focus servo ON and OFF.

$00 → $08
Focus OFF ← Focus ON

1-2. Procedure of focus activation

For description, suppose that the polarity is as described below.
a) The lens is searching the disc from far to near;
b) The output voltage (Pin 6) is changing from negative to positive; and
c) The focus S-curve is varying as shown below.

Fig. 3. S-curve

The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and the
turning the focus servo switch ON are performed during the focus S-curve transits the point A indicated in Fig. 3.
To prevent misoperation, this signal is ANDed with the focus OK signal.
In this IC, FZC (Focus Zero Cross) signal is output from the SENS pin (Pin 24) as the point A transit signal. In
addition, focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case).
Following the line of the above description, focusing can be well obtained by observing the following timing
chart.
(20ms) (200ms)
$02
($00) $03 $08

Drive voltage

∗ The broken lines in the figure

indicate the voltage assuming
Focus error
the signal is not in focus.

SENS pin
(FZC)

The instant the signal is brought into focus.

Focus OK

Fig. 4. Focus ON timing chart

– 23 –
 CXA1782CQ/CR

Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be
minimized. To do this, the software sequence shown in B is better than the sequence shown in A.

FZC ↓ ? Transfer $08

NO
YES

F. OK ? F. OK ?
NO NO
YES YES

Transfer $08 FZC ↓ ?

NO
YES

Latch Latch

(A) (B)

Fig. 5. Poor and good software command sequences

1-3. SENS pin (Pin 24)

The output of the SENS pin differs depending on the input data as shown below.
$0X: FZC
$1X: DEFECT
$2X: TZC
$3X: Automatic adjustment comparator output
$4X to 7X: HIGH-Z

2. $1X (“DEFECT” at SENS pin (Pin 24))

These commands deal with switching TG1/TG2, brake circuit ON/OFF, and the sled kick output.
The bit configuration is as follows Sled kick height
D7 D6 D5 D4 D3 D2 D1 D0 Relative
D1 D0 value
(PS1) (PS0)
0 0 0 1 TG1, TG2 Break Sled kick
0 0 ±1
circuit height ±2
0 1
ON/OFF ON/OFF
1 0 ±3
1 1 ±4
TG1, TG2
The purpose of these switches is to switch the tracking servo gain Up/Normal. TG1 and TG2 are interlinked
switches. The brake circuit (TM7) is to prevent the occurrence of such frequently occurring phenomena as
extremely degraded actuator settling due to the servo motor exceeding the linear range causing what should
be a 100-track jump to fall back down to a 10-track jump after a 100 or 10-track jump has been performed. To
do this, when the actuator travels radially; that is, when it traverses from the inner track to the outer track of
the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the RF envelope
and the tracking error is 180˚out-of-phase to cut the unneeded portion of the tracking error and apply braking.

– 24 –
 CXA1782CQ/CR

[∗A] [∗B] D2
(MIRR)
Waveform Shaping
[∗G]
RF_I 30
[∗C]
Envelope Detection
TM7
D Q Low: open
BRK
[∗D] [∗E]
Tracking error
[∗F]
High: make
CK
(TZC) 46 Waveform Shaping Edge Detection
(Latch)

CXA1782

Fig. 6. TMI movement during braking operation

From inner to outer track From outer to inner track

[∗A]

[∗B]

[∗C] (“MIRR”)

[∗D]
(“TZC”)
[∗E]

[∗F]

[∗G]
Braking is
applied from
[∗H] 0V here.

Fig. 7. Internal waveform

3. $2X (“TZC” at SENS pin (Pin 24))

These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse
and fast forward pulse during access operations.
D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 0 Tracking Sled
control control
00: OFF 00: OFF
01: Servo ON 01: Servo ON
10: F-JUMP 10: F-FAST FORWARD
11: R-JUMP 11: R-FAST FORWARD
↓ ↓
TM1, TM3, TM4 TM2, TM5, TM6

– 25 –
 CXA1782CQ/CR

4. $3X

These commands control the balance and gain control circuit switches used during automatic tracking
adjustment.
In the initial resetting state, BAL1 to BAL3 switches are OFF and TOG1 to TOG3 switches are ON.

• Balance adjustment
The balance adjustment switches BAL1 to BAL3 can be controlled by setting D3 = 0. The switches are set
using D0 to D2.
At this time, the balance adjustment LPF comparator output is selected at the SENS pin.
Data is set by specifying switch conditions D0 to D2 and sending a latch pulse with D3 = 0.
Sending a latch pulse with D3 = 1 does not change the balance switch settings.

START

C. OUT
Is the frequency
BAL1 to BAL3 high enough ?
Switch Control NO
YES

SENS output
Balance OK ?

Adjustment Completed

Balance adjustment

• Gain adjustment
The gain adjustment switches TOG1 to TOG3 can be controlled by setting D3 = 1. These switches are set
using D0 to D2. At this time, the balance adjustment HPF comparator output is selected for SENS pin.
In a fashion similar to the method used with the balance adjustment, set the data by sending a latch pulse
with D3 = 1, specifying the switch conditions D0 to D2.

START

TOG1 to TOG3
Switch control

SENS
GAIN OK ?
NO
YES

Adjustment Completed

Gain adjustment

– 26 –
 CXA1782CQ/CR

CPU Serial Interface Timing Chart

DATA D0 D1 D2 D3 D4 D5 D6 D7 D0
tWCK tWCK tSU th

CLK
1/fck tCD

tD
XLT
tWL

(VCC = 3.0V)
Item Symbol Min. Type. Max. Unit
Clock frequency fck 1 MHz
Clock pulse width fwck 500 ns
Setup time tsu 500 ns
Hold time th 500 ns
Delay time tD 500 ns
Latch pulse width tWL 1000 ns
Data transfer interval tCD 1000 ns

System Control
ADRESS DATA SENS
Item
D7 D6 D5 D4 D3 D2 D1 D0 output

FS4 DEFECT (FS3) FS2 FS1

Focus Control 0 0 0 0 Focus Disable = 1 Search Search FZC
ON = 1, OFF = 0 Enable = 0 ON = 1, OFF = 0 Up = 1, Down = 0

Tracking Control 0 TG1, TG2 Brake Sled Sled DEFECT

0 0 1
ON = 1, OFF = 0 ON = 1, OFF = 0 Kick + 2 Kick + 1
Tracking Mode 0 0 1 0 Tracking Mode ∗1 Sled Mode ∗2 TZC

Select 0 0 1 1 Automatic tracking adjustment mode Gain/Bal

∗1 TRACKING MODE ∗2 SLED MODE

D3 D2 D1 D0
OFF 0 0 OFF 0 0
ON 0 1 ON 0 1
FWD JUMP 1 0 FWD MOVE 1 0
REV JUMP 1 1 REV MOVE 1 1

– 27 –
 CXA1782CQ/CR

Serial Data Truth Table

Serial Data Hex Functions

FS = 4321
FOCUS CONTROL
FS4 DEFECT FS2 FS1 DEFECT
0 0 0 0 0 0 0 0 $00 0 E 0 0 E: enable
0 0 0 0 0 0 0 1 $01 0 E 0 1 D: disable
0 0 0 0 0 0 1 0 $02 0 E 1 0
0 0 0 0 0 0 1 1 $03 0 E 1 1
0 0 0 0 0 1 0 0 $04 0 D 0 0
0 0 0 0 0 1 0 1 $05 0 D 0 1
0 0 0 0 0 1 1 0 $06 0 D 1 0
0 0 0 0 0 1 1 1 $07 0 D 1 1
0 0 0 0 1 0 0 0 $08 1 E 0 0
0 0 0 0 1 0 0 1 $09 1 E 0 1
0 0 0 0 1 0 1 0 $0A 1 E 1 0
0 0 0 0 1 0 1 1 $0B 1 E 1 1
0 0 0 0 1 1 0 0 $0C 1 D 0 0
0 0 0 0 1 1 0 1 $0D 1 D 0 1
0 0 0 0 1 1 1 0 $0E 1 D 1 0
0 0 0 0 1 1 1 1 $0F 1 D 1 1

TRACKING MODE Hex TM = 6 5 4 3 2 1

0 0 1 0 0 0 0 0 $20 0 0 0 0 0 0
0 0 1 0 0 0 0 1 $21 0 0 0 0 1 0
0 0 1 0 0 0 1 0 $22 0 1 0 0 0 0
0 0 1 0 0 0 1 1 $23 1 0 0 0 0 0
0 0 1 0 0 1 0 0 $24 0 0 0 0 0 1
0 0 1 0 0 1 0 1 $25 0 0 0 0 1 1
0 0 1 0 0 1 1 0 $26 0 1 0 0 0 1
0 0 1 0 0 1 1 1 $27 1 0 0 0 0 1
0 0 1 0 1 0 0 0 $28 0 0 0 1 0 0
0 0 1 0 1 0 0 1 $29 0 0 0 1 1 0
0 0 1 0 1 0 1 0 $2A 0 1 0 1 0 0
0 0 1 0 1 0 1 1 $2B 1 0 0 1 0 0
0 0 1 0 1 1 0 0 $2C 0 0 1 0 0 0
0 0 1 0 1 1 0 1 $2D 0 0 1 0 1 0
0 0 1 0 1 1 1 0 $2E 0 1 1 0 0 0
0 0 1 0 1 1 1 1 $2F 1 0 1 0 0 0

– 28 –
 CXA1782CQ/CR

Automatic TOG SW BAL SW

adjustment mode Hex 3 2 1 3 2 1
0 0 1 1 0 0 0 0 $30 – – – 1 1 1 DATA D3 = 0: Balance switch setting
0 0 1 1 0 0 0 1 $31 – – – 1 1 0 DATA D3 = 1: Gain switch setting
0 0 1 1 0 0 1 0 $32 – – – 1 0 1
0 0 1 1 0 0 1 1 $33 – – – 1 0 0
0 0 1 1 0 1 0 0 $34 – – – 0 1 1
0 0 1 1 0 1 0 1 $35 – – – 0 1 0
0 0 1 1 0 1 1 0 $36 – – – 0 0 1
0 0 1 1 0 1 1 1 $37 – – – 0 0 0
0 0 1 1 1 0 0 0 $38 1 1 1 – – –
0 0 1 1 1 0 0 1 $39 1 1 0 – – –
0 0 1 1 1 0 1 0 $3A 1 0 1 – – –
0 0 1 1 1 0 1 1 $3B 1 0 0 – – –
0 0 1 1 1 1 0 0 $3C 0 1 1 – – –
0 0 1 1 1 1 0 1 $3D 0 1 0 – – –
0 0 1 1 1 1 1 0 $3E 0 0 1 – – –
0 0 1 1 1 1 1 1 $3F 0 0 0 – – –

Note) 0 means OFF and 1 means ON for TOG SW and BAL SW. These are not equal to the setting values of
each bit for serial data.

Initial State (resetting state)

ADDRESS DATA
Item HEXADECIMAL
D7 D6 D5 D4 D3 D2 D1 D0
Focus Control 0 0 0 0 0 0 0 0 $00
Tracking Control 0 0 0 1 0 0 0 0 $10
Tracking Mode 0 0 1 0 0 0 0 0 $20
0 1 1 1 $37
Select 0 0 1 1
1 0 0 0 $38

The above data means the following operation modes.

Focus Control Focus off, Defect enable, Focus Search off, Focus Search down
Tracking Control TG1 – TG2 off, Brake off, Sled Kick + 2 off, Sled Kick + 1 off
Tracking Mode Tracking off, Sled off
Select Tracking gain → min. (TOG SW: 1 1 1)
Tracking balance: RE3 → max. (TBAL SW: 0 0 0)

– 29 –
 CXA1782CQ/CR

Notes on Operation

1. FSET pin
The FSET pin determines the fc for the focus and tracking high-frequency phase compensation.

2. ISET pin
ISET current = 1.27V/R
= Focus search current
= Tracking jump current
1
= Sled kick current ($1X: PS1 = PS0 = 0) ×
2
Use the setting resistance within the range of 120kΩ to 240kΩ. If the resistance value is out of this range,
the oscillation may be occurred in the ISET block.

3. FE (focus error)/TE (tracking error) gain changing method

1) High gain: Resistance between FE pins (pins 6 and 7) 100kΩ → Large
Resistance between TE pins (pins 12 and 13) 100kΩ → Large
2) Low gain: A signal, whose resistance is divided between Pins 1 and 2, is input to FE. The internal gain
adjustment circuit is used for TE.

4. Input voltage at Pins 19 to 22 of the microcomputer interface should be as follows:

VIH VCC × 90% or more
VIL VCC × 10% or less

5. Focus OK circuit
1) Refer to the “Description of Operation” for the time constant setting of the focus OK amplifier LPF and the
mirror amplifier HPF.
VCC

20k
FOK
25
40k
The FOK and comparator output are as follows:
RL
Output voltage High: VFOKH ≈ near VCC
100k
Output voltage Low: VFOKL ≈ Vsat (NPN)
VCC
VEE VEE
6. Sled amplifier
The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately 20dB.

Sled/Tracking internal phase compensation and reference design material

Item SD Measurement pin Conditions Typ. Unit

1.2kHz gain 08 CFLB = 0.1µF 21.5 dB
FCS

6
1.2kHz phase 08 CFGD = 0.1µF 63 deg
1.2kHz gain 25 13 dB
1.2kHz phase 25 –125 deg
TRK

13 CTGU = 0.1µF
2.7kHz gain 25→13 26.5 dB
2.7kHz phase 25→13 –130 deg

– 30 –
 CXA1782CQ/CR

Package Outline Unit: mm

CXA1782CQ

48PIN QFP (PLASTIC)

15.3 ± 0.4

+ 0.4 + 0.1
12.0 – 0.1 0.15 – 0.05

36 25
0.15

37 24

13.5
48 13 + 0.2
0.1 – 0.1

1 12

0.9 ± 0.2
+ 0.15
0.8 0.3 – 0.1
± 0.12 M
+ 0.35
2.2 – 0.15

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE LEAD TREATMENT SOLDER / PALLADIUM

QFP-48P-L04 PLATING
EIAJ CODE ∗QFP048-P-1212-B LEAD MATERIAL COPPER / 42 ALLOY

JEDEC CODE PACKAGE WEIGHT 0.7g

NOTE : PALLADIUM PLATING

This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).

CXA1782CR

48PIN LQFP (PLASTIC)

9.0 ± 0.2

∗ 7.0 ± 0.1

36 25

37 24
(8.0)

0.5 ± 0.2

48 13
(0.22)

1 12
+ 0.05
0.5 ± 0.08 0.127 – 0.02
+ 0.08 + 0.2
0.18 – 0.03 1.5 – 0.1
0.1

0.1 ± 0.1
0.5 ± 0.2

0° to 10°

NOTE: Dimension “∗” does not include mold protrusion.

DETAIL A

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY / PHENOL RESIN

SONY CODE LQFP-48P-L01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE ∗QFP048-P-0707-A LEAD MATERIAL 42 ALLOY

JEDEC CODE PACKAGE WEIGHT 0.2g

NOTE : PALLADIUM PLATING

This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).

– 31 –