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CXD3059AR
CD Digital Signal Processor with Built-in RF Amplifier and Digital Servo + Digital High & Bass Boost

Description
The CXD3059AR is a digital signal processor LSI for CD 120 pin LQFP (Plastic)
players. This LSI incorporates a RF amplifier and digital servo,
high & bass boost, 1-bit DAC and analog low-pass filter.

Features
• All digital signal processing during playback is performed with
a single chip
• Highly integrated mounting possible due to a built-in RF
amplifier

RF Block
• Supports 4× speed playback CD
• RF system equalizer
• Supports pickup built-in RF summing amplifier
• Gain level switch
• TE balance adjustment function • Digital dynamics (compressor)
Volume increased by +5dB at low level
Digital Signal Processor (DSP) Block • 8× oversampling digital filter
• Supports CAV (Constant Angular Velocity) playback (attenuation: 61dB, ripple within band: ±0.0075dB)
• Frame jitter free • Digital signal output possible after boost
• 0.5× to 4× speed continuous playback possible • Serial data format selectable from (output)
• Allows relative rotational velocity readout 20 bits/18 bits/16 bits (rearward truncation, MSB first)
• Supports variable pitch playback • Digital attenuation: –∞, –60 to +6dB, 2048 steps (linear)
• The bit clock, which strobes the EFM signal, is generated by • Soft mute
the digital PLL. • Digital de-emphasis
• EFM data demodulation • High-cut filter
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction Applications
C1: double correction, C2: quadruple correction CD players
Supported during 4× speed playback
• Noise reduction during track jumps Structure
• Auto zero-cross mute Silicon gate CMOS IC
• Subcode demodulation and subcode-Q data error detection
• Digital spindle servo Absolute Maximum Ratings (Ta = 25°C)
• 16-bit traverse counter • Supply voltage 1 VDD, XVDD VSS – 0.5 to +3.5 V
• Asymmetry correction circuit • Input voltage 1 V I1 VSS – 0.3 to VDD + 0.3 V
• CPU interface on serial bus • Output voltage 1 VO1 VSS – 0.3 to VDD + 0.3 V
• Error correction monitor signal, etc. output from CPU • Supply voltage 2 IOVDD0 to 2, AVDD0 to 5
interface IOVSS – 0.5 to +4.5 V
• Servo auto sequencer • Input voltage 2 V I2 IOVSS – 0.3 to IOVDD + 0.3 V
• Fine search performs track jumps with high accuracy • Output voltage 2 VO2 IOVSS – 0.3 to IOVDD + 0.3 V
• Digital audio interface outputs • Storage temperature
• Digital level meter, peak meter Tstg –55 to +150 °C
• Bilingual compatible • Supply voltage difference
• VCO control mode IOVSS, AVSS, XVSS – VSS
• CD TEXT data demodulation –0.3 to +0.3 V
XVDD – VDD –0.3 to +0.3 V
Digital Servo (DSSP) Block IOVDD, AVDD, XVDD – VDD
• Microcomputer software-based flexible servo control –0.3 to +0.3 V
• Offset cancel function for servo error signal (IOVDD, AVDD, XVDD < 2.3V)
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment functions Recommended Operating Conditions
• Surf jump function supporting micro two-axis • Supply voltage 1 VDD, XVDD 2.5 ± 0.2 V
• Tracking filter: 6 stages, • Supply voltage 2 IOVDD0 to 2, AVDD0 to 5
Focus filter: 5 stages 3.3 ± 0.3 V
• Operating temperature
Digital Filter, DAC and Analog Low-pass Filter Blocks Topr –20 to +75 °C
• Digital dynamic bass boost and high boost
Bass Boost: 4th-order IIR 24dB/Oct I/O Pin Capacitance
+10dB/+14dB/+18dB/+22dB • Input capacitance CI 7 (Max.) pF
High Boost: Second-order IIR 12dB/Oct • Output capacitance CO 7 (Max.) pF
+4dB/+6dB/+8dB/+10dB • I/O capacitance CI/O 7 (Max.) pF
• Independent turnover frequency selection possible Note) Measurement conditions VDD = VI = 0V
Bass Boost: 125Hz/160Hz/200Hz fM = 1MHz
High Boost: 5kHz/7kHz

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–
E03736-PS
 CXD3059AR

Block Diagram

WDCK
WFCK
EMPH

SCOR

SQSO
COUT

SQCK

SYSM
XUGF

SBSO
C2PO

SENS
CLOK

EXCK
DATA
SSTP

ATSK
SCLK

XLAT
GFS
SERVO
Block CPU Interface
SERVO
Interface Bass Boost Block
MIRR
MIRR LMUT
DFCT DFCT RMUT
FOK
FOK
AOUT2
LOCK LPF
VREFR
MDP
VREL
DAC LPF
SFDR AOUT1
SRDR
EMPHI
TFDR PWM LRCKI
TRDR Generator
PCMDI
FFDR
BCKI
FRDR

XTACN
SERVO
DSP XTSL
CD Signal Clock XTAI
Prosessor Generator XTAO
TEI Block
A/D VCTL
FEI Servo
Converter
Auto VPCO
Sequencer
Digital
DOUT
Digital OUT
CLV BCK
Selector PCMD
D/A
TEO Interface LRCK
E TE
Error 32K
F Corrector RAM XRST

FEO TES1
FE TEST
EFM
Demodulator AVDD0 to 5
A Sub Code
Processor AVSS0 to 5
B SUM IOVDD0 to 2
C RFamp Block IOVSS0 to 2
D Asymmetry Digital DC/DC
Corrector PLL Convertor VDD
VSS
VC VC
APC ATT EQ AMP
PD
PDSENS
LD

RFDCO
AC_SUM
EQ_IN

RFC

RFACO

RFACI
BIAS
ASYI
ASYO

CLTV
FIFO
FILI
PCO
XPCK

DDVROUT
DDVRSEN
DDCR

–2–
 CXD3059AR

Pin Configuration

VREFR
IOVDD0

IOVDD2
AOUT2

AOUT1

IOVSS2
VREFL

PCMDI
EMPHI
AVDD2

AVDD1

PCMD

LRCKI
AVSS2
AVSS1
RMUT

EMPH
DOUT
XTAO

LRCK
TEST
TES1
XVDD

XVSS
XTAI

BCK
VDD

VSS
NC

NC
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

LMUT 91 60 BCKI
NC 92 59 NC
XTSL 93 58 DDCR
IOVSS0 94 57 AVSS5
XTACN 95 56 DDVRSEN
SQSO 96 55 DDVROUT
SQCK 97 54 AVDD5
SBSO 98 53 PCO
EXCK 99 52 FILI
XRST 100 51 FILO
SYSM 101 50 CLTV
DATA 102 49 AVSS3
VSS 103 48 VCTL
XLAT 104 47 VPCO
CLOK 105 46 ASYO
VDD 106 45 ASYI
SENS 107 44 BIAS
SCLK 108 43 AVDD3
ATSK 109 42 RFACI
WFCK 110 41 RFACO
XUGF 111 40 AVSS4
XPCK 112 39 RFC
GFS 113 38 NC
C2PO 114 37 PD
SCOR 115 36 LD
VDD 116 35 EQ_IN
C4M 117 34 AC_SUM
WDCK 118 33 PDSENS
COUT 119 32 RFDCO
NC 120 31 AVDD4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
MIRR
DFCT
FOK
VSS
LOCK
MDP
SSTP
IOVSS1
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
IOVDD1
AVDD0
AVSS0
NC
E
F
TEI
TEO
FEI
FEO
VC
A
B
C
D
NC

–3–
 CXD3059AR

Pin Description
Power Pin
Symbol I/O Description
supply No.
1 MIRR I/O 1, 0 Mirror signal input/output.
2 DFCT I/O 1, 0 Defect signal input/output.
3 FOK I/O 1, 0 Focus OK signal input/output.
4 VSS — — Internal digital GND.
GFS is sampled at 460Hz; when GFS is high , this pin outputs a high
5 LOCK I/O 1, 0 signal. If GFS is low eight consecutive
samples, this pin outputs low. Or this pin inputs when LKIN = "1".
6 MDP O 1, Z, 0 Spindle motor servo control output.
Digital
I/O = 3.3V 7 SSTP I Disk innermost detection signal input.
Internal = 8 IOVSS1 — — I/O digital GND.
2.5V
9 SFDR O 1, 0 Sled drive output.
10 SRDR O 1, 0 Sled drive output.
11 TFDR O 1, 0 Tracking drive output.
12 TRDR O 1, 0 Tracking drive output.
13 FFDR O 1, 0 Focus drive output.
14 FRDR O 1, 0 Focus drive output.
15 IOVDD1 — — I/O digital power supply.
A/D 16 AVDD0 — — Analog power supply.
3.3V 17 AVSS0 — — Analog GND.
— 18 NC — —
19 E I E signal input.
20 F I F signal input.
21 TEI I Tracking error signal input to DSSP block.
22 TEO O Tracking error signal output from RF amplifier block.
23 FEI I Focus error signal input to DSSP block.
24 FEO O Focus error signal output from RF amplifier block.
Center voltage output from RF amplifier block.
25 VC I/O
Center voltage input to DSSP block by command switch.
26 A I A signal input.
RFamp 27 B I B signal input.
3.3V
28 C I C signal input.
29 D I D signal input.
30 NC — —
31 AVDD4 — — Analog power supply.
RFDC signal output.
32 RFDCO I/O
RFDC signal input to DSSP block by command switch.
33 PDSENS I Reference voltage pin for PD.
34 AC_SUM O Analog RFAC summing amplifier output.

–4–
 CXD3059AR

Power Pin
Symbol I/O Description
supply No.
35 EQ_IN I Equalizer circuit input.
36 LD O APC amplifier output.
37 PD I APC amplifier input.
RFamp
3.3V 38 NC — —
39 RFC I Equalizer cut-off frequency adjustment pin.
40 AVSS4 — — Analog GND.
41 RFACO O RFAC signal output.
42 RFACI I RFAC signal input or EFM signal input.
43 AVDD3 — — Analog power supply.
44 BIAS I Asymmetry circuit constant current input.
45 ASYI I Asymmetry comparator voltage input.
46 ASYO O 1, 0 EFM full-swing output. (Low = VSS, High = VDD)

ASYM 47 VPCO O 1, Z, 0 Wide-band EFM PLL charge pump output.

3.3V 48 VCTL I Wide-band EFM PLL VCO2 control voltage input.
49 AVSS3 — — Analog GND.
50 CLTV I Multiplier VCO1 control voltage input.
51 FILO O Analog Master PLL (slave = digital PLL) filter output.
52 FILI I Master PLL filter input.
53 PCO O 1, Z, 0 Master PLL charge pump output.
54 AVDD5 — — Analog power supply.
DC/DC converter output.
55 DDVROUT O
Leave open when not using.
DC/DC DC/DC converter output voltage monitor pin.
3.3V 56 DDVRSEN I
Connect to analog power supply when not using.
57 AVSS5 — — Analog GND.
58 DDCR I DC/DC converter reset pin.
— 59 NC — —
60 BCKI I D/A interface bit clock input.
D/A interface serial data input.
61 PCMDI I
(2's COMP, MSB first)
62 LRCKl I D/A interface LR clock input.
63 LRCK O 1, 0 D/A interface LR clock output. f = Fs
Digital
I/O = 3.3V 64 VSS — — Internal digital GND.
Internal = D/A interface serial data output.
2.5V 65 PCMD O 1, 0
(2's COMP, MSB first)
66 BCK O 1, 0 D/A interface bit clock output.
67 VDD — — Internal digital power supply.
68 EMPH O 1, 0 High when the playback disc has emphasis, low it has not.
69 EMPHI I High when de-emphasis is ON, low when input OFF.
–5–
 CXD3059AR

Power Pin
Symbol I/O Description
supply No.
70 IOVDD2 — — I/O digital power supply.
Digital 71 DOUT O 1, 0 Digital Out output.
I/O = 3.3V
72 TEST I Test pin. Normally GND.
Internal =
2.5V 73 TES1 I Test pin. Normally GND.
74 IOVss2 — — I/O digital GND.
— 75 NC — —
76 XVSS — — Master clock GND.
X'tal 77 XTAO O Crystal oscillation circuit output.
2.5V 78 XTAI I Crystal oscillation circuit input.
79 XVDD — — Master clock power supply.
80 AVDD1 — — Analog power supply.

Lch 81 AOUT1 O Lch analog output.

3.3V 82 VREFL O Lch reference voltage.
83 AVSS1 — — Analog GND.
84 AVSS2 — — Analog GND.

Rch 85 VREFR O Rch reference voltage.

3.3V 86 AOUT2 O Rch analog output.
87 AVDD2 — — Analog power supply.
— 88 NC — —
89 IOVDD0 — — I/O digital power supply.
90 RMUT O 1, 0 Rch "0" detection flag.
91 LMUT O 1, 0 Lch "0" detection flag.
92 NC — —
Crystal selection input.
93 XTSL I Low when the crystal is 16.9344MHz;
high when the crystal is 33.8688MHz.
94 IOVSS0 — — I/O digital GND.
Oscillation circuit control.
95 XTACN I
Digital Self-oscillation when high, oscillation stop when low.
I/O = 3.3V
Subcode Q 80-bit and PCM peak and level data output.
Internal = 96 SQSO O 1, 0
CD TEXT data output.
2.5V
97 SQCK I SQSO readout clock input.
98 SBSO O 1, 0 Subcode P to W serial output.
99 EXCK I SBSO readout clock input.
100 XRST I System reset. Reset when low.
101 SYSM I Mute input. Muted when high.
102 D ATA I Serial data input from CPU.
103 VSS — — Internal digital GND.
104 XLAT I Latch input from CPU. The serial data is latched at the falling edge.
–6–
 CXD3059AR

Power Pin
Symbol I/O Description
supply No.
105 CLOK I Serial data transfer clock input from CPU.
106 VDD — — Internal digital power supply.
107 SENS O 1, 0 SENS output to CPU.
108 SCLK I SENS serial data readout clock input.
109 ATSK I/O 1, 0 Anti-shock input/output.
110 WFCK O 1, 0 WFCK output.
XUGF output.
111 XUGF O 1, 0
Output MNT0, RFCK, SOUT by command switch.
XPCK output.
112 XPCK O 1, 0
Output MNT1, SOCK by command switch.
Digital
I/O = 3.3V 113 GFS GFS output.
O 1, 0
Internal = Output MNT2, XROF, XOLT by command switch.
2.5V C2PO output.
114 C2PO O 1, 0
Output MNT3, GTOP by command switch.
115 SCOR O 1, 0 High output when the subcode sync, S0 or S1, is detected.
116 VDD — — Internal digital power supply.
4.2336MHz output.
117 C4M O 1, 0 1/4 frequency-division output of the V16M in CAV-W mode and
variable pitch mode.
Word clock output. f = 2Fs.
118 WDCK O 1, 0
GRSCOR output by command switch.
119 COUT I/O 1, 0 Track number count signal input/output.
120 NC — —

Notes)
• PCMD is a MSB first, two's complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync
protection.
• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM
signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.
• C2PO represents the data error status.
• XROF is generated when the 32K RAM exceeds the ±28 frame jitter margin.
• C4M is a 4.2336MHz output that changes in CAV-W mode and variable pitch mode.
• FSTO is the 2/3 frequency-division output of the XTAI pin.
• SOUT is the serial data output inside the servo block.
• SOCK is the serial data readout clock output inside the servo block.
• XOLT is the serial data latch output inside the servo block.

–7–
 CXD3059AR

Monitor Pin Output Combinations

Command bit
Output data
SRO1 MTSL1 MTSL0
0 0 0 XUGF XPCK GFS C2PO
0 0 1 MNT0 MNT1 MNT2 MNT3
0 1 0 RFCK XPCK XROF GTOP
0 1 1 C4M GSTO GFS C2PO
1 0 0 SOUT SOCK XOLT C2PO

Reset Timing when Power on

Power on with XRST pin low.

Set XRST pin high after holding it low 100ns or more to cancel reset.

–8–
 CXD3059AR

RF Block Pin Equivalent Circuit

Pin
Symbol I/O Equivalent circuit Description
No.

19 E I 19

VC
Tracking error amplifier input.

20 F I 20

VC

Tracking error signal input to DSSP

21 TEI I 21
block.

1pF
22 TEO O Tracking error amplifier output.
22

Focus error signal input to DSSP

23 FEI I 23
block.

1pF
24 FEO O Focus error amplifier output.
24

25 VC I/O (AVDD4 – AVSS4)/2 voltage output.

25

–9–
 CXD3059AR

Pin
Symbol I/O Equivalent circuit Description
No.

26 A I
15kΩ
26

27 B I
27

RF summing amplifier and focus

30kΩ error amplifier input.
28
28 C I
30kΩ

29

29 D I

30 NC — — —
31 AVDD4 — — Analog power supply.

10kΩ

32 RFDCO I/O 0.5pF RFDC amplifier output.

100Ω
32

59kΩ
10kΩ APC amplifier reference voltage
33 PDSENS I 33
(GND signal) input.

34 AC_SUM O RFAC summing amplifier output.

34

– 10 –
 CXD3059AR

Pin
Symbol I/O Equivalent circuit Description
No.

35
4kΩ

35 EQ_IN I 4kΩ Equalizer circuit input.

4kΩ

4kΩ
VC

57kΩ
36 LD O 10kΩ
APC amplifier output.

500Ω
36

1kΩ
37 PD I 37 APC amplifier input.

38 NC — — —

39

Equalizer cut-off frequency

39 RFC I
adjustment.

40 AVSS4 — — Analog GND.

VC 25Ω
41 RFACO O 41 RFAC amplifier output.

– 11 –
 CXD3059AR

Electrical Characteristics

1. DC Characteristics

(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –20 to +75°C)

Applicable
Item Conditions Min. Typ. Max. Unit
pins
High level
VIH (1) 0.7VDD
input voltage
Input
V ∗1, ∗3, ∗9
voltage (1) Low level
VIL (1) 0.2VDD
input voltage
High level
VIH (2) 0.7VDD
input voltage
Input Low level
VIL (2) Schmitt input 0.2VDD V ∗2
voltage (2) input voltage
Vt+ –
Hysteresis 0.5
Vt–
Input
Input voltage VIN (3) Analog input VSS VDD V ∗4, ∗12
voltage (3)
High level
VOH (1) IOH = –2.4mA VDD – 0.4
Output output voltage ∗5, ∗8, ∗9
V
voltage (1) Low level
VOL (1) IOL = 4mA 0.4
output voltage
High level
VOH (2) IOH = –1.2mA VDD – 0.4
Output output voltage ∗6
V
voltage (2) Low level
VOL (2) IOL = 2mA 0.4
output voltage
High level IOH = –2.4, –4.8,
VOH (3) VDD – 0.4
Output output voltage –7.2, –9.6mA ∗7
V
voltage (3) Low level
VOL (3) IOL = 4, 8, 12, 16mA 0.4
output voltage
High level
VOH (4) IOH = –0.28mA VDD – 0.4
Output output voltage ∗11
V
voltage (4) Low level
VOL (4) IOL = 0.36mA 0.4
output voltage

Input leak current II VIN = VSS or VDD –10 10 µA ∗1, ∗2, ∗9

Input leak current

IIH VIN = VDD 40 100 240 µA ∗3
(with pull-down resistor)
Tri-state output leak current
IOZ VIN = VSS or VDD –10 10 µA ∗8
(when high impedance)

– 12 –
 CXD3059AR

Applicable pins
∗1 PCMDI, EMPHI, TEST, TES1, XTSL, XTACN, SYSM, DATA
∗2 BCKI, LRCKI, SQCK, EXCK, XRST, XLAT, CLOK, SCLK
∗3 SSTP
∗4 E, F, TEI, FEI, A, B, C, D, PDSENS, EQ_IN, PD, RFC, RFACI, BIAS, ASYI, VCTL, CLTV, FILI, DDVRSEN,
DDCR
∗5 SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, LRCK, PCMD, BCK, EMPH, RMUT, LMUT, SQSO, SBSO,
WFCK, XUGF, XPCK, GFS, C2PO, SCOR, C4M, WDCK
∗6 ASYO
∗7 DOUT
∗8 MDP, VPCO, PCO, SENS
∗9 MIRR, DFCT, FOK, LOCK, ATSK, COUT
∗10 TEO, FEO, AC_SUM, LD, RFACO, DDVROUT, AOUT1, VREFL, VREFR, AOUT2
∗11 FILO
∗12 VC, RFDCO

– 13 –
 CXD3059AR

2. AC Characteristics

(1) XTAI pin

(a) When using self-oscillation

(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –20 to +75°C)

Item Symbol Conditions Min. Typ. Max. Unit

XTSL = L, $AEXX1 CKSL (1, 0) = 00 16.8 16.9344 17.1
Oscillation
fMAX XTSL = H, $AEXX1 CKSL (1, 0) = 00 33.5 33.8688 34.2 MHz
frequency
XTSL = H, $AEXX1 CKSL (1, 0) = 01 or 10 or 11 67.1 67.7376 68.4

(b) When inputting pulses to XTAI pin

(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –20 to +75°C)

Item Symbol Min. Typ. Max. Unit

High level pulse
tWHX 6.6 32.7 ns
width
Low level pulse
tWLX 6.6 32.7 ns
width

Pulse cycle tCX 14.6 59.5 ns

Input high level VIHX 1.7 V

Input low level VILX 0.7 V

Rise time,
tR , t F 0 10 ns
fall time

tCX

tWHX tWLX

VIHX
VIHX × 0.9

XTAI VDD/2

VIHX × 0.1
VILX

tR tF

Note) When the pulse is input to the XTAI pin, be sure to input it via the capacitor.

– 14 –
 CXD3059AR

(2) CLOK, DATA, XLAT, SQCK and EXCK pins

(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –20 to +75°C)

Item Symbol Min. Typ. Max. Unit

Clock frequency fCK 16 MHz
Clock pulse width tWCK 62.5 30000 ns
Setup time tSU 300 ns
Hold time tH 300 ns
Delay time tD 300 30000 ns
Latch pulse width tWL 750 ns
EXCK frequency fT 0.65 MHz
EXCK pulse width tWT 750 ns
SQCK frequency fT 0.65 MHz
SQCK pulse width tWT 750 120000 ns
COUT frequency (during input)∗ fT 65 kHz
COUT pulse width (during input)∗ fWT 7.5 µs
∗ Only when $44 and $45 are executed.

1/fCK
tWCK tWCK
CLOK

DATA
tWSC
XLAT
tSU tH
tD tWL
EXCK
SQCK
COUT
tWT tWT
1/fT

SBSO
SQSO
tSU tH

– 15 –
 CXD3059AR

(3) SCLK pin

XLAT
tDLS tSPW

SCLK ...
1/fSCLK

Serial Read Out Data MSB ... LSB

(SENS)

(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –20 to +75°C)

Item Symbol Min. Typ. Max. Unit

SCLK frequency fSCLK 16 MHz
SCLK pulse width tSPW 31.3 ns
Delay time tDLS 15 µs

(4) COUT, MIRR and DFCT pins

Operating frequency
(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –20 to +75°C)

Item Symbol Min. Typ. Max. Unit Conditions

COUT maximum operation frequency fCOUT 40 kHz ∗1
MIRR maximum operation frequency fMIRR 40 kHz ∗2
DFCT maximum operation frequency fDFCTH 5 kHz ∗3

∗1 When using a high-speed traverse TZC

∗2
B

When the RF signal continuously satisfies the following conditions during the traverse.
• A = 0.11VDD to 0.23VDD
B
• ≤ 25%
A+B

∗3 During complete RF signal omission.

When settings related to DFCT signal generation are Typ.

– 16 –
 CXD3059AR

1-bit DAC and LPF Block Analog Characteristics

(VDD = XVDD = 2.5V, IOVDD0 to 2 = AVDD0 to 5 = 3.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = +25°C)

Item Symbol Conditions Min. Typ. Max. Unit

Total harmonic
THD 1kHz sine wave, 0dB data, 20kHz LPF 0.006 0.014 %
distortion
Signal-to-noise 1kHz sine wave, 0dB data,
S/N 90 95 dB
ratio AMUT OFF (Using A-weighting filter 20kHz LPF)

Fs = 44.1kHz in all cases.

The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.

100Ω 22µF
AOUT1 (2) Audio Analyzer

2200pF 100kΩ

VREFL (R)

1µF

LPF external circuit diagram

Rch A

DATA RF
TEST DISC CXD3059AR Audio Analyzer
Lch B

Block diagram of analog characteristics measurement

(VDD = XVDD = 2.5V, IOVDD0 to 2 = AVDD0 to 5 = 3.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = +25°C)

Item Symbol Min. Typ. Max. Unit Applicable pins

Output voltage VOUT 920 928 mVrms ∗1

Load resistance RL 10 kΩ ∗1

VREF pin capacitance CVREF 1 µF ∗2

∗ Measurement is conducted for the above circuit diagrams with the sine wave output of 1kHz and 0dB.

Applicable pins
∗1 AOUT1, AOUT2
∗2 VREFL, VREFR
– 17 –
 RF Block Electrical Characteristics

(VDD = XVDD = 2.5V, IOVDD0 to 2 = AVDD0 to 5 = 3.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = +25°C)

Bias conditions
SW Sending Measurement Measure-
Measurement item Symbol AC input AC input DC input DC input VDD AVDD Min. Typ. Max. Unit
conditions command conditions ment pins
amplitude frequency voltage current

Connect to
Input impedance VC except A, B,
RA,B,C,D Pin current 10 15 20 kΩ
(A, B, C and D) measure- C, D
ment pins.
Input impedance 2.5V 3.3V
RE,F Pin current E, F 21 30 39 kΩ
(E and F)

Input impedance
RPD Pin current PD 10 MΩ
(PD)

RF block current
consumption IAVD $3AF100 Pin current AVDD4 40 70 mA
(on operation)
2.5V 3.3V
RF block current
consumption ISTB $ADF7CC00 Pin current AVDD4 1 mA

– 18 –
(on standby)

0.5AVDD 0.5AVDD
Output voltage VVC ±3mA 2.5V 3.3V Pin voltage VC 0.5AVDD V

VC
– 0.1 + 0.1

PD input voltage which

Input voltage VPD 0 LD, PD 100 150 200 mV
LD pin voltage is 1.41V

Output voltage AVDD

VLDstb $AD000800 0 Pin voltage LD V
(on standby) – 0.2

VPD +
VPDT 0 Pin voltage LD 1.89 2.14 2.39 V
Input voltage 12mV
2.5V 3.3V

APC
range VPD –
VPDB 0 Pin voltage LD 0.43 0.68 0.93 V
12mV

Maximum
ILD 0 1mA Pin voltage LD 0.34 0.64 0.94 V
output current

Output
RLD VPD 1mA Pin voltage LD 1.66 1.91 2.16 V
impedance
CXD3059AR
 Bias conditions
SW Sending Measurement Measure-
Measurement item Symbol AC input AC input DC input DC input VDD AVDD Min. Typ. Max. Unit
conditions command conditions ment pins
amplitude frequency voltage current

Input voltage Pin voltage, 0.5AVDD 0.9AVDD

VIR-ACSUM RFDC V
range A+B+C+D – 0.1 + 0.1

Output voltage
VOR-ACSUM Pin voltage RFDC 0.47AVDD 0.65AVDD V
range

Input conversion 0.5AVDD 0.5AVDD

VOF-ACSUM $3AA000 Pin voltage RFDC V
DC offset voltage – 0.23 + 0.23

Input conversion
µV/
DC offset VDF-ACSUM $3AA01C 2.5V 3V ±6
°C
temperature drift

ACSUM
Offset voltage VOFFSUM Pin voltage RFDC 0.7 0.9 1.1 V

Frequency
FSUM1 $3AA004 61mVp-p –4 0 1 dB
characteristics 1
0.2/6MHz VC + VAC1/2 20 log (V6M/V0.2M) RFDC
Frequency
FSUM2 $3AA018 104mVp-p –4 0 1 dB
characteristics 2

Distortion rate DSUM 600mVp-p 3MHz VC + VAC1/2 RFDC 3 %

– 19 –
(V6M/V3M) × 100

Input voltage Pin voltage, 0.3AVDD 0.7AVDD

VIR-RFDC RFDC V
range A+B+C+D – 0.1 + 0.1

Output voltage
VOR-RFDC Pin voltage RFDC 0.25AVDD 0.75AVDD V
range

Input conversion 0.3AVDD 0.3AVDD

VOF-RFDC $3AA000 Pin voltage RFDC V
DC offset voltage – 0.23 + 0.23

Input conversion
2.5V 3V µV/
DC offset VDF-RFDC $3AA01C ±6

RFDC
°C
temperature drift

Frequency
FRFDC1 $3AA004 61mVp-p –4 0 1 dB
characteristics 1
0.2/6MHz VC + VAC1/2 20 log (V6M/V0.2M) RFDC
Frequency
FRFDC2 $3AA018 104mVp-p –4 0 1 dB
characteristics 2

Distortion rate DRFDC 1.5Vp-p 100kHz RFDC 0.1 %

CXD3059AR
 Bias conditions
SW Sending Measurement Measure-
Measurement item Symbol AC input AC input DC input DC input VDD AVDD Min. Typ. Max. Unit
conditions command conditions ment pins
amplitude frequency voltage current

Input voltage VC reference about 0.375 0.625

VIR-FE FE V
range (B + D) and (A + C) AVDD AVDD

Output voltage AVDD

VOR-FE Pin voltage FE 0.5 V
range – 0.5

Input conversion 0.5AVDD 0.5AVDD

VOF-FE Pin voltage FE V
DC offset voltage – 0.03 + 0.03

Input conversion
µV/
DC offset VDF-FE 2.5V 3V ±2.8

FE
°C
temperature drift

Offset voltage VOFFFE Pin voltage FE –0.06 0 0.06 V

Frequency
FFE1 $3AA104 30mVp-p –1 0 1 dB
characteristics 1 10/
20 log (V100k/V10k) FE
Frequency 100kHz
FFE2 $3AA118 52mVp-p –1 0 1 dB
characteristics 2

Distortion rate DFE 600mVp-p 50kHz FE 3 %

– 20 –
(V50k/V100k) × 100

Input voltage VC reference about

VIR-TE TE 0.4AVDD 0.6AVDD V
range (B + D) and (A + C)

Output voltage AVDD

VOR-TE Pin voltage TE 0.5 V
range – 0.5

Input conversion 0.5AVDD 0.5AVDD

VOF-TE Pin voltage TE V
DC offset voltage – 0.03 + 0.03

Input conversion
2.5V 3V µV/
DC offset VDF-TE ±2.5

TE
°C
temperature drift

Offset voltage VOFFTE Pin voltage TE –0.075 0 0.075 V

Frequency
FTE1 $3AA204 28mVp-p –1 0 1 dB
characteristics 1 10/
20 log (V100k/V10k) TE
Frequency 100kHz
FTE2 $3AA218 45mVp-p –1 0 1 dB
characteristics 2

Distortion rate DTE $3AA200 480mVp-p 50kHz (V50k/V100k) × 100 TE 3 %

CXD3059AR
 Bias conditions
SW Sending Measurement Measure-
Measurement item Symbol AC input AC input DC input DC input VDD AVDD Min. Typ. Max. Unit
conditions command conditions ment pins
amplitude frequency voltage current

Input voltage Distortion rate 3% or

VIR-EQ RFACO 250 mVp-p
range less, no DC bias

Output voltage AVDD

VOR-EQ Pin voltage RFACO 0.5 V
range – 0.5

Input conversion
VOF-EQ Pin voltage RFACO –0.25 0.25 V
DC offset voltage

Input conversion
DC offset VDF-EQ 2.5V 3V Ta = –20 to +75°C ±0.1 V

EQ
temperature drift

Offset voltage VOFFEQ Pin voltage RFACO –0.5 0 0.5 V

Frequency
FEQ1 $3AA204 28mVp-p –1 0 1 dB
characteristics 1 10/
20 log (V100k/V10k) RFACO
Frequency 100kHz
FEQ2 $3AA218 45mVp-p –1 0 1 dB
characteristics 2

Distortion rate DEQ $3AA200 1.2Vp-p 360kHz 3 %

– 21 –
(V720k/V360k) × 100 RFACO
CXD3059AR
 CXD3059AR

Notes on Operation for RFC Pin

• Set each impedance of the heavy line shown bellow 0.1Ω or less.
• Make each wiring length of L1 to L4, L1 ≤ 20mm, L2 ≤ 20mm and L3 + L4 ≤ 40mm.
• Use the bypass condenser C with capacitance led by resistance (regulator output impedance and wiring
resistance to C) or more seeing the figure bellow.

Regulator 4
GND OUT
3

R [Ω]
R
2
AVS
0.1µF
1

C L2
L3 0
0 20 40 60 80 100
L1 C [µF]
15kΩ 0.1µF
Impedance R tolerance for bypass condenser C
L4

AVSS4 RFC AVDD4

– 22 –
 CXD3059AR

DC-DC Converter Characteristics

(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –20 to +75°C)

Item Symbol Conditions Min. Typ. Max. Unit

Output voltage VO — 2.3 2.5 2.7 V
Output current Iope — — — 100 mA

DDVROUT VOUT

DDCR

R1 C1 C2

DC-DC converter application circuit sample

(1) C2 is the oscillation stopping capacitor. Since there is possibility of an oscillation when the capacity value
changes by temperature change etc., the electrolytic capacitor with small internal series resistance (ESR)
is recommended. Capacitance 100µF is recommended. (Should be 50µF or more)
(2) Since protection circuit is built in the DC-DC converter output, it operates when an overcurrent flows.
Cancelling after protection circuit operation needs to make power supply voltage 0.7V or less once. After
that, when you switch ON power supply, set XRST pin in the condition of low.
To cancel the reset, set high after holding XRST low 100ns or more after power ON.
(3) The R1 and C1 of application circuit example have the constant assuming that power supply rise time is
400ms or less. When it is 400ms or more, it is necessary to enlarge the value of R1 × C1.

– 23 –
 CXD3059AR

CPU Interface Timing

750ns to 30µs

CLOK

DATA D0 D1 D18 D19 D20 D21 D22 D23

750ns or more

XLAT

Registers Valid

Spindle Output

n . 236 (ns) n = 0 to 31
Acceleration

MDP Z
132kHz
7.6µs Deceleration

Acceleration

MDP Z
264kHz
3.8µs Deceleration

Servo Output

MCK
(5.6448MHz) ↑ ↑ ↑ ↑ ↑ ↑ ↑
Output value + A Output value – A Output value 0
SLD
64tMCK 64tMCK 64tMCK

SFDR AtMCK

SRDR AtMCK

FCS/TRK

32tMCK 32tMCK 32tMCK 32tMCK 32tMCK 32tMCK

FFDR/
TFDR A tMCK A tMCK
2 2
FRDR/
TRDR A tMCK A tMCK
2 2

– 24 –
 CXD3059AR

DA Interface

× speed playback LRCK = 44.1kHz, BCK = 2.1168MHz)

CDDSP output selected (1×

LRCK
1 2 3 4 5 6 7 8 9 10 11 12 24
BCK

WDCK

PCMD R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB

× speed playback LRCK = 44.1kHz, BCK = 2.8224MHz)

DAC output selected (1×

$A5EA OBIT1 = 1, OBIT0 = 1

LRCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32
BCK

WDCK

PCMD R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB

$A5EA OBIT1 = 1, OBIT0 = 0

PCMD R0 Lch MSB (17) L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB

$A5EA OBIT1 = 0, OBIT0 = 0

PCMD R0 Lch MSB (19) L18 L17 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB

DAC block input timing (LRCK = 44.1kHz, BCK = 2.1168MHz)

LRCKI
1 2 3 4 5 6 7 8 9 10 11 12 24
BCKI

PCMDI R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB

– 25 –
 CXD3059AR

Application Circuit

Rch

Lch
RMUT

EMPH
DOUT
BCK
PCMD
LRCK

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RMUT
IOVDD0
NC
AVDD2
AOUT2
VREFR
AVSS2
AVSS1
VREFL
AOUT1
AVDD1
XVDD
XTAI
XTAO
XVSS
NC
IOVSS2
TES1
TEST
DOUT
IOVDD2
EMPHI
EMPH
VDD
BCK
PCMD
VSS
LRCK
LRCKI
PCMDI
LMUT 91 LMUT BCKI 60
92 NC NC 59
93 XTSL DDCR 58
94 IOVSS0 AVSS5 57
95 XTACN DDVRSEN 56 DDVROUT
96 SQSO DDVROUT 55
97 SQCK AVDD5 54
SQSO SBSO 98 SBSO PCO 53
SQCK 99 EXCK FILI 52
XRST 100 XRST FILO 51
SYSM 101 SYSM CLTV 50
DATA 102 DATA AVSS3 49
XLAT 103 VSS VCTL 48
CLOK 104 XLAT VPCO 47
SENS 105 CLOK ASYO 46
CXD3059AR
SCLK 106 VDD ASYI 45
SCOR 107 SENS BIAS 44
FOK 108 SCLK AVDD3 43
109 ATSK RFACI 42
WFCK 110 WFCK RFACO 41
XUGF 111 XUGF AVSS4 40
XPCK 112 XPCK RFC 39
GFS 113 GFS NC 38
C2PO 114 C2PO PD 37
115 SCOR LD 36 Driver circuit
116 VDD EQ_IN 35
C4M 117 C4M AC_SUM 34
WDCK 118 WDCK PDSENS 33
COUT 119 COUT RFDCO 32 RFDCO
IOVDD1
IOVSS1

AVDD0

PD
AVSS0

120 NC AVDD4 31
SRDR

TRDR

FRDR
LOCK

SFDR
DFCT

TFDR

FFDR
SSTP
MIRR

MDP
FOK

TEO

FEO
VSS

TEI

FEI
NC

NC
VC

LD
C
D
E

A
B
F

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A.GND
D
C
B
MIRR
DFCT

LOCK

A
VC
F
E
FD
TD
Driver circuit
SLED
SPDL

Limit switch

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 26 –
 CXD3059AR

Package Outline Unit: mm

120PIN LQFP (PLASTIC)

18.0 ± 0.2 1.7 MAX

16.0 ± 0.1 1.4 ± 0.1

90 61 S

0.1 S
91 60

120 31

1 30
0.5 b
0.1 M S

0.1 ± 0.05
0.6 ± 0.15

b = 0.20 ± 0.03
(17.0)

0.25
0.125 ± 0.03
(0.5)

0˚ to 10˚

DETAIL A DETAIL B
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE LQFP-120P-L01 LEAD TREATMENT PALLADIUM PLATING

EIAJ CODE LQFP120-P-1616 LEAD MATERIAL COPPER ALLOY

JEDEC CODE PACKAGE MASS 0.8g

– 27 – Sony Corporation