ĐẠI HỌC QUỐC GIA HÀ NỘI

VIỆN CÔNG NGHỆ THÔNG TIN

Computer Memory Devices

Memory Basics

Dr. Duong Quang Khanh

VNU Information Technology Institute
Email: khanhdq@vnu.edu.vn

Hanoi, 11/2/2025
❑ Computer memory is the storage space in
computer where data is to be processed and
instructions required for processing are stored.
❑ The memory is divided into large number of
small parts. Each part is called a cell. Each
location or cell has a unique address which
varies from zero to memory size minus one.
❑ For example If computer has 64k words, then
this memory unit has 64*1024=65536 memory
location. The address of these locations varies
from 0 to 65535.
 MEMORY DEFINITIONS

❑ Memory ─ A collection of storage cells together with the necessary circuits

to transfer information to and from them.

❑ Memory Organization ─ the basic architectural structure of a memory in

terms of how data is accessed.

❑ Random Access Memory ( ─ a memory organized such that data can be

transferred to or from any cell (or collection of cells) in a time that is not
dependent upon the particular cell selected.

❑ Memory Address ─ A vector of bits that identifies a particular memory

element (or collection of elements).
 MEMORY DEFINITIONS

❑ Typical data elements are:

▪ bit ─ a single binary digit
▪ byte ─ a collection of eight bits accessed together
▪ word ─ a collection of binary bits whose size is a typical unit of access
for the memory. It is typically a power of two multiple of bytes (e.g., 1
byte, 2 bytes, 4 bytes, 8 bytes, etc.)

❑ Memory Data ─ a bit or a collection of bits to be stored into or accessed

from memory cells.

❑ Memory Operations ─ operations on memory data supported by the

memory unit. Typically, read and write operations over some data element
(bit, byte, word, etc.).
 MEMORY BLOCK DIAGRAM

❑ A basic memory system is shown here:

▪ k address lines are decoded to address
2^k words of memory.
▪ Each word is n bits.
▪ Read and Write are single control lines
defining the simplest of memory
operations.
MEMORY BLOCK DIAGRAM
 MEMORY BLOCK DIAGRAM

❑ Example memory contents:

A memory with 3 address bits & 8 data
bits has:

▪ k = 3 and n = 8 so 2^3= 8 addresses

labelled 0 to 7.

▪ 2^3= 8 words of 8-bit data

 MEMORY BLOCK DIAGRAM

❑ Each memory location needs an address.

❑ If the memory is addressed to a cell, then one bit is addressed
❑ But, if the memory is addressed to the Byte or Word than that is the smallest
amount of data that can be addressed.
 BASIC MEMORY OPERATIONS

Memory operations require the following:

❑ Data ─ data written to, or read from, memory as required by the operation.

❑ Address ─ specifies the memory location to operate on. The address lines
carry this information into the memory. Typically n bits specify locations of
2^n words.

❑ An operation ─ Information sent to the memory and interpreted as control

information which specifies the type of operation to be performed. Typical
operations are READ and WRITE. Others are READ followed by WRITE and
a variety of operations associated with delivering blocks of data. Operation
signals may also specify timing info
 BASIC MEMORY OPERATIONS

❑ Read Memory ─ an operation that reads a data value stored in memory:

▪ Place a valid address on the address lines.
▪ Wait for the read data to become stable

❑ Write Memory ─ an operation that writes a data value to memory.

▪ Place a valid address on the address lines and valid data on the data lines
▪ Toggle the memory write control line

❑ Sometimes the read or write enable line is defined as a clock with precise
timing information (eg Read Clock, Write Strobe)
▪ Otherwise, it is just an interface signal
▪ Sometimes memory must acknowledge that it has completed the operation
 MEMORY OPERATION TIMING

❑ Most basic memories are asynchronous

▪ Storage in latches or storage of electrical charge.
▪ No clock
❑ Controlled by control inputs and address
❑ Timing of signal changes and data observation is critical to the operation
❑ Read timing: No. of clock pulses required for a memory request is the integer value
greater than or equal to the larger of the access time and write cycle time, divided by
the clock period
MEMORY OPERATION TIMING
 MEMORY OPERATION TIMING

❑ Write timing:

❑ Critical times measured with respect to edges of write pulse (1-0-1):

▪ Address must be established at least a specified time before 1-0 and held for at least
a specified time after 0-1 to avoid disturbing stored contents of other addresses.
▪ Data must be established at least a specified time before 0-1 and held for at least a
specified time after 0-1 to write correctly.
MEMORY OPERATION TIMING
MEMORY SIZE
MEMORY SIZE
 MEMORY SIZE

1. How many address lines and data lines are needed for each of the following
memories stored in memory?
▪ 16K x 8.
▪ 256K x 16
▪ 64M x 32
▪ 2G x 8
 MEMORY SIZE

2. Sketch the memory organization for each of the following memories.

▪ 16K x 8.
▪ 256K x 16
▪ 64M x 32
▪ 2G x 8
 MEMORY SIZE

3. Give the number of bytes stored in each of the following memories.

▪ 16K x 8.
▪ 256K x 16
▪ 64M x 32
▪ 2G x 8
 MEMORY SIZE

❑ Memory is primarily of two types:

▪ Internal Memory − cache memory and primary/main memory
▪ External Memory − magnetic disk / optical disk etc.
Characteristics of Memory Hierarchy are
following when we go from top to bottom.
▪ Capacity in terms of storage increases
▪ Cost per bit of storage decreases
▪ Frequency of access of the memory by
the CPU decreases
▪ Access time by the CPU increases

Viện CNTT | ĐHQGHN

Viện CNTT | ĐHQGHN
❑ Computer running typical scenario:
▪ Turn the computer on.
▪ The computer loads data from read only memory (ROM) and performs a power
on self test (POST) to make sure all the major components are functioning
properly. As part of this test, the memory controller checks all of the memory
addresses with a quick read/write operation to ensure that there are no errors in
the memory chips Read/write means that data is written to a bit and then read
from that bit.
▪ The computer loads the basic input/output system (from ROM). The BIOS
provides the most basic information about storage devices, boot sequence,
security, Plug and Play (auto device recognition) capability and a few other items.
▪ The computer loads the operating system (from the hard drive into the system's
RAM. Generally, the critical parts of the operating system are maintained in RAM
as long as the computer is on. This allows the CPU to have immediate access to
the operating system, which enhances the performance and functionality of the
overall system.
❑ Computer running typical scenario:
▪ When you open an application, it is loaded into RAM To conserve RAM usage,
many applications load only the essential parts of the program initially and then
load other pieces as needed.
▪ After an application is loaded, any files that are opened for use in that application
are loaded into RAM.
▪ When you save a file and close the application, the file is written to the specified
storage device, and then it and the application are purged from RAM.
❑ Fast, powerful CPUs need quick and easy access to large amounts of data in order to
maximize their performance. If the CPU cannot get to the data it needs, it literally
stops and waits for it. Modern CPUs running at speeds of about 1 gigahertz can
consume massive amounts of data – potentially billions of bytes per second. The
problem that computer designers face is that memory that can keep up with a 1
gigahertz CPU is extremely expensive much more expensive than anyone can afford
in large quantities.

❑ Computer designers have solved the cost problem by "memory using expensive
memory in small quantities and then backing it up with larger quantities of less
expensive memory.
❑ The cheapest form of read/write memory in wide use today is the hard disk. Hard
disks provide large quantities of inexpensive, permanent storage. You can buy hard
disk space for pennies per megabyte, but it can take a good bit of time (approaching a
second) to read a megabyte off a hard disk. Because storage space on a hard disk is
so cheap and plentiful, it forms the final stage of a CPUs memory hierarchy, called
virtual memory.

❑ The next level of the hierarchy is RAM. The bit size of a CPU tells you how many
bytes of information it can access from RAM at the same time. For example, a 16 bit
CPU can process 2 bytes at a time (1 byte 8 bits, so 16 bits 2 bytes), and a 64 bit
CPU can process 8 bytes at a time.
 RAM - RANDOM ACCESS MEMORY
❑ System RAM speed is controlled by bus width and bus speed. Bus width refers to
the number of bits that can be sent to the CPU simultaneously, and bus speed refers
to the number of times a group of bits can be sent each second. A bus cycle occurs
every time data travels from memory to the CPU.
❑ For example, a 100 MHz 32 bit bus is theoretically capable of sending 4 bytes 32 bits
divided by 8 = 4 bytes) of data to the CPU 100 million times per second, while a 66
MHz 16 bit bus can send 2 bytes of data 66 million times per second. If you do the
math, you'll find that simply changing the bus width from 16 bits to 32 bits and the
speed from 66 MHz to 100 MHz in our example allows for three times as much data
400 million bytes versus 132 million bytes) to pass through to the CPU every second.
 ROM - READ ONLY MEMORY

❑ ROM stands for Read Only Memory. The memory from which we can only read but
cannot write on it. This type of memory is non volatile. The information is stored
permanently in such memories during manufacture.
❑ A ROM, stores such instruction as are required to start computer when electricity is
first turned on, this operation is referred to as bootstrap ROM chip are not only used
in the computer but also in other electronic items like washing machine and
microwave oven.
❑ There are the various types of ROM:
▪ MROM–Masked ROM
▪ PROM–Programmable Read Only Memory
▪ EPROM–Erasable and Programmable Read Only Memory
▪ EEPROM–Electrically Erasable and Programmable Read Only Memory
 CACHE AND REGISTERS

❑ Caches are designed to alleviate this bottleneck

by making the data used most often by the CPU
instantly available. This is accomplished by
building a small amount of memory, known as
primary or level 1 cache, right into the CPU.
Level 1 cache is very small, normally ranging
between 2 KB and 64 KB.
❑ The secondary or level 2 cache typically
resides on a memory card located near the
CPU. The level 2 cache has a direct connection
to the CPU. A dedicated integrated circuit on the
motherboard, the L 2 controller regulates the
use of the level 2 cache by the CPU. Depending
on the CPU, the size of the level 2 cache ranges
from 256 KB to 2 MB. In most systems, data
needed by the CPU is accessed from the cache
approximately 95 percent of the time, greatly
reducing the overhead needed when the CPU
has to wait for data from the main memory.
Viện CNTT | ĐHQGHN
CACHE AND REGISTERS

Viện CNTT | ĐHQGHN