COLLEGE OF ENGINEERING AND TECHNOLOGY

Komarapalayam-637303

Department of Electronics and Communication Engineering

20EC305 – ANALOG & DIGITAL CIRCUITS LAB

Academic Year: 2023-24

NAME OF THE STUDENT: ……………………………………………..

REG NO. : ……………………………………………..

YEAR/SEM: ……………………………………………...

1
 LABORATORY CLASSES – INFORMATION & STUDENTS INSTRUCTION

Note: 1

Preparation means coming to the lab classes with neatly drawn circuit diagram /
experimental setup / written programs / flowchart, tabular columns, formulae, model
graphs etc in the observation note book and must know the step by step procedure to
conduct the experiment.

Conducting experiment means making connection, preparing the experimental

setup without any mistakes at the time of reporting to the faculty.

Observation means taking correct readings in the proper order and tabulating
the readings in the tabular columns

Calculation means calculating the required parameters using the appropriate

formulae and readings.

Results mean correct value of the required parameters and getting the correct
shape of the characteristics at the time of reporting to the faculty.

Viva voce means answering all the questions given in the manual pertaining to
the experiments.

Full marks will be awarded if the student performs well in each of the above
component.

Note: 2

Incompletion or repetition of experiments means not getting the correct values

of the required parameters and not getting the correct shape of the characteristics at
the first attempt. In such cases, it will be marked as “IC” in red ink in the status
column of the mark allocation table given at the end of every experiment. The students
are expected to redo / repeat the incomplete experiment before coming to the next lab.
In such cases marks will be reduced for conducting, observation, calculation and
results.

Note: 3

Absenteeism due to genuine reasons will be considered for doing the missed
experiments.

In case of power failure, extra classes will be arranged for doing those
experiments only and assessment of all other components preparedness, viva-voce
etc., will be completed in the regular class itself.

2
 LABORATORY CLASSES – INSTRUCTIONS TO STUDENTS

1. Students must attend the Lab classes in the uniform prescribed. Boys – Shirts
tucked in and wearing closed leather shoes.

2. Girls students with Cut shoes, overcoat, plait inside the coat. Avoid wearing loose
garments.

3. Students must check if the components, instruments and machinery are in working
condition before setting up the experiment.

4. Power supply to the experimental setup / equipment / machine must be switched on

only after the faculty checks and gives approval for doing the experiment.

5. Students must start doing the experiments only after getting permission from the
faculty.

6. Any damage to any of the equipment / instrument / machine caused due to

carelessness, the cost will be fully recovered from the individual (or) group of
students.

7. Students may contact the Lab In-charge immediately for any unexpected incidents
and emergency.

8. The apparatus used for the experiments must be cleaned and returned to the
technician, safely without any damage.

9. Make sure, while leaving the lab after the stipulated time, that all the power
connections are switched off.

10. Evaluation

• All students should go thro’ the Lab manual for the experiment to be carried
out for that day and come fully prepared to complete the experiment within
the prescribed periods.
• Students must be fully aware of the core competencies to be gained by doing
experiment / exercise / programs.
• Students should bring the lab record completed for the experiment done along
with the corrected and signed observations of previous experiment.
• The following aspects will be assessed during every exercise, in every lab
class and the marks will be awarded accordingly: Preparedness, way of
conducting experiment, observation, calculations, results, record
presentation, basic understanding and answering for viva questions.
• Marks will be reduced for repetition/re-do, delay in submitting observation
book, record books and not answering for viva questions.

3
 CONTENTS

EX.NO DATE NAME OF THE EXPERIMENT PAGE MARKS STAFFSIGN

NO.

4
AVERAGE:

Staff sign.

5
6
20EC305 ANALOG AND DIGITAL CIRCUITS LABORATORY LTPC002

OBJECTIVES

• Understand the design concepts of regulated power supply and frequency

response of BJT and FET amplifiers
• Study the transfer characteristics of Darlington amplifier
• Learn the performance of single stage and multistage amplifiers
• Acquire the combinational and sequential logic circuits
• Gain the hand on experience in SPICE simulation of Electronic circuits

LIST OF EXPERIMENTS LIST OF ANALOG EXPERIMENTS

1. Design of Regulated Power supplies.

2. Analyze the Frequency Response of CE, CB, CC and CS amplifiers.

3. Design the RC Phase shift and Wien Bridge Oscillator
4. Design and analyze the Darlington Amplifier.
5. Determination of bandwidth of single stage and multistage amplifier.
6. Examine the characteristics of Class A Amplifier.
LIST OF DIGITAL EXPERIMENTS
1. Design and implementation of code converters using logic gates

a) BCD to excess-3 code and vice versa (b) Binary to gray and vice-versa
2. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483
3. Design and implementation of Multiplexer and De-multiplexer using logic gates
4. Design and implementation of encoder and decoder using logic gates
5. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
6. Design and implementation of 3-bit synchronous up/down counter Simulation.
SIMULATION EXPERIMENTS
1. Design CE, CB and CC Amplifiers using Spice
2. Design Darlington Amplifier using Spice
3. Design single stage and multistage amplifiers using Spice
TOTAL: 45 PERIODS OUTCOMES: At the end of the course, the student
should be ableto:
• Differentiate cascade and cascode amplifier.

• Analyze the limitation in bandwidth of single stage and multi stage amplifier
• Simulate amplifiers using Spice

7
CIRCUIT DIAGRAM:

MODEL GRAPH:

TABULATION:

8
 1. DESIGN OF REGULATED POWER SUPPLIES.

AIM: DATE:
To design the regulated power supplies and verify the output.

APPARATUS REQUIRED

S.No Name Range Quantity

.

PROCEDURE:

RESULT:

Thus, the power supply was constructed and the output was verified.

9
CIRCUIT DIAGRAM

Output Voltage (in

Frequency (in Hz) volts) Gain= 20 log(Vo/Vin) (in dB)

10
 2.(a) FREQUENCY RESPONSE OF CE AMPLFIER

DATE :
AIM:
- To Plot the frequency response of a BJT amplifier in common emitter configuration.
i. Calculate gain.
ii. Calculate bandwidth.

APPARATUS REQUIRED

S.No Name Range Quantity

.
1. Transistor BC 107
2. Resistor 22K,5.6K,10K,1K,22 Each 1
0 Ω,1K
3. Capacitor 10 µF,100 µF 2,1
4. Function Generator (0-3)MHz 1
5. CRO (0-30)MHz 1
6. Regulated power supply 0-30V 1
7. Bread Board -- 1
8 Wires & Probes - As Per
-

PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Set input voltage, using the signal generator.

3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1M Hz in

regular steps and notedown the corresponding output voltage.
4. Plot the graph; Gain (dB) Vs Frequency (Hz).

RESULT:

Thus, the Common emitter amplifier was constructed and the frequency response curve is plotted.
Gain = dB (maximum).
Bandwidth= fH--fL = Hz.

11
CIRCUIT DIAGRAM

MODEL GRAPH:

F1 F2 f(Hz)
TABULATION:

Keep the input voltage constant, Vin =

Gain= 20 log(Vo/Vin) (in

Frequency (in Hz) Output Voltage (in volts)
dB)

12
 1.b FREQUENCY RESPONSE OF CB AMPLFIER

AIM:

To construct a common base amplifier circuit and to plot the frequency response characteristics.

APPARATUS REQUIRED:

S.No Nam Range Quantit

. e y
1. Transistor BC 107 1
2. Resistor 15kΩ,10kΩ,680Ω,6kΩ 1,1,1,1
3. Capacitor 0.1µF, 47µF 2, 1
4. Function Generator (0-3)MHz 1
5. CRO 30MHz 1
6. Regulated power supply (0-30)V 1
7. Bread Board 1

PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Set input voltage, using the signal generator.

3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1M Hz in

regular steps and notedown the corresponding output voltage.
4. Plot the graph; Gain (dB) Vs Frequency (Hz).

RESULT:

Thus, the Common collector amplifier was constructed and the frequency response curve is plotted.

Gain = dB (maximum).
Bandwidth= fH--fL = Hz

13
CIRCUIT DIAGRAM:

COMMON COLLECTOR TABULATION:

Keep the input voltage constant, Vin =

Frequency (in Hz) Output Voltage (in volts) Gain= 20 log(Vo/Vin) (in dB)

14
 1(c) . COMMON COLLECTOR AMPLIFIER
DATE :
AIM:

To construct a common collector amplifier circuit and to plot the frequency response
characteristics.

APPARATUS REQUIRED:
S.No. Name Range Quantity
1. Transistor
2. Resistor
3. Capacitor
4. Function Generator
5. CRO
6. Regulated power supply
7. Bread Board

PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Set input voltage, using the signal generator.

3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1M Hz in

regular steps and notedown the corresponding output voltage.

4. Plot the graph; Gain (dB) Vs Frequency (Hz).

MODEL GRAPH:

RESULT:
Thus, the Common collector amplifier was constructed and the frequency response curve is
plotted.

Gain = dB (maximum)
Bandwidth= fH--fL = Hz.

15
CIRCUIT DIAGRAM:

TABULATION:

Keep the input voltage constant, Vin =

Frequency (in Hz) Output Voltage (in volts) Gain= 20 log(Vo/Vin) (in dB)

16
 2(d). FREQUENCY RESPONSE OF CS AMPLIFIERS

AIM: -
To plot the frequency response of a FET amplifier in common source mode .

APPARATUS REQUIRED:

S.No. Name Range Quantity

1. FET
2. Resistor
3. Capacitor
4. Function Generator
5. CRO
6. Regulated power supply
7. Bread Board

PROCEDURE: -
1. Connect the circuit diagram as shown in figure.
2. Adjust input signal amplitude 50mV, 1 KHz in the function generator and observe an amplified voltage at
the output without distortion.
3. By keeping input signal voltage, say at 50mV; vary the input signal frequency from 10 to 1MHz in steps
as shown in tabular column and note the corresponding output voltage

MODEL GRAPH:

F1 F2 f(Hz)

RESULT: -
Thus, the FET Common source amplifier was constructed and the frequency response curve is plotted.
Gain = dB (maximum).
Bandwidth= fH--fL = Hz.

17
CIRCUIT DIAGRAM: RC PHASE SHIFT OSCILLATOR

S.No Amplitude(Volts) Time(ms) Frequency(KHz)

18
 3. DESIGN THE RC PHASE SHIFT AND WIEN BRIDGE OSCILLATOR

AIM: DATE:
To plot the frequency response of a design of the RC phase shift and Wien- bridge
oscillator.

APPARATUS REQUIRED:

S.No Name Range Quantity

.
1. Transistor
2. Resistor
3. Capacitor
4. Function Generator
5. CRO
6. Regulated power supply
7. Bread Board

PROCEDURE:
1. Connect the circuit diagram as shown in figure.

2. Adjust input signal amplitude 50mV, 1 KHz in the function generator and observe an
amplified voltage at the output without distortion.
3. By keeping input signal voltage, say at 50mV; vary the input signal frequency from 10
to 1MHz in stepsas shown in tabular column and note the corresponding output voltage

19
CIRCUIT DIAGRAM: WEIN BRIDGE OSCILLATOR

S.No Amplitude(Volts) Time(ms) Frequency(KHz)

20
RESULT:
Thus, design of RC phase shift and Wien bridge oscillator are constructed and verified the
frequency response .

21
CIRCUIT DIAGRAM

TABULATION

Keep the input voltage constant, Vin =

Frequency (in Hz) Output Voltage (in volts) Gain= 20 log(Vo/Vin) (in dB)

22
 4. DARLINGTON AMPLIFIER USING BJT

AIM: DATE:

To construct a Darlington current amplifier circuit and to plot the frequency response
characteristics.

APPARATUS REQUIRED:

S.No Name Range Quantity

.
1. Transistor BC 107 1
2. Resistor 15kΩ,10kΩ,680Ω,6kΩ 1,1,1,1
3. Capacitor 0.1µF, 47µF 2, 1
4. Function Generator (0-3)MHz 1
5. CRO 30MHz 1
6. Regulated power supply (0-30)V 1
7. Bread Board 1

PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Set Vi =50 mv, using the signal generator.
3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1M Hz in
regular steps andnote down the corresponding output voltage.
4. Plot the graph; Gain (dB) vs Frequency(Hz).
5. Calculate the bandwidth from the graph.

F1 F2 f(Hz)
RESULT:

Thus, the Darlington current amplifier was constructed and the frequency response
curve is plotted. The Gain Bandwidth Product is found to be =
23
24
 5. (a)DETERMINATION OF BANDWIDTH OF SINGLE STAGE AMPLIFIERS

AIM: DATE :

To Plot the Frequency Response of a single stage RC Coupled Amplifier with feedback
and withoutfeedback and find the following:

1. Voltage Gain
2. Lower cut off Frequency
3. Upper cut off Frequency
4. Bandwidth & Gain Bandwidth Product

APPARATUS REQUIRED:
S.No Name Range Quantity
1. Transistor BC107 1
2. Resistor 100k Ω 4.7k Ω, 22k Ω 220k 1,1,1,1
Ω 220 Ω
3. Capacitor 10µf ,47 µf 2, 1
4. Function Generator (0-3)MHz 1
5. CRO 30MHz 1
6. Regulated power supply (0-30)V 1
7. Bread Board 1

PROCEDURE: -
1. Connect the circuit diagram as shown in figure.
2. Adjust input signal amplitude in the function generator and observe an amplified
voltage at the outputwithout distortion.
3. By keeping input signal voltage, say at 50mV, vary the input signal frequency from 0 to
1MHz in steps asshown in tabular column and note the corresponding output
Voltages.

MODEL GRAPH

RESULT: -
Frequency response of single amplifier is plotted.
Gain = dB (maximum).

25
CIRCUIT DIAGRAM (MULTISTAGE AMPLIFIER)

TABULATION:
Keep the input voltage constant (Vin) =

Frequency (in Hz) Output Voltage (in volts) Gain = 20 log (Vo / Vin) (in dB)

26
 5. (b) DETERMINATION OF BANDWIDTH OF MULTISTAGE AMPLIFIERS

AIM: DATE :
To Plot the Frequency Response of a Multistage RC Coupled Amplifier with feedback and
without feedbackand find the following:
1. Voltage Gain
2. Lower cut off Frequency
3. Upper cut off Frequency
4. Bandwidth & Gain Bandwidth Product

APPARATUS REQUIRED
S.No. Name Range Quantity
1. Transistor BC107 1
2. Resistor (5KΩ,47 KΩ,2 KΩ, ,1 2 each
KΩ10 KΩ) 4 each
3. Capacitor 10 μF, 1 μF 2,3No.
each
4. Function Generator (0-3)MHz 1
5. CRO 30MHz 1
6. Regulated power supply (0-30)V 1
7. Bread Board 1

PROCEDURE: -
1. Connect the circuit diagram as shown in figure.
2. Adjust input signal amplitude in the function generator and observe an amplified voltage at
the output withoutdistortion.
3. By keeping input signal voltage, say at 50mV, vary the input signal frequency from 0 to
1MHz in steps as shownin tabular column and note the corresponding output
voltages

MODEL GRAPH:

RESULT: -
Frequency response of multistage amplifier is plotted.
Gain = dB (maximum)..
Bandwidth= fH--fL = Hz.
At stage I: Bandwidth= fH—fL=

At stage II : Bandwidth= fH--fL =

27
28
 6. CHARACTERISTICS OF CLASS A AMPLIFIER

AIM: DATE :

To Plot the Frequency Response of a Multistage RC Coupled Amplifier with feedback and
without feedbackand find the following:
1. Voltage Gain
2. Lower cut off Frequency
3. Upper cut off Frequency
4. Bandwidth & Gain Bandwidth Product
APPARATUS REQUIRED
S.No. Name Range Quantity
1. Transistor 1
2. Resistor 2 each
4 each
3. Capacitor 2,3No.
each
4. Function Generator 1
5. CRO 1
6. Regulated power supply 1
7. Bread Board 1

PROCEDURE: -
4. Connect the circuit diagram as shown in figure.
5. Adjust input signal amplitude in the function generator and observe an amplified voltage at
the output withoutdistortion.
6. By keeping input signal voltage, say at 50mV, vary the input signal frequency from 0 to
1MHz in steps as shownin tabular column and note the corresponding output
voltages

RESULT: -
Characteristics and Frequency response of class A amplifier is plotted.

29
CIRCUIT DIAGRAM:

30
 7.(a)SPICE SIMULATION OF COMMON SOURCE AMPLIFIERS

AIM: DATE:
To simulate the Common Source amplifier in Multisim and study the transient and frequency
response.

SOFTWARE TOOL REQUIRED :

(i) Multisim.

PROCEDURE:

1. Open Multisim Software to design FET common source amplifier circuit

2. Select on New editor window and place the required component CS

amplifier on the circuitwindow.
3. Make the connections using wire and check the connections and oscillator.

4. Go for simulation and using Run Key observe the output waveforms on CRO
5. Indicate the node names and go for AC Analysis with the output node

6. Observe the Transient response , Ac Analysis and draw the magnitude response curve
7. Calculate the bandwidth of the amplifier

RESULT:

Thus the frequency and transient response for common source amplifier is plotted using
Multisim.

31
MODEL GRAPH:

32
 7.(b).SPICE SIMULATION OF COMMON EMITTER

AIM: DATE:

To simulate the Common Emitter amplifier in Multisim and study the transient
and frequencyresponse.

SOFTWARE TOOL:
Multisim
PROCEDURE:
1. Open Multisim Software to design Common Emitter amplifier circuit

2. Select on New editor window and place the required component on

the circuitwindow.
3. Make the connections using wire and set oscillator (FG) frequency & amplitude.

4. Check the connections and the specification of components value properly.

5. Go for simulation using Run Key observe the output waveforms on CRO
6. Indicate the node names and go for AC Analysis with the output node

7. Observe the Ac Analysis and draw the magnitude response curve

8. Calculate the bandwidth of the amplifier

RESULT:

Thus the frequency and transient response for common emitter amplifier is plotted
using Multisim.

33
OUTPUT WAVEFORM

34
 7. ( ) SPICE SIMULATION OF COMMON EMITTER AMPLIFIER

AIM: DATE:

To simulate the Common Emitter amplifier in Multisim and study the transient
and frequencyresponse.

SOFTWARE TOOL:
Multisim
PROCEDURE:
1. Open Multisim Software to design Common Emitter amplifier circuit

2. Select on New editor window and place the required component on

the circuitwindow.
3. Make the connections using wire and set oscillator (FG) frequency & amplitude.

4. Check the connections and the specification of components value properly.

5. Go for simulation using Run Key observe the output waveforms on CRO
6. Indicate the node names and go for AC Analysis with the output node

7. Observe the Ac Analysis and draw the magnitude response curve

8. Calculate the bandwidth of the amplifier

RESULT:

Thus the frequency and transient response for common emitter amplifier is plotted
using Multisim.

35
CIRCUIT DIAGRAM COMMON COLLECTOR AMPLIFIER

OUTPUT WAVEFORM

36
 7.( ) SPICE SIMULATION OF COMMON COLLECTOR AMPLIFIER

AIM: DATE:

To simulate the Common collector amplifier in Multisim and study the transient
and frequencyresponse.

SOFTWARE TOOL:
Multisim
PROCEDURE:
1. Open Multisim Software to design Common collector amplifier circuit

2. Select on New editor window and place the required component on

the circuitwindow.
3. Make the connections using wire and set oscillator (FG) frequency & amplitude.

4. Check the connections and the specification of components value properly.

5. Go for simulation using Run Key observe the output waveforms on CRO
6. Indicate the node names and go for AC Analysis with the output node

7. Observe the Ac Analysis and draw the magnitude response curve

8. Calculate the bandwidth of the amplifier

RESULT:

Thus the frequency and transient response for common collector amplifier is plotted
using Multisim.

37
CIRCUIT DIAGRAM

OUTPUT WAVEFORM

38
 7.( ) SPICE SIMULATION OF COMMON BASE AMPLIFIER

AIM: DATE:

To simulate the Common base amplifier in Multisim and study the transient and
frequencyresponse.

SOFTWARE TOOL:
Multisim
PROCEDURE:
1. Open Multisim Software to design Common base amplifier circuit

2. Select on New editor window and place the required component on

the circuitwindow.
3. Make the connections using wire and set oscillator (FG) frequency & amplitude.

4. Check the connections and the specification of components value properly.

5. Go for simulation using Run Key observe the output waveforms on CRO

6. Indicate the node names and go for AC Analysis with the output node

7. Observe the Ac Analysis and draw the magnitude response curve

8. Calculate the bandwidth of the amplifier

RESULT:

Thus the frequency and transient response for common base amplifier is plotted using
Multisim.

39
 CIRCUIT DIAGRAM FOR DARLINGTON AMPLIFIER

OUTPUT WAVEFORM

40
 7.( ) SPICE SIMULATION OF DARLINGTON AMPLIFIER

AIM: DATE:

To simulate the Darlington amplifier in Multisim and study the transient and
frequencyresponse.

SOFTWARE TOOL:
Multisim
PROCEDURE:
1. Open Multisim Software to design the Darlington amplifier circuit

2. Select on New editor window and place the required component on

the circuitwindow.
3. Make the connections using wire and set oscillator (FG) frequency & amplitude.

4. Check the connections and the specification of components value properly.

5. Go for simulation using Run Key observe the output waveforms on CRO
6. Indicate the node names and go for AC Analysis with the output node

7. Observe the Ac Analysis and draw the magnitude response curve

8. Calculate the bandwidth of the amplifier

RESULT:

Thus the frequency and transient response for the Darlington amplifier is plotted using
Multisim.

41
SINGLE STAGE AMPLIFIER

MULTISTAGE AMPLIFIER

42
 7.( )SPICE SIMULATION OF SINGLE STAGE AND MULTISTAGE AMPLIFIER

AIM: DATE:

To simulate the single stage and multistage amplifier in Multisim and study the
transient and frequencyresponse.

SOFTWARE TOOL:
Multisim
PROCEDURE:
1. Open Multisim Software to design the single stage and multistage amplifier circuit

2. Select on New editor window and place the required component on

the circuitwindow.
3. Make the connections using wire and set oscillator (FG) frequency & amplitude.

4. Check the connections and the specification of components value properly.

5. Go for simulation using Run Key observe the output waveforms on CRO
6. Indicate the node names and go for AC Analysis with the output node

7. Observe the Ac Analysis and draw the magnitude response curve

8. Calculate the bandwidth of the amplifier

43
OUTPUT WAVEFORM

SINGLE STAGE OUTPUT

MULTISTAGE OUTPUT

44
RESULT:

Thus the frequency and transient response for the single stage and multistage amplifier is
plotted using Multisim.

45
 LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR

TRUTH TABLE:

Inputs (BINARY CODE) Outputs (GRAY CODE)

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

46
EX.No: DESIGN AND IMPLEMENTATION OF
DATE: CODE CONVERTER

AIM:

To design and implement 4-bit

(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:
BINARY CODES: A group of binary bits that used to represent the characters,
numbers and symbols is defined as binary codes. Binary codes are used in the digital
computer to represent, store and transmit various data.
BCD NUMBERS: BCD numbers are straight binary representation for decimal
numbers. The decimal numbers ate directly represented with the weightages of 8421 in
BCD code. This is popularly used in decimal addition, subtraction, etc. the BCD code
represents the decimal number 0 to 9 with the binary representation 0000 to 1001. In the
4-bit binary representation last six assignments are discarded for BCD number
representation.
EXCESS – 3 CODE: The 4-bit excess – 3 code is obtained by adding 3(0011)
with BCD code. 8421 and 2421 weighted codes provide the self-complement number of
excess – 3 code in the binary representation. The self-complement property of excess – 3
code helps to perform the arithmetic operation in digital system design.

47
LOGIC DIAGRAM:
GRAY TO BINARY CODE CONVERTOR

TRUTH TABLE:

Inputs (GRAY CODE) Outputs (BINARY CODE)

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0

48
GRAY CODE: This code is an un-weighted binary code. A gray code is often used in
the translation of an analog quantity, such as a shaft position in to digital form. The four
bit gray code can be used to represent the decimal number from 0 to 15. In this
representation the last and first entry of gray code consequently differs only in one bit
position (MSB bit). So this is also called reflective code.
CODE CONVERTERS: The presence of different codes in digital system for the same
discrete elements of binary information results the requirement of code conversion. Code
converter is a logic circuit that converts one type of binary code into another type of
binary code.

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

49
LOGIC DIAGRAM:
BCD TO EXCESS-3 CODE CONVERTOR

TRUTH TABLE:

Inputs (BCD CODE) Outputs (EX-3 CODE)

B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

50
51
LOGIC DIAGRAM:
EXCESS-3 TO BCD CODE CONVERTOR

TRUTH TABLE:

Inputs (EX-3 CODE) Outputs (BCD CODE)

E3 E2 E1 E0 B3 B2 B1 B0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

52
RESULT:

53
BLOCK DIAGRAM - BINARY ADDER

PIN DIAGRAM OF IC 7483:

LOGIC DIAGRAM:
4 BIT BINARY ADDER

54
EX.No: DESIGN OF 4-BIT ADDER AND SUBTRACTOR
DATE:

AIM:
To design and imp
lement 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - Adequate

THEORY:

BINARY ADDER:
A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output
carry from each full adder connected to the input carry of next full adder in the chain. The
augend bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from
right to left, with subscript ‘0’ denoting the least significant bit. The carries are connected
in chain through the full adders. The input carry to the adder is C0 and it ripples through
the full adders to the output carry C4. The ‘S’ outputs generate the required sum bits.

BINARY SUBTRACTOR:
The subtraction of unsigned binary numbers can be done most conveniently by
means of complements. The subtraction A – B can be done by taking 2’s complement of
B and adding it to A. The 2’s complement can be obtained by taking 1’s complement and
adding 1 to the least significant pair of bits. The 1’s complements can be implemented
with inverters, and a 1 can be added to the sum through the input carry. The input carry
C0 must be equal to 1 when performing subtraction.

55
 LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM:
4- BIT BINARY ADDER/SUBTRACTOR

56
BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one
common binary adder. This is done by including an exclusive – OR gate with each full-
adder. The mode input M controls the operation of the circuit. When M=0, the circuit is
an adder and when M=1, the circuit becomes a subtractor.

PROCEDURE:

1. Rig the circuit as per the circuit diagram.

2. Apply the given binary input data to the respective input pins
3. Verify the truth table.

57
TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

58
RESULT:

59
LOGIC DIAGRAM: BCD ADDER

60
EX.No: DESIGN OF BCD ADDER
DATE:

AIM:
To design and implement BCD adder IC 7483.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 2
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7408 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - Adequate

THEORY:
BCD ADDER: BCD adder is a circuit that performs the addition of two BCD numbers in
parallel. BCD additions are performed in 4-bit binary form so there is a possibility of
increasing binary number greater than 9 that results wrong output. To avoid this, in BCD
addition correction logic I included as described below,
1. If the binary sum is equal or less than 9 with carry 0, then that binary sum is
correct BCD sum.
2. I the binary sum is equal or less than 9 with carry 1, then that binary sum is an
incorrect BCD sum. To get the correct BCD sum add 0110 with least significant
binary sum digits.
3. If the binary number is greater than 9, then that binary sum is an incorrect BCD
sum. To get the correct BCD sum add 0110 with binary sum digits.
BCD adder can be constructed with three blocks such as two binary adders and the
correction logic circuit. Initially in the BCD adders, the four bit binary numbers are added
using parallel binary adder and then, the binary output is checked to correct as BCD
number. The correction logic generates the correction code based on the binary output
values. When we get the incorrect binary output as per the condition described above, the
correction code is added with the binary output to get the correct BCD number through
second binary adder.

61
TRUTH TABLE:

Binary sum BCD sum

Decimal
K Z8 Z4 Z2 Z1 C S8 S4 S2 S1
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 2
0 0 0 1 1 0 0 0 1 1 3
0 0 1 0 0 0 0 1 0 0 4
0 0 1 0 1 0 0 1 0 1 5
0 0 1 1 0 0 0 1 1 0 6
0 0 1 1 1 0 0 1 1 1 7
0 1 0 0 0 0 1 0 0 0 8
0 1 0 0 1 0 1 0 0 1 9
0 1 0 1 0 1 0 0 0 0 10
0 1 0 1 1 1 0 0 0 1 11
0 1 1 0 0 1 0 0 1 0 12
0 1 1 0 1 1 0 0 1 1 13
0 1 1 1 0 1 0 1 0 0 14
0 1 1 1 1 1 0 1 0 1 15
1 0 0 0 0 1 0 1 1 0 16
1 0 0 0 1 1 0 1 1 1 17
1 0 0 1 0 1 1 0 0 0 18
1 0 0 1 1 1 1 0 0 1 19

62
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

63
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

64
EX.No: DESIGN AND IMPLEMENTATION OF
DATE: MULTIPLEXER AND DEMULTIPLEXER

AIM:
To design and implement multiplexer and demultiplexer using logic gates
and study of IC 74150 and IC 74154.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational circuit that
selects binary information from one of many input lines and directs it to a single output
line. The selection of a particular input line is controlled by a set of selection lines.
Normally there are 2n input line and n selection lines whose bit combination determine
which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor. Decoder can also be used as
demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates.
The data select lines enable only one gate at a time and the data on the data input line will
pass through the selected gate to the associated data output line.

65
CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

66
67
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

68
69
LOGIC DIAGRAM FOR DEMULTIPLEXER:

TRUTH TABLE

INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

70
PROCEDURE:
(iv) Connections are given as per circuit diagram.

(v) Logical inputs are given as per circuit diagram.

(vi) Observe the output and verify the truth table.

71
PIN DIAGRAM FOR IC 74150:

PIN DIAGRAM FOR IC 74154:

72
RESULT:

73
LOGIC DIAGRAM FOR ENCODER:

TRUTH TABLE FOR ENCODER

INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

74
EX.No: DESIGN AND IMPLEMENTATION OF ENCODER AND
DATE: DECODER

AIM:
To design and implement encoder and decoder using logic gates and study of
IC 7445 and IC 74147.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 27

THEORY:

ENCODER:
An encoder is a digital circuit that perform inverse operation of a decoder. An
encoder has 2n input lines and n output lines. In encoder the output lines generates the
binary code corresponding to the input value. In octal to binary encoder it has eight
inputs, one for each octal digit and three output that generate the corresponding binary
code. In encoder it is assumed that only one input has a value of one at any given time
otherwise the circuit is meaningless. It has an ambiguila that when all inputs are zero the
outputs are zero. The zero outputs can also be generated when D0 = 1.

75
PIN DIAGRAM FOR IC 7445: BCD TO DECIMAL DECODER:

PIN DIAGRAM FOR IC 74147:

76
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded
input into coded output where input and output codes are different. The input code
generally has fewer bits than the output code. Each input code word produces a different
output code word i.e there is one to one mapping can be expressed in truth table. In the
block diagram of decoder circuit the encoded information is present as n input producing
2n possible outputs. 2n output values are from 0 through out 2n – 1.

PROCEDURE
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table

77
TRUTH TABLE:

INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

LOGIC DIAGRAM FOR DECODER:

78
RESULT:

79
PIN DIAGRAM FOR IC 7476:

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

80
EX.No: CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE
DATE: COUNTER AND MOD 10/MOD 12 RIPPLE COUNTER

AIM:
To design and verify 4 bit ripple counter mod 10/ mod 12 ripple counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 30

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its

clock input. Counter represents the number of clock pulses arrived. A specified sequence
of states appears as counter output. This is the main difference between a register and a
counter. There are two types of counter, synchronous and asynchronous. In synchronous
common clock is given to all flip flop and in asynchronous first flip flop is clocked by
external pulse and then each successive flip flop is clocked by Q or Q output of previous
stage. A soon the clock of second stage is triggered by output of first stage. Because of
inherent propagation delay time all flip flops are not activated at same time which results
in asynchronous operation.

81
TRUTH TABLE:

CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1

82
83
LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:

CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0

84
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

85
LOGIC DIAGRAM FOR MOD 12 RIPPLES COUNTER:

TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0

86
RESULT

87
STATE DIAGRAM:

CHARACTERISTICS TABLE:

Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

88
EX.No: DESIGN AND IMPLEMENTATION OF 3 BIT
DATE: SYNCHRONOUS UP/DOWN COUNTER SIMULATION

AIM:
To design and implement 3 bit synchronous up/down counter simulation

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 -
2. 3 I/P AND GATE IC 7411 -
3. OR GATE IC 7432 -
4. XOR GATE IC 7486 -
5. NOT GATE IC 7404 -
6. SPICE SOFTWARE - -

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its

clock input. Counter represents the number of clock pulses arrived. An up/down counter
is one that is capable of progressing in increasing order or decreasing order through a
certain sequence. An up/down counter is also called bidirectional counter. Usually
up/down operation of the counter is controlled by up/down signal. When this signal is
high counter goes through up sequence and when up/down signal is low counter follows
reverse sequence.

89
 LOGIC DIAGRAM:

TRUTH TABLE

Input Present State Next State A B C

Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1

90
PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(III) Observe the output and verify the truth table using SPICE software

RUSULT:

91
 VIVA QUESTIONS- DIGITAL EXPERIMENTS
EX.NO.1
1. Define Digital Systems.

2. What is a Logic gate?

3. What are the basic digital logic gates?

4. Which gates are called as the universal gates?

5. State De Morgan's theorem.

EX.NO.2
1. Write the truth table for Half adder

2. Write the truth table for Half subtracor

3. Write the truth table for Ex-OR gate

4. What are the drawbacks of K-MAP

92
EX.NO.3
1. What is code conversion?

2. What is code converter?

3. List the types of code converter.

4. What are all the application of code converter

5. List the application of code gray code.

EX.NO.4
1. Define Half adder and full adder

2. What is binary adder?

3. What is BCD adder?

4. Write the truth table for AND gate and OR gate .

93
EX.NO.5

1. 1. Give the applications of Demultiplexer.

2. Give other name for Multiplexer and demultiplexer

3. Application of Mux.

4. What is digital comparator?

5. Difference between Decoder & Demux.

EX.NO.6
1. List out the applications of decoder?

2. What is priority Encoder?

3. Define Encoder?

4. What is binary decoder?

94
 5. Define Decoder?

EX.NO.7

1. Difference between Combinational & Sequential Circuits.

2. Define Flip flop.

3. What are the different types of flip-flop?

4. Define race around condition.

5. What is a master-slave flip-flop?

EX.NO.8
1. Give the comparison between synchronous & Asynchronous counters

2. Applications of Flip-Flop.

3. List any two design procedure for Synchronous Counter.

4. Define Shift Register Counter.

5. What is meant by counter?

95
 DESIGN AND IMPLEMENTATION OF SHIFT
REGISTER

AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:

A register is capable of shifting its binary information in one or both directions is

known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip
flop is connected to the input of next flip flop of the register. Each clock pulse shifts the
content of register one bit position to right.

96
TRUTH TABLE:
Serial in Serial out
CLK
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:

TRUTH TABLE:
OUTPUT

CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

97
98
LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:

TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:

99
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

VIVA QUESTIONS
1. Define registers.

2. Define shift registers

3. What are the different types of shift type?

4. What is bi-directional shift register and unidirectional shift register?

5. Write the truth table for SISO.

100
TRUTH TABLE:
DATA INPUT OUTPUT

CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

101
RESULT

102