HOLY MARY

INSTITUTE OF TECHNOLOGY & SCIENCE

(COLLEGE OF ENGINEERING)
Bogaram (v), Keesara (M), Ranga Reddy District.

ECPC LAB MANUAL Lab

LABORATORY FACULTY MANUAL
For II year II semester ECE
A.Y.2016-17
DEPARTMENT OF
ELECTRONICS & COMMUNICATION ENGINEERING
VISION of Institute

To be a premier institute in the country and region for the study of engineering,
technology and management by maintaining high academic standards which promote the
analytical thinking and independent judgment among the prime stakeholders enabling
them to function responsible way in the globalized society.

MISSION of Institute

 To impart quality professional education that meets the needs of present and emerging
technological world.
 To strive for student achievement and success, preparing them for life and leadership
with ethics.
 To provide a scholarly and vibrant learning environment that enables faculty, staff and
students achieve personal and professional growth.
 To contribute to advancement of knowledge, in both fundamental and applied areas of
engineering, technology & management.
 To undertake research and development works by forging alliances with research
institutes, government organizations, industries and alumni and become a centre of
excellence for quality professional educations and research.

Vision of the Department

To be a world leader and renowned for Electronics & Communication Engineering and
research Entrepreneurs and Researchers Contributing to the Global Societal Desire.

Mission of the Department

 To educate graduates in the basic principles underlying the field of Electronics & Communication
Engineering.
  To train our students to think independently in terms to master systematic approach to problem solving.
 To have a keen awareness of the role of engineering in the modern society.

DC:

1. An ability to model, simulate and design

Electronics and Communication Engineering
systems, conduct experiments, as well as
Co1
analyze and interpret data and prepare a
report with conclusions.

2. A knowledge of contemporary issues

involved in the practice of Electronics and
Co2
Communication Engineering profession

3. An ability to use modern Electronic Design

Automation (EDA) tools, software and
electronic equipment to analyze, synthesize
Co3 and evaluate Electronics and Communication
Engineering systems for multidisciplinary
tasks.

Apply engineering and project management

Co4 principles to one's own work and also to manage
projects of multidisciplinary nature

Lab Course Outcomes

INSTRUCTIONS / Do’s and Don’t

Instruction to Students:-
1. Do not handle any equipment without reading the instructions /Instruction manuals.
2. Observe type of sockets of equipment power to avoid mechanical damage.
3. Do not insert connectors forcefully in the Sockets.
4. Strictly observe the instructions given by the Teacher/ Lab Instructor.
5. After the experiment is over, the students must hand over the Bread board, Trainer kits, wires,
CRO Probes and other Components to the lab assistant / teacher.
6. It is mandatory to come to lab in a formal dress (Shirts, Trousers, ID card, and Shoes for
boys). Strictly NO Jeans for both Girls and Boys
7. It is mandatory to come with observation book and lab record in which previous experiment
should be written in Record and the present lab‘s experiment in Observation book.
8. Observation book of the present lab experiment should be get corrected on the same day and
Record should be corrected on the next scheduled lab session.
9. Mobile Phones should be Switched OFF in the lab session.
10. Students have to come to lab in-time. Late comers are not allowed to enter the lab.
11. Prepare for the viva questions. At the end of the experiment, the lab faculty will ask the viva
Questions and marks are allotted accordingly.
12. Bring all the required stationery like graph sheets, pencil & eraser, different color pens etc.
for the lab class.

Instructions to Laboratory Teachers:-

1. Observation book and lab records submitted for the lab work are to be checked and signed
before the next lab session.
2. Students should be instructed to switch ON the power supply after the connections are
checked by the lab assistant / teacher.
3. The promptness of submission should be strictly insisted by awarding the marks accordingly.
4. Ask viva questions at the end of the experiment.
5. Do not allow students who come late to the lab class.
6. Encourage the students to do the experiments innovatively.

List of Experiments

Experiment/ NAME OF PROGRAM PAGE NO

week
1 Common Emitter Amplifier.
 Common Source Amplifier

Two stages RC coupled Amplifier.

2
Current shunt and Voltage series Feed-back Amplifier

3 Cascode Amplifier.
Wien Bridge Oscillator using Transistors

4 RC Phase shift Oscillator using Transistor.

Class A Power Amplifier (Transformer Less)

5 RC Phase shift Oscillator using Transistor.
Class A Power Amplifier (Transformer Less)

6 Class B Complementary Symmetry Amplifier.

Common Base (BJT)/ Common Gate (JFET) Amplifier.

7 Class A Power Amplifier(With Transformer Load).

Class C power Amplifier

8 Single Tuned voltage Amplifier.

Hartley & Colpitt’s oscillator

9 Darlington pair.
MOS Common Source Amplifier.

10 LINEAR WAVE SHAPIN

11 NON-LINEAR WAVE SHAPING CIRCUITS
12 COMPARISON OPERATION OF COMPARATORS
TRANSISTOR AS A SWITCH
14 BISTABLE MULTIVIBRATOR
ASTABLE MULTIVIBRATOR
15 MONOSTABLE MULTIVIBRATOR
SCHMITT TRIGGER
16 UJT RELAXATION OSCILLATOR
BOOT STRAP SWEEP GENERATOR
17 MILLER SWEEP CUIRCUITS
Week-1

EXPT NO: 1

COMMON EMITTER AMPLIFIER

PRELAB:

1.Study the operation and working principle of CE amplifier.

2.Identify all the formulae you will need in this Lab.
3.Study the procedure of using Multisim tool (Schematic & Circuit File).
4.In this lab you will use “decibels”, or dB. This is a dimensionless ratio, in logarithmic
form.
Calculate the following:
a. The gain in dB of an amplifier with a gain of 10,000.
b. The gain in dB of an amplifier with a gain of 0.1.
c. The voltage ratio that corresponds to – 3 dB.
OBJECTIVE:
1. To simulate the Common Emitter amplifier in Multisim and study the transient and
frequency response.
2. Obtain the frequency response characteristics of CE amplifier by hardware
implementation.
3. To determine the phase relationship between the input and output voltages by
performing the transient analysis.
4. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies and
bandwidth of CE amplifier by performing the AC analysis.
5. Determine the effects of input signal frequency on capacitor coupled common
emitter amplifier

SOFTWARE TOOL:
Multisim

APPARATUS:
1. Regulated power supply (12V) - 1 No.
2. Function generator - 1 no.
3. CRO - 1 No.
4. Transistor (BC 107 or 2N2222) - 1 No.
5. Resistors (5KΩ,47 KΩ,2 KΩ, ,1 KΩ) - 1 No. each
6. Resistor (10 KΩ) - 2 Nos.
 7. Capacitors (10 µF, 1 µF) - 1,2 No. each
8. Bread Board - 1 No.
9. Connecting wires

Circuit Diagram

VCC
12 V

R1 RC
47kΩ 10kΩ
C2
RS
Q2 1µF
C1

1kΩ 1µF RL
2N2222A 10kΩ
Vin R2
0.02 Vpk 5kΩ
1kHz
0° RE CE
2kΩ 10µF

Fig: Common Emitter Amplifier

THEORY:
The practical circuit of CE amplifier is shown in the figure. It consists of different circuit
components. The functions of these components are as follows:
1. Biasing Circuit: The resistances R1, R2 and RE form the voltage divider biasing circuit
for the CE amplifier. It sets the proper operating point for the CE amplifier.
2. Input capacitor C1: This capacitor couples the signal to the transistor. It blocks any dc
component present in the signal and passes only ac signal for amplification. Because of
this, biasing conditions are maintained constant.
3. Emitter Bypass Capacitor CE: An emitter bypass capacitor CE is connected in parallel
with the emitter resistance, RE to provide a low reactance path to the amplified ac signal.
If it is not inserted, the amplified ac signal passing through RE will cause a voltage drop
across it. This will reduce the output voltage, reducing the gain of the amplifier.
4. Output Coupling Capacitor C2: The coupling capacitor C2 couples the output of the
amplifier to the load or to the next stage of the amplifier. It blocks DC and passes only
AC part of the amplified signal.
OPERATION:

When positive half of the signal is applied, the voltage between base and emitter (V be) is
increased because it is already positive with respect to ground. So forward bias is increased i.e.,
the base current is increased. Due to transistor action, the collector current I C is increased times.
When this current flows through RC the drop IC RC increases considerably. As a consequence of
this, the voltage between collector and emitter (Vce) decreases. In this way, amplified voltage
appears across RC). Therefore the positive going input signal appears as a negative going output
signal i.e., there is a phase shift of 180° between the input and output.

PROCEDURE:

1. Open Multisim Software to design Common Emitter amplifier circuit

2. Select on New editor window and place the required component on the circuit
window.
3. Make the connections using wire and set oscillator (FG) frequency & amplitude.
4. Check the connections and the specification of components value properly.
5. Go for simulation using Run Key observe the output waveforms on CRO
6. Indicate the node names and go for AC Analysis with the output node
7. Observe the Ac Analysis and draw the magnitude response curve
8. Calculate the bandwidth of the amplifier
OBSERVATIONS/GRAPS:

TRANSIENT RESPONSE:

FREQUENCY RESPONSE
 Value
S. No. Parameter

1 Max. Absolute Gain 17.54

2 Max. Gain in dB 41.32
3 3dB Gain 8.77
4 Lower Cutoff Frequency 93.216
5 Upper Cutoff Frequency 2.445
6 Bandwidth 90.771

RESULT:
Henc By Using software we have simulated transient and frequency response of common
emitter amplifier

Week-1:
EXPT NO: 2

COMMON SOURCE AMPLIFIE

PRELAB:

1. Study the operation and working principle of CS amplifier.

2. Identify all the formulae you will need in this Lab.
3. Study the procedure of using Multisim (Schematic & Circuit File).

OBJECTIVE:

1. To simulate the Common Source amplifier in Multisim and study the transient and frequency
response.
2. Obtain the frequency response characteristics of CS amplifier by hardware implementation.
3. To determine the phase relationship between the input and output voltages by performing the
transient analysis.
4. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies and bandwidth
of CS amplifier by performing the AC analysis.
5. Determine the effects of input signal frequency on Common Source amplifiers
SOFTWARE
TOOL:
Multisi
m

APPARATUS:
Regulated power supply =1 no
Function generator =1 no
CRO =1 no
FET(BFW 10). =1 no
Resistors(2.2MΩ,10KΩ,4.7KΩ,470Ω =1 no
Capacitor(100µf,10 µf) =1 no
Breadboard. =1 no

CIRCUIT DIAGRAM:

VDD
15 V

RD
4.7kΩ C2

Q1
10µF
R1 C1
RL
10kΩ 10µF 2N3370 1kΩ

Vin
50mVpk Rg RS
1kHz 2.2MΩ 470Ω
0°

Fig: Common Source Amplifier circuit Diagram

THEORY:

In Common Source Amplifier Circuit Source terminal is common to both the input and
output terminals. In this Circuit input is applied between Gate and Source and the output is
taken from Drain and the source. JFET amplifiers provide an excellent voltage gain with the
added advantage of high input impedance and other characteristics JFETs are often preferred
over BJTs for certain types of applications. The CS amplifier of JFET is analogous to CE
amplifier of BJT.

PROCEDURE:

1. Open Multisim Software to design FET common source amplifier circuit

2. Select on New editor window and place the required component CS amplifier on the
circuit window.
3. Make the connections using wire and check the connections and oscillator.
4. Go for simulation and using Run Key observe the output waveforms on CRO
5. Indicate the node names and go for AC Analysis with the output node
6. Observe the Transient response , Ac Analysis and draw the magnitude response curve
7. Calculate the bandwidth of the amplifier

Expected Graphs:
OBSERVATIONS / GRAPHS:
TRANSIENT RESPONSE:

FREQUENCY RESPONSE
INFERENCE:

S. No. Parameter Value

1 Max. Absolute Gain 10.44
10log2(10.44)=33.
2 Max. Gain in dB 84
3 3dB Gain 5.22

4 Lower Cutoff Frequency 1.688

5 Upper Cutoff Frequency 32.02
6 Bandwidth 30.338

RESULT:
By Using software we have simulated transient and frequency response of common emitter
amplifier

Week-2:
EXPT NO: 3

TWO STAGE RC COUPLED AMPLIFIER

PRELAB:

1.Study the purpose of using multistage amplifiers.

2. Learn the different types of coupling methods.
3. Study the effect of cascading on Bandwidth.
4. Identify all the formulae you will need in this Lab.
5. Study the procedure of using Multisim tool (Schematic & Circuit File).

OBJECTIVE:

1. To simulate the Two Stage RC Coupled Amplifier in Multisim and study the transient
and frequency response.
2. To determine the phase relationship between the input and output voltages by
performing the transient analysis.
3. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies and
bandwidth of Two Stage RC Coupled Amplifier by performing the AC analysis.
4. To determine the effect of cascading on gain and bandwidth.
SOFTWARE TOOL:

Multisim

APPARATUS:

1.Regulated power supply - 1 No.

1
. 2. Function generator - 1 No.
2
. 3. CRO - 1 No.
3
. 4. Transistor (BC 107 or 2N2222) - 2 No.
4
. 5. Resistors (5KΩ,47 KΩ,2 KΩ, ,1 KΩ) - 2 No. each
5
. 6. Resistor (10 KΩ) - 4 Nos.
6
. 7. Capacitors (10 µF, 1 µF) - 2,3No. each
7

CIRCUIT DIAGRAM:

VCC
12V

R2
R5 R8
22kΩ
R4 10kΩ 1kΩ
150kΩ C2 C5 XSC1

10µF Q2 10µF CRO out put

Q1 Ext Trig
C1 +
R3 _
A B
_ _
V10kΩ 10µF BC107BP + +
BC107BP R1
R9
50mVrms 220Ω
1kHz R6 5.6kΩ
0° 22kΩ C4
R7 C3 R10
100µF
220Ω 100µF 220Ω

Fig: Two Stage RC Coupled Amplifier Circuit Diagram 3.a

THEORY:

An amplifier is the basic building block of most electronic systems. Just as one brick does
not make a house, a single-stage amplifier is not sufficient to build a practical electronic system.
The gain of the single stage is not sufficient for practical applications. The voltage level of a
signal can be raised to the desired level if we use more than one stage. When a number of
amplifier stages are used in succession (one after the other) it is called a multistage amplifier or a
cascade amplifier. Much higher gains can be obtained from the multi-stage amplifiers. In a multi-
stage amplifier, the output of one stage makes the input of the next stage. We must use a suitable
coupling network between two stages so that a minimum loss of voltage occurs when the signal
passes through this network to the next stage. Also, the dc voltage at the output of one stage
should not be permitted to go to the input of the next. If it does, the biasing conditions of the next
stage are disturbed.
Figure shows how to couple two stages of amplifiers using RC coupling scheme. This is
the most widely used method. In this scheme, the signal developed across the collector resistor
RC (R2)of the first stage is coupled to the base of the second stage through the capacitor CC.
(C2) The coupling capacitor blocks the dc voltage of the first stage from reaching the base of the
second stage. In this way, the dc biasing of the next stage is not interfered with. For this reason,
the capacitor CC (C2)is also called a blocking capacitor.
As the number of stages increases, the gain increases and the bandwidth decreases.
RC coupling scheme finds applications in almost all audio small-signal amplifiers used in record
players, tape recorders, public-address systems, radio receivers, television receivers, etc.

PROCEDURE:

1. Open Multisim Software to design Two stage RC coupled amplifier circuit

2. Select on New editor window and place the required component CS amplifier on the
circuit window.
3. Make the connections using wire and check the connections and oscillator.
4. Go for simulation and using Run Key observe the output waveforms on CRO
5. Indicate the node names and go for AC Analysis with the output node
6. Observe the Transient response and Ac Analysis for the first stage and second stage
separately and draw the magnitude response curve
7. Calculate the bandwidth of the amplifier
OBSERVATIONS/GRAPHS:

TRANSIENT RESPONSE:

FREQUENCY RESPONSE:
INFERENCE:

1. From the transient analysis, it is observed that,___________________________

2. From the frequency response curve the following results are calculated:
3. From the AC response, it is observed that, _____________________________

S. No. Parameter Value

1 Max. Gain in dB 15.520
2 3dB Gain 15.520/2=7.716
3 Lower Cutoff Frequency 1.6048
4 Upper Cutoff Frequency 485.273
5 Bandwidth 483.6682

RESULT:Hence two stage RC-coupled amplifies charactiristics plotted and calculated the gain.

Week-2:

EXPT NO 4

CURRENT SHUNT AND VOLTAGE SERIES FEEDBACK AMPLIFIER

PRELAB:
1. Study the concept of feedback in amplifiers.
2. Study the characteristics of current shunt feedbackamplifier.
3. Identify all the formulae you will need in thisLab.
4. Study the procedure of using Spice tool (Schematic & Circuit File).
OBJECTIVE:
1. To simulate the Current Shunt Feedback Amplifier inPSpice and study the transient
and frequency response.
2. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies
and bandwidth of Current Shunt Feedback Amplifier by performing the AC analysis.
3. To determine the effect of feedback on gain and bandwidth.
SOFTWARE TOOL:
EdwinXP / Topspice / Multisim / Microsim / or any other equivalent tool.
CIRUIT DIAGRAM:

THEORY:
Feedback plays a very important role in electronic circuits and the basic
parameters, such as input impedance, output impedance, current and voltage gain and
bandwidth, may be altered considerably by the use of feedback for a given amplifier. A portion
of the output signal is taken from the output of the amplifier and is combined with the normal
input signal and thereby the feedback is accomplished.

There are two types of feedback. They are i) Positive feedback and ii) Negative
feedback. Negative feedback helps to increase the bandwidth, decrease gain, distortion,
and noise, modify input and output resistances as desired.

A current shunt feedback amplifier circuit is illustrated in the figure. It is called a series derived,
shunt-feedback. The shunt connection at the input reduces the input resistance and the
series connection at the output increases the output resistance. This is a true current
amplifier.
PROCEDURE:

1. Open Multisim Software to design Common Base amplifier circuit

2. Select on New editor window and place the required component on the circuit
window.
3. Make the connections using wire and set oscillator (FG) frequency & amplitude.
4. Check the connections and the specification of components value properly.
5. Go for simulation using Run Key observe the output waveforms on CRO
6. Indicate the node names and go for AC Analysis with the output node
7. Observe the Ac Analysis and draw the magnitude response curve
8. Calculate the bandwidth of the amplifier

EXPECTED GRAPHS:
OBSERVATIONS:
1.From the frequency response curve the following results are calculated:

S.No Parameter Values

1 Max.Gain in db -1.6db/-1.10db
2 3db Gain -4.6db/-4db
3 Lower Cutoff Frequency 404KHZ/1HZ
4 Upper Cutoff Frequency 13.2MHZ/206HZ
5 Band width 13.23MHZ/205HZ

2. From the AC response, it is observed that, ____The current has been increasing

RESULT:
Hence current and voltage series feer back amplifiers graph plotted and gain
calculated.

Week-3:
EXPT NO 5

CASCODE AMPLIFIER

PRELAB:

1. Study the operation and working principle of Cascode amplifier.

2. Identify all the formulae you will need in this Lab.
3. Study the procedure of using Multisim tool (Schematic & Circuit File).

OBJECTIVE:
1. To simulate the Cascode amplifier in Multisim and study the transient and
frequency response.
2. Obtain the frequency response characteristics of Cascode amplifier by hardware
implementation.
3. To determine the phase relationship between the input and output voltages by
performing the transient analysis.
4. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies
and bandwidth of CB amplifier by performing the AC analysis.
5. Determine the effects of input signal frequency on common Base. amplifiers

SOFTWARE TOOL:
Multisim.
APPARATUS:
1. Regulated power supply - 1 No.
 2. Function generator - 1 No.
3. CRO - 1 No.
4. Transistor (BC 107 or 2N2222) - 1 No.
5. Resistors (20KΩ) - 1 No.
6. Resistor (10 KΩ) - 2 Nos.
7. Capacitors (10 µF,) - 2 Nos.
8. Bread Board - 1 No.
9. Connecting wires

CIRCUIT DIAGRAM:

THEORY:
While the C-B (common-base) amplifier is known for wider bandwidth than the C-E
(common-emitter) configuration, the low input impedance (10s of Ω) of C-B is a limitation for
many applications. The solution is to precede the C-B stage by a low gain C-E stage which has
moderately high input impedance (kΩs). The stages are in a cascode configuration, stacked in
series, as opposed to cascaded for a standard amplifier chain. See “Capacitor coupled three stage
common-emitter amplifier” Capacitor coupled for a cascade example. The cascode amplifier
configuration has both wide bandwidth and a moderately high input impedance.

PROCEDURE:
1. Open Multisim Software to design Common Base amplifier circuit
2. Select on New editor window and place the required component on the circuit
window.
3. Make the connections using wire and set oscillator (FG) frequency & amplitude.
4. Check the connections and the specification of components value properly.
5. Go for simulation using Run Key observe the output waveforms on CRO
6. Indicate the node names and go for AC Analysis with the output node
7. Observe the Ac Analysis and draw the magnitude response curve
8. Calculate the bandwidth of the amplifier

OBSERVATIONS:
1.From the frequency response curve the following results are calculated:

S.No Parameter Values

1 Max.Gain in db 22db
2 3db Gain 19DB
3 Lower Cutoff Frequency 391.37HZ
4 Upper Cutoff Frequency 1.96MHZ
5 Band width 1.96MHZ

EXPECTED GRAPHS:
RESULT:

Hence cascade amplifiers transient& Frequency response ploted and gain calculated.

Week-3;

EXPT NO: 6

WIEN BRIDGE OSCILLATOR USING TRANSISTORS

PRELAB

1. Study the operation and working principle of Wien bridge oscillator

2. Identify all the formulae you will need in this Lab.
3. Study the procedure of using Multisim tool (Schematic & Circuit File

OBJECTIVE:

a. To simulate the Common Base amplifier in Multisim and study the transient and
frequency response.
b. Obtain the frequency response characteristics of wien bridge by hardware
implementation.
c. To determine the phase relationship between the input and output voltages by
performing the transient analysis.
d. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies
and bandwidth of CB amplifier by performing the AC analysis.
e. Determine the effects of input signal frequency on common Base. amplifiers

SOFTWARE TOOL:
Multisi
CIRCUIT DIAGRAM:

THEORY:
The wein bridge oscillator is a standard circuit for generating low frequencies in the
range of 10 Hz to about 1MHz.The method used for getting +ve feedback in wein bridge
oscillator is to use two stages of an RC-coupled amplifier. Since one stage of the RC-coupled
amplifier introduces a phase shift of 180 deg, two stages will introduces a phase shift of 360
deg. At the frequency of oscillations f the +ve feedback network shown in fig makes the input
& output in the phase. The frequency of oscillations is given as

f =1/2π√R1C1R2C2Ω
In addition to the positive feedback

PROCEDURE:
1. Open Multisim Software to design Common Base amplifier circuit
2. Select on New editor window and place the required component on the circuit
window.
3. Make the connections using wire and set oscillator (FG) frequency & amplitude.
4. Check the connections and the specification of components value properly.
5. Go for simulation using Run Key observe the output waveforms on CRO
6. Indicate the node names and go for AC Analysis with the output node
 7. Observe the Ac Analysis and draw the magnitude response curve
8. Calculate the bandwidth of the amplifier

OBSERVATIONS:

1
f=
2 π √ R 1 R 3C 6 C 8
WERE R1=2.2kΩ
R2=22 kΩ
C6=c8=1.5nf
Theoretical frequency=15.25KHZ

Practical frequency=1/T=14.88KHZ
Were T=67.164.31µs

EXPECTED GRAPHS:

RESULTS:

Hence wine bridge oscillator graph plotted and compared theoretical & practical
frequency calculated.
Week-4:
EXPT NO: 7
RC PHASE SHIFT OSCILLATOR
PRELAB:

1. Study the different types of oscillator and their conditions.

2. Identify all the formulae you will need in this Lab.
OBJECTIVE:

1. To simulate RC phase shift oscillator in Multisim and study the transient response.
2. To determine the phase shift of RC network in the circuit.
SOFTWARE TOOL:
Multisim
APPARATUS:
1. Regulated power supply - 1 No.
2. Function generator - 1 No.
3. CRO - 1 No.
4. Transistor (BC 107 or 2N2222) - 2 No.
5. Resistors (47 KΩ, 2.2 KΩ, 1k) - 1 No. each
6. Resistor (10 KΩ) - 3 Nos.
7. Capacitors (10 µF, 100 µF) - 1No. each
(1nf,or 10nf) - 3 No.
CIRCUIT DIAGRAM:

VCC
12V

R5
R4 2.2kΩ XSC1
47kΩ C2
Ext Trig
+
10µF _
Q1 A B
C5 C4 C1 + _ + _

1nF 1nF 1nF

BC107BP

R3 R6
R2
10kΩ 10kΩ
10kΩ R7 C3
1kΩ 100µF

Fig: RC Phase Shift oscillator7.a

PROCEDURE:

1. Open Multisim Software to design RC Phase shift oscillator

2. Select on New editor window and place the required component on the circuit window.
3. Make the connections using wire and check the connections and oscillator.
4. Go for simulation and using Run Key observe the output waveforms on CRO
5. Observe the Transient Response and Calculate the Frequency of the oscillator

OBSERVATIONS:

Theoretical frequency :

1
f=
2 πRC √ 6+ 4 k
Were R=10KΩ
C=1nf
K=00.22
F=6.06KHZ

Practical frequency:
T=162.2µs
F=1/T=6.16KHZ
OBSERVATIONS/GRAPHS:

TRANSIENT RESPONSE:

EXERCISE: 1.Design RC Phase shift oscillator using FET and different design values 2.
Design a PCB layout for RC Phase shift oscillator.
RESULT:
Hence RC-phase shift oscillator graph plotted & compared theoretical frequencies.
EXPT NO: 8

CLASS A POWER AMPLIFIER (Transformer less)

PRELAB:

1. Study the operation and working principle of CLASS A Power Amplifier.

2. Identify all the formulae you will need in this Lab.
3. Study the procedure of using Multisim tool (Schematic & Circuit File).

OBJECTIVE:

1. To simulate the Common Base amplifier in Multisim and study the transient and
frequency response.
2. Obtain the frequency response characteristics of CB amplifier by hardware
implementation.
3. To determine the phase relationship between the input and output voltages by performing
the transient analysis.
4. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies and
bandwidth of CB amplifier by performing the AC analysis.
5. Determine the effects of input signal frequency on common Base. amplifiers

SOFTWARE TOOL:
Multi sim
APPARATUS:

1. Regulated power supply - 1 No.

2. Function generator - 1 No.
3. CRO - 1 No.
4. Transistor (BC 107 or 2N2222) - 1 No.
5. Resistors (20KΩ) - 1 No.
6. Resistor (10 KΩ) - 2 Nos.
7. Capacitors (10 µF,) - 2 Nos.
8. Bread Board - 1 No.
9. Connecting wires

CIRCUIT DIAGRAM:
THEORY:
Class A power amplifier is one in which the output current flows during the entire
cycle (360°) of input signal. Thus the operating point is selected in such a way that the
transistor operates only over the linear region of its load line. So this amplifier can amplify input
signals of small amplitude.
The theoretical efficiency of transformer coupled or inductively coupled class
A power amplifier is 50%. Practically it is in the range of30 – 35%. The formula for calculating
collector efficiency is % 100.

ⴄ=Pac/Pdc
where Pac and Pdc values are calculated as follows:

PROCEDURE:
1. Open Multisim Software to design Common Base amplifier circuit
2. Select on New editor window and place the required component on the circuit
window.
3. Make the connections using wire and set oscillator (FG) frequency & amplitude.
4. Check the connections and the specification of components value properly.
5. Go for simulation using Run Key observe the output waveforms on CRO
6. Indicate the node names and go for AC Analysis with the output node
7. Observe the Ac Analysis and draw the magnitude response curve
8. Calculate the bandwidth of the amplifier
OBSERVATIONS:
V=15v
I=21.4mv
Pdc IC*VCC=00.26W;
RL=47Ω
2/
pac= vo 8RL

ᶯ=pac/pdc*100=23%

EXPECTED GRAPH:

RESULT:
Hence Transient and frequency response of class-A power amplifies ploted &efficiency
calculated.
Week-5:
EXPT NO: 9
CLASS B COMPLEMENTARY SYMMETRY AMPLIFIER
PRELAB:
1. Study the operation and working principle of Class B power amplifier.
2. Identify all the formulas you will need in this Lab.
3. Study the procedure of using Spice tool (Schematic & Circuit File).
OBJECTIVE:
1. To simulate the Common Source amplifier in Multisim and study the transient and frequency
response.
2. Obtain the frequency response characteristics of CS amplifier by hardware implementation.
3. To determine the phase relationship between the input and output voltages by performing the
transient analysis.
4. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies and
bandwidth of CS amplifier by performing the AC analysis.
5. Determine the effects of input signal frequency on Common Source amplifiers
SOFTWARE TOOL:
Multi Sim
APPARATUS:
1. Regulated power supply - 1 No.
2. Function generator - 1 No.
3. CRO - 1 No.
4. Transistor (BC 107 or 2N2222) - 1 No.
5. Resistors (20KΩ) - 1 No.
6. Resistor (10 KΩ) - 2 Nos.
7. Capacitors (10 µF,) - 2 Nos.
8. Bread Board - 1 No.
9. Connecting wires
CIRCUIT DIAGRAM:
THEORY:
The use of both the input and output transformers in an ordinary push-pull
amplifier circuit is eliminated using a circuit called complementary-symmetry push-pull
amplifier circuit.
This uses a pair of transistors having complementary symmetry, that is, one transistor is PNP and
the other is NPN.
Note that the complementary symmetry circuit requires two power supplies, since each
transistor must be biased suitably. The transistors T1 and T2 are operated in class-B.That is, the
bias is adjusted such that the operating point corresponds to the cut-off points. Hence, with
no signal input, both
transistors are cut-off and no collector current flows.
The signal applied at the input goes to the base of both the transistors. Since the
transistors are of opposite type, they conduct in opposite half-cycles of the input. For example,
during the positive half-cycle of the input signal, the PNP transistor T1 is reverse biased
and does not conduct. The NPN transistor T2, on the other hand, is forward-biased and
conducts.
This results in a half-cycle of output voltage across the load resistor. The other
half-cycle of output across the load is provided by the conduction of transistor T1 (the transistor
T2 remains cut-off) during the negative half-cycle of the input. Since the collector current
from each transistor flows through the load during the alternate half-cycles of the input signal,
no center tapped output transformer is required. The two transistors – though of opposite
type – must be matched. If there is an imbalance in the characteristics of the two
transistors, even harmonics will no longer be
Cancelled.
This would result in considerable distortion. Increasing availability of complementary
transistors is making the use of class-B transformer coupled stages obsolete. All modern power
amplifier circuits are transformer less and use complementary transistors.
PROCEDURE:
1. Open Multisim Software to design Class B power amplifier circuit
2. Select on New editor window and place the required component on the circuit
window.
3. Make the connections using wire and set oscillator (FG) frequency & amplitude.
4. Check the connections and the specification of components value properly.
5. Go for simulation using Run Key observe the output waveforms on CRO.
6. Indicate the node names and go for AC Analysis with the output node.
7. Observe the Ac Analysis and draw the magnitude response curve.
8. Calculate the bandwidth of the amplifier.

Observations:
Voltage =9.4v
I=8.3ma
Pdc=IRMS*2/π*Vdc=0.026w;
Rl=470Ω
Pac=Vo2 /8RL=0.02w;
ᶯ=pac/pdc*100=76%

EXPECTEDGRAPHS:

RESULTS:
Hence graph plotted of class-B complementary symmetry power amplifies and efficiency
calculated.

EXPT NO:10 (a)

COMMON BASE (BJT)AMPLIFIER

PRELAB:

1. Study the operation and working principle of CB amplifier.

2. Identify all the formulae you will need in this Lab.
3. Study the procedure of using Multisim tool (Schematic & Circuit File).

OBJECTIVE:
1. To simulate the Common Source amplifier in Multisim and study the transient and frequency
response.
2. Obtain the frequency response characteristics of CS amplifier by hardware implementation.
3. To determine the phase relationship between the input and output voltages by performing the
transient analysis.
4. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies and
bandwidth of CS amplifier by performing the AC analysis.
 5. Determine the effects of input signal frequency on Common Source amplifiers

SOFTWARE TOOL:
Multisim.

APPARATUS:
1. Regulated power supply - 1 No.
2. Function generator - 1 No.
3. CRO - 1 No.
4. Transistor (BC 107 or 2N2222) - 1 No.
5. Resistors (20KΩ) - 1 No.
6. Resistor (10 KΩ) - 2 Nos.
7. Capacitors (10 µF,) - 2 Nos.
8. Bread Board - 1 No.
9. Connecting wires
CIRCUIT DIAGRAM:

VEE VCC
12 V 12V

RE RC
20k? 10k?
C1 C2

Q1
10µF BC 107 10µF
Vin
10mVpk RL
1kHz 10k?
0°
THEORY:
In Common Base Amplifier Circuit Base terminal is common to both the input and
output terminals. In this Circuit input is applied between emitter and base and the output is taken
from collector and the base. As we know, the emitter current is greater than any other current in
the transistor, being the sum of base and collector currents i.e. IE= IB+ IC In the CE and CC
amplifier configurations, the signal source was connected to the base lead of the transistor, thus
handling the least current possible. Because the input current exceeds all other currents in the
circuit, including the output current, the current gain of this amplifier is actually less than 1
(notice how Rload is connected to the collector, thus carrying slightly less current than the signal
source). In other words, it attenuates current rather than amplifying it. With common-emitter and
common-collector amplifier configurations, the transistor parameter most closely associated
with gain was β. In the common-base circuit, we follow another basic transistor parameter: the
ratio between collector current and emitter current, which is a fraction always less than 1. This
fractional value for any transistor is called the alpha ratio, or α ratio.( α= IC/IE) Since it
obviously can't boost signal current, it only seems reasonable to expect it to boost signal voltage.

Operation:
The positive going Pulse of input Source increases the emitter voltage. As the base
voltage is Constant, the forward bias of emitter base junction reduces. This reduces IB,
reducing IC and hence the drop across RC since VO=VCC - IC RC, the reduction in IC results in an
increase in VO. Therefore, we can Say that positive going input produces positive going
output and similarly negative going input produces negative going output and there is no
phase shift between input and output in a common base amplifier

PROCEDURE:

Open Multisim Software to design Common Base amplifier circuit

1. Select on New editor window and place the required component on the circuit
window.
2. Make the connections using wire and set oscillator (FG) frequency & amplitude.
3. Check the connections and the specification of components value properly.
4. Go for simulation using Run Key observe the output waveforms on CRO
5. Indicate the node names and go for AC Analysis with the output node
6. Observe the Ac Analysis and draw the magnitude response curve
7. Calculate the bandwidth of the amplifier
OBSERVATIONS:

S. No. Parameter Value

2 Max. Gain in dB 19.7db
3 3dB Gain 16.7db
4 Lower Cutoff Frequency 16.05HZ
5 Upper Cutoff Frequency 5.36MHZ
6 Bandwidth 5.36MHZ

1. EXPECTED GRAPHS:
OBSERVATIONS /
GRAPHS:

TRANSIENT RESPONSE:

FREQUENCY RESPONSE:
RESULTS:

1. From the transient analysis the phase relationship between input and output voltage
signals is _____1800______ degrees.
2. From the frequency response curve the following results are calculated:

Hence Common base Amplifier graph plotted & compared theoretical frequencies.

EXPT NO: 10 (b)

COMMON GATE (JFET) AMPLIFIER

AIM: -
1. Plot the frequency response of a FET amplifier in common gate mode.
2. Calculate gain.
3. Calculate bandwidth.

COMPONENTS & EQUIPMENTS REQUIRED: -

S.No Device Range/Rating QTY

1. (a) DC supply voltage 12V 1
(b) FET BFW 11/2N4392 1
(c) Capacitors 1F 2
(d) Resistors 1K,10k,1.5K 1
2. Signal generator 0.1Hz-1MHz 1
3. CRO 0Hz-20MHz 1
4. Connecting wires 5A 4

CIRCUITDIAGRAM:
VDD
12V
R3
1.5kΩ
C1
XSC1
Q1 1µF
C2
Ext Trig
+
1µF BFW10 _
R2 A B
10kΩ + _ + _
XFG1
THEORY:
A common-gate amplifier is one of three basic single-stage field-effect transistor (FET)
amplifier topologies, typically used as a current buffer or voltage amplifier. In this circuit the
source terminal of the transistor serves as the input, the drain is the output and the gate is
connected to ground, or "common," hence its name. The analogous bipolar junction transistor
circuit is the common-base amplifier. his configuration is used less often than the common
source or source follower. It is useful in, for example, CMOS RF receivers, especially when
operating near the frequency limitations of the FETs; it is desirable because of the ease of
impedance matching and potentially has lower noise

PROCEDURE:

1. Open Multisim Software to design FET common source amplifier circuit

2. Select on New editor window and place the required component CS amplifier on the
circuit window.
3. Make the connections using wire and check the connections and oscillator.
4. Go for simulation and using Run Key observe the output waveforms on CRO
5. Indicate the node names and go for AC Analysis with the output node
6. Observe the Transient response , Ac Analysis and draw the magnitude response
curve
7. Calculate the bandwidth of the amplifier

RESULT :

Hence common gate (Jfet) amplifier

EXPT NO 11:

CLASS A POWER AMPLIFIER (WITH TRANSFORMER LOAD)

AIM: Plot the frequency response of Class a power amplifier with transformer load. Calculate gain,
band width.
APPARATUS REQUIRED:
S.No Device Range/Rating Qty
1. (a) DC supply voltage 12V 1
(b) BJT BC148 1
(c) Capacitors 10µF 2
1
6.8 kΩ,
(d) Resistors 470Ω,560Ω,10kΩ 1
1
2. Signal generator 0.1Hz-1MHz 1
3. CRO 0Hz-20MHz 1
4. Connecting wires 5A 4

CIRCUIT DIAGRAM:
THEORY:
Class A power amplifier is one in which the output current flows during the
entire cycle (360°) of input signal. Thus the operating point is selected in
such a way that the transistor operates only over the linear region of its load
line. So this amplifier can amplify input signals of small amplitude.
The theoretical efficiency of transformer coupled or inductively coupled
class A power amplifier is 50%. Practically it is in the range of30 – 35%. The
formula for calculating collector efficiency is % 100.

ⴄ=Pac/Pdc
where Pac and Pdc values are calculated as follows:

PROCEDURE:
1. Study the circuit provided on the front panel of the kit.
2. Connect the signal generator at the input terminals.
3. Connect the CRO at the output terminals.
4. Switch on the power supply.
5. Apply a sine wave I/P around of 1KHz, Adjust the amplitude so that
transist or should not enter in saturation.
6. Now increase I/P frequency Fi from 100 Hz to 200 KHz in suitable
steps, Observe & note the corresponding O/P voltage VO. Determine it‛s gain.
7. Plot the graph, frequency of I/P Fi VS gain. Determine its bandwidth.

EXPECTED GRAPHS:

RESULT:
EXPT NO 12
CLASS C POWER AMPLIFIER
AIM:
Plot the frequency response of a class C power Amplifier. Calculate gain. Calculate bandwidth.

APPARATUS REQUIRED:
S.No Device Range/Rating Qty
1. (a) DC supply voltage 12V 1
(b) BJT BC107 1
(c) Capacitors 10F 2
100F 1
220,22K,1k
(d) Resistors  1
(e) inductor (1mH) 5.6K,10k 1
2. Signal generator 0.1Hz-1MHz 1
3. CRO 0Hz-20MHz 1
4. Connecting wires 5A 4

CIRCUIT DIAGRAM:

THEORY: The use of both the input and output transformers in an ordinary push-pull
amplifier circuit is eliminated using a circuit called complementary-symmetry push-pull
amplifier circuit.
This uses a pair of transistors having complementary symmetry, that is, one transistor is PNP
and the other is NPN.
Note that the complementary symmetry circuit requires two power supplies, since each
transistor must be biased suitably. The transistors T1 and T2 are operated in class-B.That is,
the bias is adjusted such that the operating point corresponds to the cut-off points. Hence,
with no signal input, both
transistors are cut-off and no collector current flows.
The signal applied at the input goes to the base of both the transistors. Since the
transistors are of opposite type, they conduct in opposite half-cycles of the input. For example,
during the positive half-cycle of the input signal, the PNP transistor T1 is reverse
biased and does not conduct. The NPN transistor T2, on the other hand, is forward-
biased and conducts.
This results in a half-cycle of output voltage across the load resistor. The other half-
cycle of output across the load is provided by the conduction of transistor T1 (the transistor T2
remains cut-off) during the negative half-cycle of the input. Since the collector current
from each transistor flows through the load during the alternate half-cycles of the input signal,
no center tapped output transformer is required. The two transistors – though of opposite
type – must be matched. If there is an imbalance in the characteristics of the two
transistors, even harmonics will no longer be
cancelled. This would result in considerable distortion. Increasing availability of
complementary transistors is making the use of class-B transformer coupled stages obsolete.
All modern power amplifier circuits are transformerless and use complementary transistors.

PROCEDURE:
1. Study the circuit diagram provided on the front panel of the kit.
2. Connect the sine wave generator to the inpu t terminals.
3. Connect Dual Trace CRO at input & output side,
4. Switch ‘ON ‛ the power supply.
5. Apply a sine wave I/P from signal generator at I/P Vin of circuit.
6. Now keep the amplitude Vin constant. Vary the I/P frequency Fi from 100Hz to 200KHz in
steps. Observe & note the corresponding O/P voltage VO Calculate the voltage gain AV= VO/
Vi n.
7. Repeat step 6 for different frequencies.
8. Plot a graph between I/P frequency Fi(on X-axis) & voltage gain AV (on Y- axis). Find out
the bandwidth from graph.

Observations:
S.No Input frequency Output voltage Av =vo/vin
1 2KHZ
2 10KHZ
3 300KHZ
4 50KHZ

RESULT: Hence frequency response of class-C power amplifies is plotted and

gain was calculated.
EXPT NO: 13
SINGLE TUNED AMPLIFIER
AIM: -
Plot the frequency response of a single tuned amplifier. Calculate gain.
Calculate bandwidth.

COMPONENTS & EQUIPMENTS REQUIRED: -

S.No Device Range/Rating Qty

1. (a) DC supply voltage 12V 1
(b) BJT BC107 1
(c) Capacitors 10F 2
100F 1
220,22K,1k
(d) Resistors  1
(e) inductor (1mH) 5.6K,10k 1
2. Signal generator 0.1Hz-1MHz 1
3. CRO 0Hz-20MHz 1
4. Connecting wires 5A 4

CIRCUIT DIAGRAM:
VCC
12V

C2
L1
1nF
1mH
R2
22kΩ

C5

Q2 10µF CRO out put

R3

10kΩ
BC107BP
V1
R1
R9
50mVrms 1kΩ
60kHz 5.6kΩ
0° C4
R10
100µF
220Ω

Fig: Single Tuned amplifiercircuit12.b

PROCEDURE: -
1. Connect the circuit diagram as shown in figure.
2. Set the input signal amplitude in the function generator and observe an amplified
voltage at the output without distortion.
3 By keeping input signal voltage, say at 50mV, vary the input signal frequency from 0 to
1MHz in steps as shown in tabular column and note the corresponding output
voltages.

PRECAUTIONS:
1. Avoid loose connections and give proper input Voltage

TABULAR COLUMN:

Input = 50mV

Frequency Output Gain Gain

(in Hz) Voltage (Vo) Av=Vo/Vi (in dB) =
20log10(Vo/Vi)
20
40

RESULT: -
1. Frequency response of BJT amplifier is plotted.
2. Gain = _______dB (maximum).
3. Bandwidth= fH--fL = _________Hz.
EXPT NO:1 4 a
HARTLEY OSCILLATOR
AIM:
Find practical frequency of a Hartley oscillator and to compare it with theoretical frequency for L
= 10mH and C = 0.01F, 0.033F and 0.047F.
COMPONENTS AND EQUIPMENTS REQUIRED:
S.No Device Range/Rating Quantity

1 a) DC supply voltage 12V 1

b) Inductors 5mH 2
c) Capacitor 0.01F,0.022F;0.033F 1
0.047F 1
d) Resistor 1K,10K,47K 1
e) NPN Transistor BC 107 1
2 Cathode Ray Oscilloscope (0-20) MHz 1
3. BNC Connector 1
4 Connecting wires 5A 4

CIRCUIT DIAGRAM:

VCC
12V

R5
R4 5kΩ
100kΩ C2

100nF
CRO output
Q1
C1

100nF
BC107BP
L1
1mH R6
10kΩ
R7 C3
1kΩ 0.1µF
C4
.01µF
L2
1mH

Fig: Hartley oscillator circuit.13.b

PROCEDURE:

1. Connect the circuit as shown in figure.

2. With 0.1F capacitor and 20mH in the circuit and observe the waveform.
3. Time period of the waveform is to be noted and frequency is to be calculated by
the formula f = 1/T .
4. Now fix the capacitance to 0.033 F and 0.047F and calculate the frequency and
tabulate the readings as shown.
5. Find the theoretical frequency from the formula f = 1

2 LT C
Where LT = L1 + L2 = 5mH + 5mH = 10mH and compare theoretical and practical
values.

PRECAUTIONS:
No loose contacts at the junctions.

TABULATIONS:
S.No LT(mH) Theoretical Practical Vo (peak to
C (F) frequency frequency peak)
(KHz) (KHz)
1 10 0.01 2.9KHZ 2.8KHZ 0.12v
2 10 0.033 503.54HZ 476.1HZ 0.1requency2v
3 10 0.047 356.06HZ 434.78HZ 0.12v

1. For C = 0.01F, & LT = 10 mH;

Theoretical frequency = 2.9khz
2. Practical frequency=2.8khz

2. For C = 0.033F, & LT = 10 mH;

Theoretical frequency =503.54Hz
Practical frequency =476.1Hz
3. For C = 0.047F, & LTs = 10 mH;
Theoretical frequency =353.06HZ
Practical frequency =434.78HZ

RESULT: Hence the Hartley oscillator is designed and its practical frequency is compared
with theoritical frequency
EXPT NO:1 4 b
COLPITTS OSCILLATOR
AIM: Find practical frequency of Colpitt’s oscillator and to compare it with
theoretical
Frequency for L= 5mH and C= 0.001F, 0.0022F, 0.0033F
respectively.
COMPONENTS & EQIUPMENT REQUIRED: -

S.No Device Range/Rating Quantity

1 a) DC supply voltage 12V 1
b) Inductors 5mH 1
c) Capacitor 0.01F,0.01F,100F 1
d) Resistor 1K,10K,47K 1
e) NPN Transistor BC 107 1
2 Cathode Ray Oscilloscope (0-20) MHz 1
3. BNC Connector 1
4 Connecting wires 5A 4

CIRCUIT DIAGRAM:

VCC
12V

R5
R4 5kΩ
100kΩ C2

CRO output
100nF
Q1
C1

100nF
BC107BP
C4
0.1µF R6
L1 10kΩ
20mH R7 C3
1kΩ 0.1µF
C5
0.1µF

PROCEDURE:-
1. Connect the circuit as shown in the figure
2. Connect C2= 0.001Fin the circuit and observe the waveform.
3. Time period of the waveform is to be noted and frequency
should be calculated by the formula f=1/T
 4. Now, fix the capacitance to 0.002 F and then to 0.003 F and calculate
the
frequency and tabulate the reading as shown.
1
2 LC
5. Find theoretical frequency from the formula f= T

C1C2
Where CT  and compare theoretical and practical values.

C1 C2
PRECAUTIONS:-
1. No loose connections at the junctions.

TABULAR COLUMN:

S.NO L(mH) C1 (F) C2 (F) Theoretical Practical Vo(V)

Frequency Frequency Peak to
(KHz) (KHz) peak
1 1mH .1u 0.1u 71.2KHZ 6V
71..42KHZ
2 1mH 0.01u 0.1u 711.76HZ 714.28HZ 6V

For C=0.01F,
0.1uf & L= 1mH
Theoretical
frequency =71.2KHZ
Practical frequency
=71.42KHZ
For C=0.1F, 0.1uf
& L= 1mH
Theoretical
frequency
=711.76HZ
Practical frequency
=714.28HZ
RESULT: Hence the colpits oscillator is designed and its practical frequency is
compared with theoritical frequency
EXPT NO:15
DARLINGTON PAIR AMPLIFIER
AIM: -
To Plot the frequency response of a Darlington amplifier. Calculate gain.
Calculate bandwidth.

COMPONENTS & EQUIPMENTS REQUIRED: -

S.No Device Range/Rating Qty

1. (a) DC supply voltage 12V 1
(b) BJT BC547 2
(c) Capacitors 10F 2
22k,2.2K,1k
(d) Resistors  1
82K,390 1
2. Signal generator 0.1Hz-1MHz 1
3. CRO 0Hz-20MHz 1
4. Connecting wires 4

CIRCUIT DIAGRAM:

VCC
12V

R1
R4 2.2kΩ
82kΩ
C2

Q7 10µF CRO
C1
BC547C Q6
V1 10µF
R3
50mVpk R5 BC547C 1kΩ
1kHz 22kΩ
0°
R2
390Ω

51
PROCEDURE: -
1. Connect the circuit diagram as shown in figure. Set the RPS voltage at 12V and input signal
amplitude (sine wave) 50mV, 1 KHz in the function generator.
2. Feed the sine wave signal to the input of the amplifier and observe an amplified voltage at
the output without distortion.{ input at CH-1 & output at CH-2}
3. By keeping input signal voltage, constant 50mV, Select the Range switch of FG input signal
frequency from {10Hz to 1MHz} in steps. Note down the output Vo peak-to-peak amplitude of
signal for different frequencies in tabular column.
4. Calculate the Bandwidth from the plot of graph.

TABULAR FORM Vi=Input 50mV

Frequency Output Gain Gain

(in Hz) Voltage (Vo) Av=Vo/Vi (in dB) =
20log10(Vo/Vi)
20 37mv 0.74 -2.6
40 40 0.8 -927.36
80 43mv 0.86 -814.35
100 46mv 0.92 -641.72

OBSERVATIONS:
S. No. Parameter Value
2 Max. Gain in dB -537.1db
3 3dB Gain -540.1db
4 Lower Cutoff Frequency 550.5HZ
5 Upper Cutoff Frequency 52KHZ
6 Bandwidth 51.5KHZ

EXPECTED GRAPH:

Result:
Hence frequency response of Darlington amplifies plotted & gain, Bandwidth calculated.

52
EXPT NO:1 6

MOS COMMON SOURCE AMPLIFIER

AIM: -
1. Plot the frequency response of a FET amplifier in common source mode .
2. Calculate gain.
3. Calculate bandwidth.

COMPONENTS & EQUIPMENTS REQUIRED: -

S.No Device Range/Rating QTY

1. (a) DC supply voltage 12V 1
(b) FET BFW 11/2N4392 1
(c) Capacitors 10F 2
100F 1
(d) Resistors 100,470 1
4.7K,8.2k 1
2. Signal generator 0.1Hz-1MHz 1
3. CRO 0Hz-20MHz 1
4. Connecting wires 5A 4

CIRCUIT DIAGRAM:

VDD
12V

R4
4.7kΩ
C1

Q1 10µF CRO out put

R2 C2

R1
1kΩ
10µF BFW10 1.0kΩ
V1
C3
R3
R5 100µF
50mVrms 470Ω
1kHz 1MΩ
0°

Fig: Common Source Amplifier circuit Dig 2.b

53
PROCEDURE: -

1. Connect the circuit diagram as shown in figure.

2. Adjust input signal amplitude 50mV, 1 KHz in the function generator and observe an
amplified voltage at the output without distortion.
3. By keeping input signal voltage, say at 50mV; vary the input signal frequency from 10 to
1MHz in steps as shown in tabular column and note the corresponding
output voltages.

PRECAUTIONS:

1. Avoid loose connections and give proper input Voltage

TABULAR COLUMN: Input = 50mV

Frequency (in Hz) Output Voltage (Vo) Gain Av=Vo/Vi Gain(in dB) =20log10(Vo/Vi)

50 1.21V 24.2 23
100 1.66V 33.2 24.4
1K 1.67V 33.4 24.5

RESULT: -
1. Frequency response of FET Common source amplifier is plotted.
2. Gain = ____24.4___dB (maximum).
3. Bandwidth= fH--fL = _____36.4____Hz.

EXPECTED GRAPH:

54
EXPT NO:1 7
1. LINEAR WAVE SHAPING
Aim :

Design a RC LPF and HPF at various time constants and verify the responses for Square wave
input (choose C = 0.1µf, Vi = 4 VP-P, f = 10 K Hz).
Apparatus:

1. CRO
2. Signal Generator
3. Bread board
4. Capacitor (0.1µf)
5. Resistors (100Ω, 1KΩ, 10 KΩ)
6. Connecting wires.

Circuit Diagram:

HPF:

Design / Calculations:
a) RC = T

Given T = 1/10KHz = 0.1 mSec

R = 0.1x 10-3 / 0.1µf = 1 Kohms

-T/2RC
V1 = V / (1 + e )

V1| 

%tilt

55
 = 2.49 V
V
 1.51V
T
2 RC
1e
|
 V1  V1
T1 = T2 = T/2 V
2

= (2.49 – 1.51)/2 = 49%)

b) RC >> T

Choose RC = 10T = 1 mSec

103
R= 10K
0.1x10

The O/P waveform will be identical to I/P

T1 = T2 = T/2

56
c) RC << T

RC = 0.1 T

R= 0.1*104
1000.1*106

LPF:

a) RC = T
C = 0.1µf, R = 1KΩ

V T
2 RC
e −1

2
V2 = = 0.49V
T
2 RC
e +1

V1 = -0.49 V

57
b) RC >> T

R = 10 KΩ, C = 0.1 µf

V T
2 RC
e −1

V2 = 2 = 0.05V V1= 0.05v

T
2 RC
e +1

c) RC << T

R = 100Ω,

C = 0.1 µf

58
OBSERVATIONSFOR HIGH PASS RC CIRCUIT:

For R=100K Ω
i) Rc-High pass circit(RC≫T)

RC=10T
R=100KΩ,F=1KHZ
C=10/103*100*103 =0.1 µf

ii)Medium time constant;

RC=T
C=T/R
= C=1/103*100*103 =0.01 µf
iii) Short time constant;
RC≪t
RC=T/!)
C=T/10R
=10/10*103*100*103 =0.001 µf

Note:

Low Pass Filter allows the DC component of I/P signal and High Pass
Filter block the DC component of I/P Signal.

Procedure:

B) Connect the circuit as shown in figure (LPF / HPF)

C) Apply the Square wave input to this circuit (Vi = 4 VP-P, f = 10KHz)

59
 1. Observe the output waveform for (a) RC = T, (b) RC>>T, (c)
RC>>T
2. Verify the values with theoretical calculations
:
Precautions:

Use two CRO probes and observe I/P & O/P waveforms simultaneously
by putting CRO on DC modes.

Result:

LPF and HPF are designed at various time constants and the responses
for square wave input is observed & hence plotted.

60
EXPERMENT:18

2. NON-LINEAR WAVE SHAPING CIRCUITS

(a) CLIPPERS
Aim:

a) To study the clipping circuits using diodes.

b) To observe the transfer characteristics of all the clipping circuits in
CRO.
Apparatus:

 Signal Generator.
 Bread board
 Connecting patch cards.
 CRO
 DC power supply (dual)
 Resistors (1 K, 10K)
 Diodes (1N4007)
Theory:

Clipping circuits basically limit the amplitude of the input signal either
below or above certain voltage level. They are referred to as Voltage limiters,
Amplitude selectors or Slicers. A clipping circuit is one, in which a small
section of input waveform is missing or cut or truncated at the out put section.
Clipping circuits are classified based on the position of Diode.
1.Series Diode Clipper
2.Shunt Diode Clipper

Procedure:
1.Connect the circuit as shown in fig.1
2.In each case apply 10 VP-P, 1KHz Sine wave I/P using a signal generator.

O/P is taken across the load RL.

3.Observe the O/P waveform on the CRO and compare with I/P waveform.

4.Sketch the I/P as well as O/P waveforms and mark the numerical values.

5.Note the changes in the O/P due to variations in the reference voltage V R =
2V, 3V..

6.Obtain the transfer characteristics of Fig.1, by keeping CRO in X-Y mode.7.

Repeat the above steps for all the circuit.

61
Precautions:

1.Set the CRO O/P channel in DC mode always.

2.Observe the waveform simultaneously by keeping common ground.
3.See that there is no DC component in the I/P.
4.To find transfer characteristics apply input to the X-Channel, O/P to Y-
Channel, adjust the dot at the center of the screen when CRO is in X-Y
mode.
5.Both the channels must be in ground, then remove ground and plot the
transfer characteristics.

Circuit Diagram Input&Output Wave Forms

62
Circuit diagram O/P Wave Forms

63
64
Circuit Diagrams Transfer Characteristics

65
66
 Result:

Different types of clipping circuits have been studied and observed the
responses for various combinations of VR and clipping diodes.

(b) CLAMPERS

Aim:

To study the clamping circuits using diodes and capacitors.

Apparatus:

 Signal Generator.
 Bread board
 Connecting patch cards.
 CRO
 DC power supply (dual)
 Resistors ( 100 KΩ )
 Diodes (1N4007)
 Capacitor (0.1µf)

Theory:

Clamping circuits add a DC level to an AC signal. A clamper is also refer to as

DC restorer or DC re-inserter. The Clampers which clamp the given waveform ithe
above or below the reference level, which are known as positive or negative clamping
respectively.

Procedure:

1. Connect the circuit as shown in fig.1.

2. Apply a Sine wave of 10VP-P, 1KHz at the input terminals with the help of
Signal Generator.
3. Observe the I/P & O/P waveforms of CRO and plot the waveforms and mark
the values with VR = 2 V, 3V
4. O/P is taken across the load RL.
5. Repeat the above steps for all clamping circuits as shown .
6. waveforms are drawn assuming diode is ideal.

67
 Circuit diagram
I/P & O/P Wave Forms
Vi =5V

C1 -5V

10V V1 0.1uF V0
D1
7.07V_rms
1N4007GP
1000Hz 0.5V
0Deg -

-9.5V

C1

V0
V1 0.1uF R1
10V D1 9.5V
7.07V_rms 100kohm
1000Hz 1N4007GP 5V
0Deg

-0.5V

V0

C1

0.1uF D1
1N4007GP
V1
10V
7.07V_rms
1000Hz
0Deg V2
2V

68
Circuit diagram O/P Wave forms

Result:

Different types of clamping circuits are studied and observed the response for
different combinations of VR and diodes.

69
EXPERMENT:19

COMPARISON OPERATION OF COMPARATORS

AIM:

To compare the applied input signal with the reference voltages to the Comparator
Circuit.

APPARATUS:

l. Comparator Trainer Kit.

2. l MHz Function Generator Inc.

3. 20MHz C.R.O.

4. Connecting Patch chords.

CIRCUIT DIAGRAM:

70
PROCEDURE:

1. Connect the comparator circuit as shown in fig (1).

2. Connect the lMHz function generator to the input terminals. Apply 1V signal at non-
inverting terminals of the op amp IC741.

3. Connect the 20MHz C.R.O at the output terminals.

4. Keep 1V reference voltage at the Inverting terminal of the Op amp. When Vin is less than
the Var, then output voltage is at Vm because of the higher input voltage at negative
terminal. Therefore the output voltage is at logic low level

5. Now, Keep lV reference voltage. When an is less than the Vin, then the output voltage is at
+Vm because of the higher input voltage at positive terminal. Hence, the output voltage is at
logic high level.

6. Observe and record the output voltage and waveforms.

Wave Forms:

71
RESULT:

Applied input signal is compared with reference voltages and the corresponding
waveforms are noted.

72
EXPERMENT:20

TRANSISTOR AS A SWITCH
Aim:
Design Transistor to act as a Switch and verify the operation. Choose VCC = 10V, ICmax = 10 mA,
hfe = 50, VCESat = 0.2, Vin = 4Vp-p, VBESat = 0.6 V

Apparatus:

1. Transistor (BC 107).

2. Breadboard.
3. CRO.
4. Resistors (1K, 8.2K).
5. DC power supply.
6. Function Generator.
7. Connecting patch cards.
Theory:

When the I/P voltage Vi is negative or zero, transistor is cut-off and no current flows
through Rc hence V0 ≅ VCC when I/P Voltage Vi jumps to positive voltage, transistor will be
driven into saturation. Then

V0 = Vcc – ICRC ≅ VCESat

Design procedure:

When Q is ON
V  V
RC = CC CESat
I
C max

= (10-0.2) / 10 mA = 1K

IB ≥ICmax / hfe
≥ 10mA / 50

IB ≥0.2 mA

To keep transistor remain in ON, IB should be greater than

Ibmin = 0.2mA

Vin = IBRB + VBE Sat

2V = 0.2 mA RB + 0.6V

RB = 7 K (choose practical values as 8.2 K)

73
Circuit diagram:

Procedure:

1. Connect the circuit as shown in figure.

2. Apply the Square wave 4 Vp-p frequency of 1 KHz
3. Observe the waveforms at Collector and Base and plot it.

Precautions:

1. When you are measuring O/P waveform at collector and base, keep the CRO in DC mode.
2. When you are measuring VBE Sat, VCE Sat keep volts/div switch at either 0.2 or 0.5
position.
3. When you are applying the square wave see that there is no DC voltage in that. This can be
checked by CRO in either AC or DC mode, there should not be any jumps/distortion in waveform
on the screen.

OBSERVATIONS:

Td(delay time)=4µs

Ts(storage time)=5 µs

Tr(rise time)=6 µs

Tf(fall time)=4 µs

74
Expectedwaveforms:

Result:

Transistor as a switch has been designed and O/P waveforms are observed.

75
EXPERMENT:21

BISTABLE MULTIVIBRATOR
Aim:
Design the Bi-sta ble Multivibrator circuit and verify the operatio n.
Obtain the res olving time of Bi-stable Multivibrator an d verify theoretically.
Cho ose R1 = 10KΩ, C = 0.3µf, VCE Sat = 0.2V, ICma x = 15mA, VCC = 15V,
VBB = 15V, VB1 = -1.2V

Apparatus:

4. Resistors(1k,10k,100k)-5no’s,2no’s,2no’s.
5. Capacito rs(0.001µf,0.33µf)-2no’s,3no’s.
6. Diodes( 1N4007)-3no’s.
7. Transist ors(BC107)-2no’s.
8. Function Generator
9. Regulat ed Power Supply
10. CRO
11. Connecting wires.

Circuit diagram:

76
 A Bistable circuit is one which can exist indefinitely in either of two stable
states and which can be induced to make an abrupt transition from one state to the other
by means of external excitation. The Bistable circuit is also called as Bistable
multivibrator, Eccles jordon circuit, Trigger circuit, Scale-of-2 toggle circuit, Flip-Flop
& Binary.

A bistable multivibratior is used in a many digital operations such as counting and the
storing of binary information. It is also used in the generation and processing of pulse-
type waveform. They can be used to control digital circuits and as frequency dividers .
There are two outputs available which are complements of one another. i.e.
when one output is high the other is low and vice versa .
Design :
V −V
CC CESat
RC =
I
C max

RC = (15 – 0.2) / 15mA ≅ 1K

V R
Choose RC = −V BBR1 CESat 2

1K, VB1 = R1  R2  R1  R2

-1.2 = 15x10  0.2R2 ; R2 =100KΩ

10  R 2

fmax =
R1  R2 = 10 100K  55KHz
2CR R 2x0.3x10−6 x10Kx100K
1 2
Procedure:

1. Switch ON the system and observe for the power LED indication.
2. Apply two Square waves with same frequency or different frequency at
terminals T1 & T2. You may observe symmetrical or Asymmetrical square
waves respectively. Observe both I/P & O/P waveforms on CRO.
3. Set the I/P frequency at 500hz.
4. Until you get a 500Hz at the O/P, increase the trigger I/P amplitude, note
down the I/P amplitude, this is the minimum pulse step required for trigger
the bi-stable Multivibrator with the given circuit parameters.
5. Now slowly increase the frequency and at one particular frequency the circuit
does not respond and the output disappears. Just lesser than this frequency,
the circuit again responds, this is the maximum allowable frequency.
6. Sketch the O/P waveforms. Sample O/P waveforms are as shown in figure

Expected waveforms:

77
Result:

Bistable Multivibrator circuit is designed and output waveformsare

observed.

78
EXPERMENT:22

ASTABLE MULTIVIBRATOR
Aim:-
To desian Astable Multivibrator to generate a Square wave of 1KHz frequency.
Choose C = 1nf, 10nf, 100nf.

Apparatus :

1. Regulated DC Power supply - 1 no

2. CRO, - 1 no
Resistors (1K, 72K, 724K,
3. 7.2K) - each 2 no’s
4. Capacitors (0.1nf, 10nf ,100nf) - 3 no’s
5. Transistors (BC 107) - 2 no’s
Circuit diagram:

79
Expected waveforms:

Result :

An Astable Multivibrator is designed the waveforms are observed and verified

the results theoretically.

80
EXPERMENT:23
MONOSTABLE MULTIVIBRATOR

Aim :

To design a monostable multivibrator for the Pulse width of 0.03mSec.

Apparatus:

1. Resistors(10k,1k,43.2k,100k)-2no’s,2no’s,1no,1no.
2. Capacitors(0.047µf)-2no’s
3. Diodes(1N4007)-1no.
4. Transistors(BC107)-2no’s.
5. Function Generator.
6. CRO.
7. Regulated Power Supply.
8. Connecting wires.
Circuit diagram :

81
Theory:

The monostable circuit has one permanently stable and one quasi-stable state.
In the monostable configuration, a triggering signal is required to induce a transition
from the stable state to the quasi-stable state. The circuit remains in its quasi-stable
for a time equal to RC time constant of the circuit. It returns from the quasi-stable
state to its stable state without any external triggering pulse. It is also called as one-
shot a single-cycle, a single step circuit or a univibrator.

Design :

To design a monostable multivibrator for the Pulse width of 0.03mSec.

Choose ICmax = 15mA, VCC = 15V, VBB = 15V, R1 = 10K.

T =  ln 2

T = 0.69 RC

Choose C = 10nf

0.3 x 10-3Sec = 0.69 x R x 10 x 10-9

R = 43.47 K
V − V
RC = CC CESat
I
C max
RC = (15 – 0.2) / 15mA ≅ 1K

Minimum requirement of for more margin, given

| VB1| ≤ 0.1 VB1 = -1.185
V
CESat
R
VB −V BBR1 2
1 = R1  
R2 R1  R2
− 15R
-1.18 = 1  0.2R2 ; given R1 = 10K
R1  R 2
R2 = 100K

Theoretical calculations: R=56kπ,C=100nf

T(ON)=0.69RC
=0.69*56*103*100*10-9 =3.9msec

82
 F=1/T=1/3.9msec=0.256KHZ

Practical calculation : Tp=0.377KHZ

Procedure:

1.Switch ON the trainer kit and observe power indication.

2.Wire the circuit as shown in the circuit diagram.
3.Calculate the pulse width (T) of the Monostable O/P with the selected values of R
& C on the CRO. See that CRO is in DC mode.
4.electth triggering pulse such that the frequency is less than 1/T
5.Apply the triggering input to the circuit and to the CRO’s channel 1 . 6.Connect the
CRO channei-2 to the collector and base of the TransisterQ1&Q2..
7.Adjust the triggering pulse frequency to get stable pulse on the CRO and now
measure the pulse width and verify with the theoretical value.
Obtain waveforms at different points like VB1, VB2, VC1 & V
8.Repeat the experiment for different combinations of R & C (C = 1nf, 100nf).
Calculate R for same value of T = 0.3 mSec.
Expected Waveforms:

83
Result:

A collector coupled Monostable Multivinbrator is designed, the waveforms are observed and verified
the results theoretically.

84
EXPERMENT:24
SCHMITT TRIGGER
Aim:-
(a) To design the circuit of Schmitt trigger with UTP = 3V LTP = 1.5V ,V cc =
15V ,Rs = 1k,Rc2 = 3k,R1 = 15k R2 = 4.7k
(b) To Obtain the UTP and LTP values Practically and verify it theoretically
(c) To obtain square wave from the sine wave.
Apparatus:
1. Bread board
2. Function Generator
3. Regulated Power Supply
4. C.R.O
5. Connecting wires
6. Resistors(1k,3.3k,15k,2.2k,4.7k)-2no’s,1no.
7. Capacitors(10µf,1µf)-1no,1no.
8. Transistors(BC107)-2no’s.
Circuit diagram:

85
Procedure:-

(1) Connect the circuit as shown in Fig.

(2) Switch ON the supply.
(3) With Vi = 0V, measure the output voltage.
(4) Slowly increase the input voltage from 0V to maximum
and observe the output for the transition.
(5) Obtain the voltage at which the LOW to HIGH transition
is occurred and this is the UTP and now measure the input
voltage.
(6) Now, slowly decrease the input voltage and observe for the
HIGH to LOW transition at the output, the input voltage at
this point is called the LTP.
(7) Apply a sine wave input to the circuit.
(8) Observe the input and output waveforms on CRO.
(9) Vary the input frequency and comment on the results
obtained.
(10) Repeat the experiment with different R2.
(11) Verify the result theoretically.

Observations:-
With Re = 480ohms
DC AC
UTP = 2.9V UTP = 3V
LTP = 1.8V LTP = 2V
VH = UTP – LTP VH = UTP – LTP

Theoretical Calculations:
V1 calculation:

V
BE2 = 0.6V for Si
V
r1 = 0.5V
(=VBE at cut in)
V R
CC 2 R2 (RC1  R1 ) V
V’ = ; Rb = CC
= 12V
R  R1  R  R1 
C1 R2 C1 R2

V Re (hFE  1)
EN
= (V’ - VBE2) * Rb  Re (hFE  1)

86
 V1 = VEN + Vr1 (Accurate value)

V
1
= V’ - 0.1 v (approximate value)

V2 calculation:
R R  R2
a = 2
; R = C1 (R1 ) ;
R
R1  R 2 C1  R1  R2
1
h
Re’ = Re(1+ FE );

V2 = VBE1 + R e ' Rs / hFE (V’ - Vr2) VBE = 0.6V

aR Re' Vr = 0.5V
= V
(or) V2 BE1 + Re (V’ – Vr2) (approximately)
aR  Re

OBSERVATIONS:
The time period of waveform=1ms
The amplitude of square waveform=4.8V
VUTP=5.6V

VLTP=4.8V
VH= VUTP- VLTP=0.8V

Expected Waveforms

87
:

Result: Schmitt Trigger circuit has designed and the square wave is observed from
the sine wave.

88
EXPERMENT:25

UJT RELAXATION OSCILLATOR

Aim:-
To study the UJT relaxation oscillator.
Apparatus:-
(1) UJT (2N2646)
(2) Capacitor
(3) Resistors
(4) C.R.O
(5) Regulated Power Supply
(6) Bread board.

Theory:

The unijunction is a 3-terminal,semiconductor device with –

ve resistance characteristics.It constitute three terminals base 1 and base
2 and emitter.
A relaxation oscillator shown in fig.The circuit must be
relaxation biased for stable operation that is load line determined by v
and r must inserted in the input characteristics in the –ve resistance. The
resistors rb1 and rb2 are not essential to the ckt but are included because
the voltage level applied across these resistors may prove useful and the
capacitor C charges to peak voltage Vp the device turns ON and
capacitor discharges to the valley voltage Vv where upper cycle repeats
the Vc appears charging time T.

Procedure:-
(1) Connect the circuit as shown in Fig.
(2) Observe the waveforms emitter,base1,base2 on the CRO.
(3) Calculate the frequency of waveforms.
(4) Compare theoretical and practical frequencies.
(5) Observe the input and output waveforms on CRO.
(6) Plot the waveforms.
Circuit Diagram:

89
 Theoretical Values:
We have
Vb1=iRb1.
Vbb 12
But i= = =0.0082A
Rb1  Rb2 470  1k
Vbb 12
Vb1= * Rb1 = * 470 =3.84v
Rb1  Rb2 470  1k
Rb1
= *Vbb

Rb1  Rb2
Rb1 470
Intrinsic Standoff Ratio η= = =0.32.
Rb1  Rb 2470  1k
Emitter Voltage Ve= Vγ+Vb1
= 0.7+3.84=4.54v
1
f=
RC log(1/(1 − n))
1
=
33k * 0.1*10^−6 log(1/(1 − 0.32))

= 1.81kHz.

OBSERVATIONS:

ᶯ=Vp/Vbb
=8.5/12=0.70

T=RC log10(1/1-ᶯ)
9
=150*103*10*10-
=0.15msec
F=iT=1/0.15msec=6.6KHZ

Practical calculations:
Ts(sweep time)=30µs.
Tr(Reten time)=26µs.
T=Ts+Tr=290µs.

90
Model Waveforms:

Observations:-
Vb1 = 3.84v
η = 0.32
Ve = 4.54v
f = 1.81kHz.

Result: The UJT Relaxation Oscillator has studied.Theoretical values are

compared with the practical values.

91
EXPERMENT:26
BOOT STRAP SWEEP GENERATOR
Aim:-
To study the Boot Strap Sweep Generator.
Apparatus:-
(1) Transistors
(2) Capacitors
(3) Resistors
(4) C.R.O
(5) Regulated Power Supply
(6) Bread board.
(7) Connecting Wires
(8) Diode
Theory:

The transistor Q1 acts as ON-OFF switch, and the transistor Q2 is an emitter-

follower. The input vi is a pulse voltage, or rectangular wave. when the input signal vi is
positive, transistor Q1 becomes ON, there exist goes into saturation.
Therefore potential of point A,VA=Vce(sat).If Q1 is silicon transistor,Vce(sat)=0.3v.
Therefore VA=0.3v. Output Voltage Vo= VA-Vbe(Q2) (in active
region) = 0.3-0.6=-0.3v.
The emitter of Q2 is coupled to the collector of Q1 through the capacitor
Cb.Hence point B becomes –ve w.r.t. Vcc.Diode D readily conducts, with the result that
potential Vb=Vcc.When the i/p Vi goes – ve,Q1 becomes OFF.The potential of A rises.
This increases of voltage at A is transmitted to B through Q2 and capacitor Cb.The
result is that the potential of B also rises by the same amount. This is the principle of
bootstrap. Thus Vb rises from Vcc to (Vcc+VA).Let I denote the current through Rc1.
We have I=(Vb-VA)/Rc1=Vcc/Rc1,since Vb=Vcc+VA. Since both Vcc
and Rc1 are of fixed magnitude, the
ratio(Vcc/Rc1) is constant. Hence current I is of constant magnitude. From the circuit,
we have I=i1,since Q1 is now cut off and its collector current is zero. But i1=i2+i3.i3 is
the base current of Q2.
Since Q2 is an emitter follower, its i/p impedance is very very high and hence i3 is
practically zero.
Therefore i1=i2.But i1=I. i2=I,is a constant curren

Procedure:-
(1) Connect the circuit as shown in Fig.
(2) Observe the waveforms on the CRO.
(3) Observe the input and output waveforms on CRO.
(4) Plot the waveforms.

92
Circuit Diagram:

VCC
20V

D1
DIOD E_VIR TUA L
C2

R1 R2 0.0F
1k? 1k?

U2
U1
C1

0.001µF BD 135
BD 135
V1
C3
1kHz 0.001µF R3
5V 1k?

VEE
-12V
ModelWaveforms:

[Type text] Page 93

Observations:-
Ts=4µs
Tr=6 µs

Result: The Boot Strap Sweep Generator has studied.

[Type text] Page 94

EXPERMENT:27

MILLER SWEEP CUIRCUITS

AIM:-

To Study the operation of Miller sweep circuit.

Apparatus:

1.Trainer kit

2.Patch Cards

3.CRO

Theory:

The miller sweep circuit or miller integrator generator is a precise and linear ramp voltage using active devic
feedback, the effective time constant and supply voltage is enhanced.

Miller sweep circuit is the basic schematic of a widely used sawtooth generator. The amplifier acts to increas
thus, linearity is improved and the output amplitude is increased. As the integral of a step function is a ramp, it is ev
would provide a sawtooth output.

The feedback can be negetive voltage or current type. The circuit of miller sweep generator is drawn below.

Circuit Diagram

[Type text] Page 95

It uses a BJT,the switch shown in the fig. Is an idea] switch normally it is closed.

The transistor is in off condition. The timing capacitor is charged to a voltage Vcc via the resistor Rc and the

Procedure:

1. Connect the circuit as shown in figure

2. Apply the Square wave input to this circuit at switch point 5

3. Apply Frequency 1KHz to SOOKHz only

4. Observe the output waveform Sweep signal for different frequency

Precautions:

Use two CRO probes and observe I/P & 0/ P waveforms simultaneously by putting CRO. Don't exceed
input Frequency not more than 500KHz

Result:
Observed the input and output waveforms of the Miller sweep circuit.

[Type text] Page 96

EXPERIMENT NO.28
STUDY OF LOGIC GATES

OBJECTIVE: Verification of truth table of logic gates.

EQUIPMENT REQUIRED: Regulated power supply

COMPONENETS REQUIRED:

1. Bread Board
2. IC trainer Kit Patch cards
3. IC’s 7400, 7402,7404,7408,7432 & 7486
4. Connecting wires.

PRE-LAB: To study about the logic gates.

To study the data sheets of Ic’s
7400, 7402,7404,7408,7432 & 7486

CIRCUIT DIAGRAM:

TRUTH TABLE

THEORY:

[Type text] Page 97

In digital electronics, the binary digits 0 and 1 are represented by voltages LOW and
HIGH. This branch of electronics is mathematically supported by Boolean algebra. The
basic logic operations in this algebra are NOT, AND and OR. These logic operators are
binary as they work on two operands to specify the output.

PROCEDURE:

1. Connect the IC on the breadboard.

2. Give two input connections from the trainer kit as in its pin diagram.
3. Connect the ground & apply a dc signal of 5V from the external power supply.
4. Make the connections as per the pin diagram.
5. Switch on the power supply.
6. Apply one combination of inputs and verify the truth table of that IC for that input
combination.
7. Repeat this for all possible combinations.
8. For remaining IC’s repeat the steps from 1 to 7.

: Truth tables of logic gates are verified.

RESULT: Hence Verification of truth table of logic gates.

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