Birla Institute of Science and Technology, Hyderabad Campus
Analog and Digital VLSI Design, Part-A (CLOSED BOOK)
Max. Marks: 30 Max. Time: 75 Min
1. Each question carries 2 M 2. Answers should be accurate up to 2 decimal points.
3. Neglect Velocity saturation and other second order effects unless explicitly mentioned in the question paper
4. Assume wire delay as zero and Ignore clock skew
5. Zero marks will be awarded for overwriting
Name: ID No.:
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1. Consider a processor, which can operate in two different modes: (i) Mode-1: a high voltage mode (1V, 3GHz, α =1),
and (ii) Mode-2: a low voltage mode (0.75V, 2 GHz, α =1). Then (Dynamic power consumption)mode1 divided by
(Dynamic power consumption)mode2 is --------------------------------.
2. Assume that all the primary inputs are uncorrelated and uniformly distributed with input signal probabilities P A=1 =
PB=1 = PC=1 = PD=1 = ½. The transition probability (α0->1) of node F is---------------------
3. The Boolean logic equation for the stick diagram is ----------------------------
4. An enhacement type NMOS transistor has the following parameters V TO =0.8V, ɤ =0.2V1/2, λ =0.05 V-1, |2ØF|= |-2ØF|
=0.58V, µnCox = 20µA/ V2.When the transistor is biased with V G =2.8V, VD=5V, Vs=1V, VB =0V, the drain current is I D
=0.24mA. Then the value of W/L is -------------------.Consider body effect and channel length modulation.
5. A 10KΩ resistive load inverter circuit with a 1pF load is shown below. Given µ nCox = 25µA/ V2 , W/L =10, Vt = 1V.
Assume Vin = 5V and the NMOS is in linear mode of operation. Then the value of VOL is -------------------------V
6. The number of lines of the address bus must be used to access memory of 2048 words (each word is 8 bits wide) is
------------------------.
7. The Boolean function for the node D in the below circuit is ------------------------------------------------------------------------
8. The Boolean function for the node F in the below circuit is ------------------------------------
9. The Boolean function for the output O2 for the below circuit is -----------------------
10. The difference in the arrival time of a clock signal at two different registers is known as ----------------------------
11. For the circuit given below, the maximum clock frequency for reliable operation is ------------------------------ GHz.
NAND gate delay = 20ps, NOR gate delay =30ps, EXOR gate delay =50ps, NOT gate delay =15ps.
FF 1: tclk-q = 50ps, set up time = 30ps, hold time =10ps
FF 2: tclk-q = 35ps, set up time = 50ps, hold time =10ps
12. Given an 4*4 carry-save multiplier with tand = 3ps, tcarry = 10ps. Assume that the tmerge delay stage of carry save adder
is 4-bit wide. The tmerge stage is implemented using an adder that has a delay of log2M ps(where M is the width of
the tmerge adder) The critical path of an 4*4 carry-save multiplier is -------------------------------ps.
13. For the circuit shown below, (W/L)1 = 10, (W/L)2 = 100, (W/L)3 =1000, (W/L)4 =10. The node P is 4V w.r.t GND.
Neglect channel length modulation and assume Q2, Q3 and Q4 are in saturation. Then the value of I X is ---------- mA
14. A 1024-bit ripple carry adder with tsum = 3ps, tcarry = 10ps has a critical path equal to --------------------------------ps
15. A NMOS transistor node voltages VG= 1.5V, VD=1.8V, Vs= 0.7V, VB=0V. Consider the NMOS under bias has Vₜₒ= 0.3V,
W/L = 9.5/2, ɤ =0.27 V¹/², λ =0.1 V-1, |-2Øf| = |2Øf|=0.6V, µₙCₒₓ =299 µA/V². The value of current (ID) in µA through
the NMOS is -----------------------------------------------( Consider Body effect and channel length modulation)
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