Dr.

KVSR Institute of Technology

Dept.of Electrical and Electronics Engineering

VISION OF THE INSTITUTION:

To be a Global Leader in imparting Quality Technical Education to produce competent technically

innovative Engineers imbibed with Research aptitude, Entrepreneurship and Social responsibility.

VISION OF THE EEE DEPARTMENT

To strive towards excellence in electrical and Electronics engineering through teaching, experimental
learning and research to meet industrial and societal needs.

MISSION OF THE INSTITUTION

1. To nurture the students with fundamental engineering knowledge enriched with technical skills.

2. To create conducive environment to nurture innovation and interdisciplinary Research.

3. To develop professionals through innovative pedagogy focusing on individual growth, discipline,

integrity, ethics and social responsibility.

4. To foster industry-institution partnerships leading to skill development and entrepreneurship.

MISSION OF THE EEE DEPARTMENT

M1: To provide appropriate facilities and environment for effective teaching- learning process.
M2: To create interdisciplinary research ambience to nurture innovative and research skills.
M3: To incorporate interpersonal skills, professional integrity, ethics and societal responsibility.
M4: To imbibeentrepreneurship skills and leadership qualities.
 ProgrammeEducationalObjectives (PEOs)

PEO-1 Strong fundamental knowledge in electronics and communication Engineering,

analytical, critical reasoning and problem-solving skills to develop innovative
solutions(Continuing Education).

PEO-2 Professionally progress in electronics, communication, signal processing, VLSI,

embedded systems and related areas with an inclination towards R&D and lifelong
learning(Excellence in Career).

PEO-3 Entrepreneurship skills, leadership qualities to work with diversified teams in

multidisciplinary environment(Leadership and Multi-disciplinary).

PEO-4 Professionally deft and intellectually adept to develop solutions to complex

engineering problems with professional ethics and societal
responsibility(Contribution to Society).
 ProgrammeOutcomes(Pos)

PO_1 Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, andanengineeringspecializationtothesolutionofcomplexengineeringproblems.
PO_2 Problemanalysis:Identify,formulate,reviewresearchliterature,andanalyzecomplex
engineeringproblemsreachingsubstantiatedconclusionsusingfirstprinciplesofmathematics,naturalscie
nces,andengineeringsciences.
PO_3 Design/developmentofsolutions:Designsolutionsforcomplexengineeringproblemsanddesignsyste
mcomponentsorprocessesthatmeetthespecifiedneedswithappropriateconsiderationforthepublichealt
handsafety,andthecultural,societal,andenvironmental
considerations.
PO_4 Conductinvestigationsofcomplexproblems:Useresearch-
basedknowledgeandresearchmethodsincludingdesignofexperiments,analysisandinterpretationofdata,
andsynthesisofthe
informationtoprovidevalidconclusions.
PO_5 Moderntoolusage:Create,select,andapplyappropriatetechniques,resources,andmodern
engineeringandITtoolsincludingpredictionandmodelingtocomplexengineeringactivitieswithanunders
tandingofthelimitations.
PO_6 Theengineerandsociety:Applyreasoninginformedbythecontextualknowledgetoassess
societal,health,safety,legalandculturalissuesand
theconsequentresponsibilitiesrelevanttotheprofessionalengineeringpractice.
PO_7 Environmentandsustainability:Understandtheimpactoftheprofessionalengineeringsolutionsinsocie
talandenvironmentalcontexts,anddemonstratetheknowledgeof,andneed
forsustainabledevelopment.
PO_8 Ethics:Applyethicalprinciplesandcommittoprofessionalethicsandresponsibilitiesandnorms
oftheengineeringpractice.
PO_9 Individualandteamwork:Functioneffectivelyasanindividual,andasamemberorleaderin
diverseteams,andinmultidisciplinarysettings.
PO_10 Communication:Communicateeffectivelyoncomplexengineeringactivitieswiththeengineering
community and with society at large, such as, being able to comprehend and
writeeffectivereportsanddesigndocumentation,makeeffectivepresentations,andgiveandreceive
clearinstructions.
PO_11 Projectmanagementandfinance:Demonstrateknowledgeandunderstandingofthe
engineeringandmanagementprinciplesandapplythesetoone’sownwork,asamemberandleaderina
team,tomanage projectsandinmultidisciplinaryenvironments.
PO_12 Life-longlearning:Recognizetheneedfor,andhavethepreparationandabilitytoengagein
independentandlife-longlearning inthebroadestcontextoftechnologicalchange.
 ProgrammeSpecificOutcome(PSOs)

PSO-1 Design problems related to Electronics, Communications, Signal processing, VLSI and
Embedded systems.

PSO-2 Analyze and solve the complex Communication Engineering problems in architecture design
and computer networking.

PSO-3 An ability to use modern software tools to analyze, synthesize and evaluate VLSI and
Communication Engineering systems for multidisciplinary tasks.
 Dr.K.V.SUBBA REDDY INSTITUTE OF TECHNOLOGY
III B.Tech.I-Sem(ECE)
(23A104312P) ANALOG AND DIGITALCIRCUITS
LABORATORY
COURSEOUTCOMES(COS)

CO1 Interpret the characteristics of diodes and transistors for circuit design. L3
CO2 Construct and evaluate rectifiers, amplifiers, and oscillator circuits. L3
CO3 Implement basic Op-Amp applications, combinational and sequential circuits using logic gates. L4
CO4 Design digital systems using universal gates, multiplexers, and comparators. L4
CO5 evelop and realize fundamental digital components such as adders, converters, flip-flops, encoders,
and decoders. L4

PART A:
LIST OF EXPERIMENTS:
ANALOG CIRCUITS List of Experiments:
(Any 06 Experiments are to be conducted)
1. CB Characteristics
2. CE Characteristics.
3. CE Amplifier
4. CC Amplifier
5. Clippers
6. Clampers
7. Hartley & Colpitt‘s Oscillators.
8. RC Phase shift oscillator
9. Astable multivibrator
10. Monostable multivibrator
11. A to D Convertor
12. D to A Convertor
13. Op-Amp Applications-Adder, subtractor, comparator
PART B:
LIST OF EXPERIMENTS:
DIGITAL CIRCUITS List of Experiments:
(Any 6 Experiments are to be conducted)

1. Realization of Boolean Expressions using Gates

2. Design and realization of logic gates using universal gates
3. Generation of clock using NAND / NOR gates
4. Design a 4 – bit Adder / Subtractor
5. Design and realization of a 4 – bit Gray to Binary and Binary to Gray Converter
6. Design and realization of 8x1 MUX using 2x1 MUX
7. Design and realization of 4 bit comparator
8. Design and realization of Flip-Flops.
9. Design and realization of Encoders
10. Design and realization of Decoders
11. Design and realization of Comparator.
 DO’s

1. Studentsshouldbepunctualandregulartothelaboratory.
2. Studentsshouldcometothelabin-timewithproperdresscode.
3. Studentsshouldmaintaindisciplineallthetimeandobeytheinstructions.
4. Studentsshouldcarryobservationand recordcompletedinallaspects.
5. Studentsshouldbeattheirconcernedexperimenttable,unnecessarymomentisrestricted.
6. Studentsshouldfollowthe
indentproceduretoreceiveanddepositthecomponentsfromlabtechnician.
7. Whiledoingtheexperimentsanyfailure/malfunctionmustbereportedtothefaculty.
8. StudentsshouldchecktheconnectionsofcircuitproperlybeforeswitchONthepowersupply.
9. Studentsshouldverifythereading withthehelpofthelabinstructorafter
completionofexperiment.
10. StudentsmustendurethatallswitchesareinthelabOFFposition,alltheconnectionsare
removed.
11. Attheend ofpracticalclasstheapparatusshouldbereturned tothelabtechnicianandtake
backtheindentslip.
12. After completing your lab session SHUTDOWN the systems, TURNOFF the
powerswitchesandarrangethe chairs properly.
13. Eachexperimentshouldbewrittenintherecordnotebookonlyafter getting
signaturefromthelabinchargeintheobservationnotebook.
DON’Ts
1. Don’t eatanddrinkinthelaboratory.
2. Don’ttouchelectricwires.
3. Don’tturnONthecircuitunless itiscompleted.
4. Avoidmakinglooseconnections.
5. Don’tleavethe labwithoutpermission.
6. Don’tbringmobilesintolaboratory.
7. Donotopenanyirrelevantsitesoncomputer.
8. Don’t use a flash drive on computers.
 ADC LAB

INPUT&OUTPUTCHARACTERISTICSOFCBCONFIGURATION
14.
AIM:
Tostudytheinputand outputcharacteristicsofatransistorinCommonBaseconfiguration.

Equipment:
S.No. Name Quantity
1 CBConfigurationTrainer Kit 1(One)No.
2 DigitalAmmeters (0-200mA) 2(One)No.Each
3 DigitalVoltmeter(0 -20V) 2(Two)No.
4 Connectingwires(SingleStrand)

Specifications:
ForTransistorCL100:
 MaxCollector Current=1A
 VCEOmax=50V

CircuitDiagram:

h–ParametermodelofCBtransistor:

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 ADC LAB

PinassignmentofTransistor:

View from side of pins View from top of casing

Operation:
BipolarJunctionTransistor(BJT)isathreeterminal(emitter,base,collector)semiconductordevice.Therea
re two types of BJTs, namelyNPN and PNP. It consists of two PN junctions, namelyemitter junction
and collector junction.
Thebasiccircuit diagramforstudying input characteristicsisshowninthecircuit diagram.The
inputisapplied betweenemitterandbase, theoutputistakenbetweencollectorand base.
Herebaseofthetransistoriscommon to both input and output and hence the name is Common Base
Configuration.
Input characteristicsareobtainedbetweentheinputcurrentandinput voltageat constantoutputvoltage.Itis
plotted between VEEand IEat constant VCBin CB configuration.
Outputcharacteristicsareobtainedbetweentheoutputvoltageandoutput current atconstant input current.Itis
plotted between VCBand ICat constant IEin CB configuration.

Procedure:
Input Characteristics:
1. Connectthecircuitasshowninthecircuitdiagram.
2. KeepoutputvoltageVCB=0VbyvaryingVCC.
3. VaryingVEEgradually, notedownemittercurrentIEandemitter-basevoltage(VEE).
4. Stepsize isnot fixedbecauseofnonlinearcurve. InitiallyvaryVEEinstepsof0.1V.
Oncethecurrent starts increasing vary VEEin steps of 1V up to 12V.
5. Repeataboveprocedure(step3)forVCB=4V.
6.
OutputCharacteristics:
1. Connectthecircuitasshowninthecircuitdiagram.
2. Keepemittercurrent IE=5mAbyvarying VEE.
3. VaryingVCCgradually instepsof1Vupto12VandnotedowncollectorcurrentI Candcollector-
base voltage(VCB).
4. Repeatabove procedure(step3)forIE=10mA.

Observations:
Input Characteristics
VEE(Volts) VCB=0V VCB=4V
VEB(Volts) IE(mA) VEB(Volts) IE(mA)

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 ADC LAB

OutputCharacteristics
VCC(Volts) IE= 0mA IE= 5V IE= 10mA
VCB(Volts) IC(mA) VCB(Volts) IC(mA) VCB(Volts) IC(mA)

Graph:

1. Plotthe input characteristics fordifferent valuesof VCBbytakingVEEonX-axisandIEonY-

axis taking VCBas constant parameter.
2. Plottheoutputcharacteristicsbytaking VCBonX-axisandtaking IConY-axistaking
IEasaconstant parameter.

CalculationsfromGraph:
Theh-parametersaretobecalculatedfromthefollowingformulae:
1. Input Characteristics: Toobtaininput resistance, find VEEand IEforaconstant
VCBononeofthe input characteristics.
Input impedance= hib= Ri= VEE/ IE(VCB= constant)
Reverse voltagegain=hrb= VEB/ VCB(IE=constant)
2. OutputCharacteristics: Toobtainoutputresistance,find ICand VCBat
aconstantIE. Output admitance = hob = 1/Ro = IC/ VCB(IE= constant)
Forward currentgain=hfb= IC/ IE(VCB=constant)

Inference:
1. InputresistanceisintheorderoftensofohmssinceEmitter-BaseJunction isforward biased.
2. Outputresistanceisinorderofhundredsofkilo-ohmssinceCollector-BaseJunction isreversebiased.
3. HigheristhevalueofVCB, smalleristhecutinvoltage.
4. Increaseinthe valueofIBcausessaturationoftransistorat smallvoltages.

Precautions:
1. Whileperformingtheexperiment donot
exceedtheratingsofthetransistor.Thismayleadtodamage the transistor.

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 ADC LAB

2. Connectvoltmeterandammeterincorrectpolaritiesasshowninthecircuitdiagram.
3. Do notswitchONthepowersupplyunlessyouhavecheckedthecircuit
connectionsasperthecircuit diagram.
4. Makesurewhileselectingtheemitter,baseandcollectorterminalsofthetransistor.

Result:

Page 4
 ADC LAB

COMMON EMITTER AMPLIFIER:

AIM:To Study the common emitter amplifier and to findCut off frequencies, Bandwidth and Mid band
Voltage.

APPARATUS:
1. Common Emitter Amplifier Kit
2. Dual Trace CRO
3. Function generator
4. Patch Cords.

THEORY:The common emitter configuration is widely used as a basic amplifier as it has both voltage and
current amplification.
Resistors R1 & R2 form a voltage divider across the base of the transistor. The function of this network is to
provide necessary bias condition and, ensure that emitter - base junction is operating in the proper region.
In order to operate transistor as an amplifier, the biasing is done in such a way that the operating point
should be in the active region. For an amplifier the Q-point is placed so that the load line is bisected.
Therefore, in practical design the VCE is always set to VCC/2. This will conform that the Q-point always
swings with in the active region. This limitation can be explained by maximum signal handling capacity.
Output is produced with out any clipping or distortion for the maximum input signal. If not so, reduce the
input signal magnitude.

The Bypass Capacitor The emitter resistor RE is required to obtain the DC quiescent stability. However the
inclusion of RE in the circuit causes a decrease in amplification at higher frequencies. In order to avoid such
a condition, it is bypassed by capacitor so that it acts as a short circuit for AC and contributes stability for
DC quiescent condition. Hence capacitor is connected in parallel with emitter resistance.
𝑋𝐶𝐸 ≪ 𝑅𝐸

1
≪ 𝑅𝐸
2𝜋𝑓𝐶𝐸

1
𝐶𝐸 ≫
2𝜋𝑓𝑅𝐸
The Coupling Capacitor An amplifier amplifies the given AC signal. In order to have noiseless transmission
of signal (with out DC), it is necessary to block DC i.e. the direct current should not enter the amplifier or
load. This is usually accomplished by inserting a coupling capacitor between any two stages.
𝑋𝐶𝐶 ≪ (𝑅𝑖 ||ℎ𝑖𝑒 )

1
≪ (𝑅𝑖 ||ℎ𝑖𝑒 )
2𝜋𝑓𝐶𝐶

1
𝐶𝐶 ≫
2𝜋𝑓𝐶𝐶 (𝑅𝑖 ||ℎ𝑖𝑒 )
Frequency Response Emitter bypass capacitors are used to short circuit the emitter resistor and thus
increase the gain at high frequency. The coupling and bypass capacitors cause the fall of in the low
frequency response of the amplifier because their impedance becomes large at low frequencies. The stray
capacitors are effectively open circuits.
In the mid frequency range the large capacitors are effective short circuits and the stray capacitors are open
circuits, so that no capacitance appears in the mid frequency range. Hence, the mid band gain is maximum.

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 ADC LAB

At the high frequencies, the bypass and coupling capacitors are replaced by short circuits and stray
capacitors and the transistor determine the response.
CIRCUIT DIAGRAM:

BC 107

PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Set Source Voltage Vs = 50mV to 250mV (say) at 1 KHz frequency, using function generator.
3. Keeping the input voltage constant vary the frequency from 50Hz to 1MHz in regular steps and note
down the corresponding output voltage.
4. Plot the Graph: gain (dB) Vs frequency.
5. Calculate the bandwidth from Graph.
6. Calculate all the parameters at mid band frequencies (i.e. at 1 KHz).
7. To calculate Voltage Gain:
𝑂𝑢𝑡𝑝𝑢𝑡 𝑉𝑜𝑙𝑡𝑎𝑔𝑒(𝑉𝑜 )
𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝐺𝑎𝑖𝑛(𝐴𝑉𝑆 ) =
𝑆𝑜𝑢𝑟𝑐𝑒 𝑉𝑜𝑙𝑡𝑎𝑔𝑒(𝑉𝑠 )

𝑂𝑢𝑡𝑝𝑢𝑡 𝑉𝑜𝑙𝑡𝑎𝑔𝑒(𝑉𝑜 )
𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝐺𝑎𝑖𝑛(𝐴𝑉 ) =
𝐼𝑛𝑝𝑢𝑡 𝑉𝑜𝑙𝑡𝑎𝑔𝑒(𝑉𝑖 )
Here input voltage = Voltage across R2Resistor.
To obtain output resistance, measure the voltage across the output terminals without connecting any load.
Keep the input voltage constant connect a Decade Resistance Box (DRB) across output terminals. Change
the resistance until you get half of the open circuit voltage. The resistance of load will give the output
resistance.

TABULAR COLUMN:

VS = 50mV
𝑽 𝑽
Frequency VO(volts) Gain = 𝑽𝑶 Gain(dB) = 20log ( 𝑽𝑶 )
𝑺 𝑺

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 ADC LAB

GRAPH (FREQUENCY RESPONSE):

In the usual application, mid band frequency range are defined as those frequencies at which the response
has fallen to 3dB below the maximum gain (|A| max). These are shown as fL and fH, and are called as the
3dB frequencies are simply the lower and higher cut off frequencies respectively. The difference between
higher cut- off frequency and lower cut-off frequency is referred to as bandwidth (fH – fL).

Result:

Page 7
 ADC LAB

ASTABLE MULTIVIBRATOR

AIM: 1.To study and design IC 555 timer as an Astable multivibrator.

2.Calculate the frequency of oscillations & time period of output
Waveform.

APPARATUS: 1.IC 555 Timer Trainer kit.

2.20MHz C.R.O.
3.Multimeter
4.Connecting patch chords.

Circuit Diagram: Astable Multivibrator

INTRODUCTION:

The 555 Timer is used in number of applications; it can be used as monostable, astable
multivibrators, DC to DC converters, digital logic probes, analogy frequency voltage regulators and time
delay circuits.
The IC 555 timer is 8-pin IC and it can operate in free- running (Astable MV) mode or in one-shot
(Monostable MV ) mode.Pin configuration is as shown fig (1.a ). It can produce accurate and highly stable
time delays or oscillations.

THEORY:

Astable Multivibrator often called a free-running Multivibrator. External Trigger

input is not required to operate the 555 as an Astable Configuration. However, the time during which the
output is either high or low is determined by two external components Resistor & Capacitor.
Fig (1) shows the 555 as Astable Multivibrator. Initially, when the output is high, capacitor C starts
charging towards Vcc through resistor Ra and Rb. As soon as voltage across the capacitor equals to 2/3 Vcc,
comparator-1 triggers the flip-flop, and the output is low. Now capacitor discharges through R b and
transistor Q1. When the voltage across capacitor c equals to 1/3Vcc, comparator-2’s output triggers the flip-

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 ADC LAB

flop, and the output goes high. Then the cycle repeats. The output voltage waveforms are as shown in fig
(2).
In this way capacitor periodically charges 7 discharges between 2/3Vcc and 1/3Vcc respectively.
The time during which the capacitor charges from 1/3Vcc to 2/3 Vcc is equal to the time, the output
is high and is given by
tc = 0.69(Ra + Rb) c
The time during which the capacitor discharges from 2/3 Vcc to 1/3Vcc is equal to the time, the
output is low and is given by
td = 0.69(Rb) c
The Total Time period of the pulse is the sum of charge time and discharge time, time period is given by
T = tc + td
= 0.69(Ra + 2Rb) c
This, in turn gives the frequency of oscillation as given below
F = 1/T = 1.45/(Ra + 2Rb) c

DUTY CYCLE:

This term is in conjunction with Astable Multivibrator. The duty cycle is the ratio of the time t c during
which the output is high to the total time period T. It is generally expressed as a percentage.
%Duty cycle = tc/T *100
= (Ra + Rb/Ra + 2Rb)*100

PROCEDURE:

1. Connect the IC 555 timer as an astable configuration as shown in fig (1)

2. Connect the C.R.O at the output terminals.
3. Give the supply to the trainer.
4. Record & observe the waveforms at the output terminals and also across the capacitor.
5. Verify with the Sample output waveforms as shown in fig (2)
6. Calculate Tc,Td, time period of pulse (T) and duty cycle percentage theoretically and verify
with practical values.
7. Find the charging time tc discharging time td and totals time period T from the output
waveform.
8. Verify these values with theoretical values and calculate the % of the duty cycle.

Where Tc = 0.69 (RB + RA)C

RA =R2 + R1
Td = 0.69 RBC
T = Tc + Td
T
% of DC = d * 100
T

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 ADC LAB

WAVEFORMS:
VO

VCC

OV t

Vc
2/3 VCC

1/3 VCC
t

F
i
g
.

RESULT:

Page 10
 ADC LAB

MONOSTABLE MULTIVIBRATOR

AIM: 1.To study and design 555 timer as a Monostable multivibrator.

2.Calculate the frequency of oscillations & time period of output waveform.

APPARATUS: 1.555 Timer Trainer Kit.

2. 20MHz C.R.O
3. 1MHz Function generator
4. Multimeter
5. Connecting patch chords.

CIRCUIT DIAGRAM:

Page 11
 ADC LAB

INTRODUCTION:

The 555 Timer is used in number of applications; it can be used as monostable, astable multivibrators, DC to
DC converters, digital logic probes, analogy frequency voltage regulators and time delay circuits.
The IC 555 timer is 8-pin IC and it can operate in free- running (Astable MV ) mode or in one-shot (
Monostable MV ) mode.Pin configuration is as shown fig (1 ). It can produce accurate and highly stable
time delays or oscillations.

THEORY:

Monostable can also called as One-shot Multivibarator fig (1) Shows the Monostable
Multivibrator. When the output is low, the circuit is in stable state, Transistor Q1 is ON and capacitor C is
shorted out to ground. However, upon application of a negative trigger pulse to pin-2, transistor Q1 is turned
OFF, which releases short circuit across the external capacitor and drives the output High. The capacitor C
now starts charging up toward Vcc through RA. However, when the voltage across the external capacitor
equals 2/3 Vcc comparator-1’s (C1) output switches from low to high, which is turn drives the output to its
low state via the output of the flip flop turns transistor Q1 ON, and hence, capacitor C rapidly discharges
through the transistor. The output of the Monostable remains low until a trigger pulse is again applied. Then
the cycle repeats.

Fig (2) shows the trigger input and output voltages, and capacitor voltage waveforms. Pulse
width of the trigger input must be smaller than the expected pulse width of the output waveforms. Trigger
pulse must be a negative- going input signal with amplitude larger than 1/3 Vcc.
The time during which the output remains high is given by
tp =1.1RAC
Once triggered, the circuit’s output will remain in the high state until the set time t p elapses. The
output will not change its state even if an input trigger is applied again during this time interval t P.

PROCEDURE:
1. Connect the 555 timer as monostable mode as shown in fig (1).
2. Connect the C.R.O at the output terminals.
3. Apply external trigger at the trigger input terminal and give supply to trainer.
4. Record and observe the waveforms at the output terminals and also across the capacitor.
5. Verify with the sample output waveforms as shown in fig (2)
6. Calculate the pulse width, time period of pulse (Tp) theoretically and verify with practical values.
7. Now change RA value and observe out pulse width Tp and verify it theoretically.
Tp = 1.1 RA C

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 ADC LAB

WAVEFORMS:

RESULT:

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 ADC LAB

4 – BIT D/A CONVERTER (R-2R TYPE)

AIM: To obtain analog output voltages for the digital input data using 4 - bit R-2R type D/A
converter.

APPARATUS:
1) 4 – bit D/A converter (R-2R) Trainer Kit.
2) Multimeter.

CIRCUIT DIAGRAM:

THEORY:
Real world signals are analogue. Digital systems that interface with the real world do so using analogue-to-digital
converters (ADC). Conversion back to analogue is accomplished using digital-to- analogue converters (DAC). The R-
2R ladder network is commonly used for Digital to Analogue conversions.

In basic N bit R-2R resistor ladder network the digital inputs or bits range from the most significant bit (MSB) to the
least significant bit (LSB). The bits are switched between either 0V or VR and depending on the state and location of
the bits Vo will vary between 0V and VR . The MSB causes the greatest change in output voltage and the LSB causes
the smallest.

The R-2R ladder is inexpensive and relatively easy to manufacture since only two resistor values are required. It is fast
and has fixed output impedance R.

In R-2R ladder type D to A converter, only two values of resistor is used (i.e. and 2R). Hence it is suitable for
integrated circuit fabrication. The typical values of R are from 2.5Kto 10K. In this output voltage is a weighted
sum of digital inputs. Since the resistive ladder is a linear network, the principle of super position can be used to find
the total analog output voltage for a particular digital input by adding the output voltages caused by the individual
digital inputs.The output voltage is linearly proportional to the digital input and the range can be adjusted by changing
the reference voltage VR .
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 ADC LAB

PROCEDURE:
1. Connect the trainer to the mains and switch on the power supply.
2. Measure the supply voltages of the circuit as +12V & -12V.
3. Calculate theoretically Vo for all digital Input data using formula.
b3 b b b
V0 = -Rf ( + 2 + 1 + 0 ).
2 R 4 R 8R 16R
In this experiment Rf = 1 1k & R= 11k.
4. Note down Output voltages for different combinations of digital inputs and compare it with theoretical values.
For Example:
When b3 is high and all other inputs are low then the output voltage is
5 0 0 0
V0 = - Rf ( + + + )
2 R 4 R 8 R 16 R
= -11K( 5 )
2 * 11K

= -2.5V
TABLE:
DIGITAL I/P DATA Observed V0 Calculated V0
b3 b2 b1 b0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

RESULT:

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 ADC LAB

8-BIT A/D CONVERTER (ADC 0808)

AIM: To study the analog to digital convertion using Successive approximation method.

APPARATUS:
1. A/D Converter trainer
2. Digital Multimeter
3. Connecting Wires
THEORY:

Regulated Power Supply:

This consists of bridge rectifier followed by capacitor filter and three terminal regulators to provide regulated
DC voltages in the circuit.i.e, ± 5V and 12v @ 150mA each.
A/D Convertor:A block diagram of the ADC 0808 is shown below.

Block digram:

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 ADC LAB

Connection Diagrams Dual-In-Line Package

CONVERTER
CHARACTERIS
TICS
The Converter
The heart of this single chip data acquisition system is its 8- bit analog-to-digital converter. The
converter is designed to give fast, accurate, and repeatable conversions over a wide range of temperatures. The
converter is partitioned into 3 ma- jor sections: the 256R ladder network, the successive ap- proximation
register, and the comparator. The converter's digital outputs are positive true.
The 256R ladder network approach (Figure 1) was chosen over the conventional R/2R ladder because of its
inherent monotonicity, which guarantees no missing digital codes. Monotonicity is particularly important in
closed loop feedback control systems. A non-monotonic relationship can cause os- cillations that will be
catastrophic for the system. Additionally, the 256R network does not cause load variations on the ref- erence
voltage.is reset on the positive edge of the start conversion start pulse. The conversion is begun on the falling edge
of the start con- version pulse. A conversion in process will be interrupted by receipt of a new start conversion
pulse. Continuous conver- sion may be accomplished by tying the end-of-conversion (EOC) output to the SC
input. If used in this mode, an external start conversion pulse should be applied after power up. End- of-conversion
will go low between 0 and 8 clock pulses after the rising edge of start conversion.
The most important section of the A/D converter is the com- parator. It is this section which is responsible
for the ultimate accuracy of the entire converter. It is also the comparator drift which has the greatest influence
on the repeatability of the device. A chopper-stabilized comparator provides the most effective method of
satisfying all the converter requirements.The chopper-stabilized comparator converts the DC input sig- nal into
an AC signal.
This signal is then fed through a high gain AC amplifier and has the DC level restored. This tech- nique limits
the drift component of the amplifier since the drift is a DC component which is not passed by the AC amplifier.
This makes the entire A/D converter extremely insensitive to temperature, long term drift and input offset errors.

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FIGURE 1. Resistor Ladder and Switch Tree

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Timing diagram:

Theoritical calculation:

Theoretical value can be obtained by:

A/D input voltage
________________ = X(10) = Y(2)
1 LSB value

Where
1 LSB value = Vref / 2n
Since Vref = 5V and n= 8
1 LSB Value = 0.01953
Example:
A/D input voltage = 1 V
= 51.2(10)
= 00110011(2)
So digital output is 00110011

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s.no Analog input Digital output

voltage (VA) binary
1 1V 00110011
2 2V
3 3V

Procedure

1. Switch ON SSLAB Model IC- 28 trainer

2. Supplies are built in need not connect externally
3. Apply Clock Signal to 10th and 22nd pin which are shorted
4. Apply Input DC 0-5V Signal to 26 th Pin and observe the Binary out put
Corresponding to DC Voltage

RESULT:

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DIGITAL CIRCUITS

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Experiment-3
8X1 MULTIPLEXERUSING IC 74LS151
AIM: To construct multiplexer and de-multiplexer circuits using IC-74X151 and IC-74X155 respectively.

8X1 MULTIPLEXER
THEORY:
Multiplexer is a combinational circuit that has most of 2n data inputs, „n‟ selection lines with a single
output. One of these data inputs will be connected to the output Y based on the values of selection lines. 8 X
1 Multiplexer has 8 data inputs I0, I1, I2, I3, I4, I5, I6 & I7, 3 select lines S0, S1, & S2 and one output Y.

Procedure:
1. Connect Data inputs(I0-I7) to logic switches with the help of patch cords.
2. Connect Z and 𝑍 output to logic indicator.
3. Connect the enable (𝐸) to the logic switch and put this to
4. Put S0 =0 & S1=0 and S2=0 and observe the output by changing input levels. Withthis we can notice that
the output is following only I0 and the other inputs cannotaffects the output.
5. By varying the selection lines S0,S1and S2 verify the truth table of the 8X1 multiplexer

TRUTH TABLE:
𝐸 S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 Z 𝑍
H X X X X X X X X X X X X X
L 0 0 0 0 X X X X X X X 1 0
L 0 0 0 1 X X X X X X X 0 1
L 0 0 1 X 0 X X X X X X 1 0
L 0 0 1 X 1 X X X X X X 0 1
L 0 1 0 X X 0 X X X X X 1 0
L 0 1 0 X X 1 X X X X X 0 1
L 0 1 1 X X X 0 X X X X 1 0
L 0 1 1 X X X 1 X X X X 0 1
L 1 0 0 X X X X 0 X X X 1 0
L 1 0 0 X X X X 1 X X X 0 1
L 1 0 1 X X X X X 0 X X 1 0
L 1 0 1 X X X X X 1 X X 0 1
L 1 1 0 X X X X X X 0 X 1 0
L 1 1 0 X X X X X X 1 X 0 1
L 1 1 1 X X X X X X X 0 1 0
L 1 1 1 X X X X X X X 1 0 1

Result:

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Experiment-4
ENCODER
8x3ENCODER:
AIM: To verify operation of 8:3 Priority Encoder using IC 74LS148
APPARATUS:
1. 8:3 Priority Encoder IC 74LS148 kits
2. Patch chords

THEORY:
An encoder is a combinational circuit that connects the binary information from ‘2 n’ input lines to a
maximum of n unique input lines. The IC 74148 accepts three binary outputs and when enable provides 8
indivual active low inputs.

PROCEDURE:
1.Make the connections as per the circuit diagram.
2.Change the values of EI, 0 To 7 using logic indicators.
3.Observe the output status of A2, A1, A0, GS, and EO at output logic indicators.
4.Verify the truth table.

TRUTH TABLE:
INPUTS OUTPUTS
EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO
H X X X X X X X X H H H H H
L H H H H H H H H H H H H L
L X X X X X X X L L L L L H
L X X X X X X L H L L H L H
L X X X X X L H H L H L L H
L X X X X L H H H L H H L H
L X X X L H H H H H L L L H
L X X L H H H H H H L H L H
L X L H H H H H H H H L L H
L L H H H H H H H H H H L H

RESULT:

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Experiment-5
DECODER
3x8 DECODER:

AIM:To verify operation of 3 to 8 decoder using ic 74LS138

APPARATUS:
1. 3 to8decoder IC 74LS138 kits
2. Patch chords

Theory:
A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to a maximum
of 2n unique out lines. The IC 74LS138 accepts three binary inputs and when enable provides 8 indivual
active low outputs. The devices has 3 enable inputs. Two active low and one active high.

PROCEDURE:
1.Make the connections as per the circuit diagram.
2.Change the values of E1, E2, E3, A, B, and C using switches.
3.Observe status of Y0 to Y7 on LED’s.
4.Verify the truth table.

Note: Instead of enable inputs G2a,G2b,G1we are giving on boardE3,E2,E1and A0,A1,A2.

TRUTH TABLE:
INPUTS OUTPUTS
E1 E2 E3 A0 A1 A2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
H X X X X X H H H H H H H H
X H X X X X H H H H H H H H
X X L X X X H H H H H H H H
L L H L L L L H H H H H H H
L L H H L L H L H H H H H H
L L H L H L H H L H H H H H
L L H H H L H H H L H H H H
L L H L L H H H H H L H H H
L L H H L H H H H H H L H H
L L H L H H H H H H H H L H
L L H H H H H H H H H H H L

RESULT:

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Experiment-6
COMPARATOR

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