ALUMNI SHINING G LO B A L LY

N O . 1 D E S T I N AT I O N F O R V L S I & E M B E D D E D S Y S T E M S T R A I N I N G

Advanced VLSI Design

& Verification Course
Offline | Blended | Online

5000+ 250+
Global Alumni Hiring Partners

Hands-on Training Placement Assistance 1:1 Mentoring 24/7 Lab Access & Support
A D VA N C E D V L S I D E S I G N & V E R I F I C AT I O N C O U R S E M AV E N - S I L I C O N . C O M

MAVEN SILICON Maven Silicon is a leading provider of VLSI & Embedded training for students and profession-
als. We offer a range of high-quality VLSI & Embedded training programs and internships,
taught by experienced industry professionals, aimed at helping engineers to upskill and
advance their careers in the fast-growing Semiconductor Industry. From digital design and
verification to physical design and design for testing, Maven Silicon covers a wide variety of
topics along with labs and projects through Industry standard EDA tools. Our
state-of-the-art training facilities, coupled with innovative training methods, provide
students with hands-on experience and a strong foundation in the latest VLSI & Embedded-
technologies. Our curriculum is designed to meet the demands of the industry and is
constantly updated to keep pace with the latest advancements. In addition, Maven Silicon
offers flexible scheduling options and customized training programs to accommodate
student's busy schedules.

With a commitment to excellence and a passion for empowering students and professionals,
Maven Silicon is dedicated to providing the highest quality hands-on training to help
engineers reach their full potential in the Semiconductor industry.

My vision is to create an excellent learning ecosystem of

superior technical expertise, hands-on training experience,
and industry-oriented courses with innovative learning
processes.

For more than 15 years, Maven Silicon has been a benchmark

for the VLSI training ecosystem in India, offering high-quality
VLSI training courses for VLSI aspirants, professionals, and
organizations across the globe.

Sivakumar P R
Founder and CEO

Our CEO, Sivakumar P R, has 25+ years of experience in the engineering and semiconductor industries. He has worked as a Verification
Consultant in the top EDA companies like Synopsys, Cadence, and Mentor Graphics. During this tenure, he worked very closely with
various ASIC and FPGA design houses and helped them to use the EDA solutions effectively for the successful tape-outs of multi-million
gate designs.

To know more about our CEO, visit https://www.linkedin.com/in/sivapr/

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Five reasons to muse with MAVEN SILICON

Dynamic VLSI courses designed and delivered by Industry experts
01
Maven Silicon is the Best VLSI training center which provides high-class industry standard VLSI training. The courses have been
designed by industry experts, based on the job opportunities and career growth in the semiconductor industry and we keep
updating our VLSI Curriculum as per the latest industry trends.

Superior Training Methodology and Infrastructure

02
Our training methodology is unique. It helps our students to learn even complex technologies in a short span of time and make
them experts. 70% of the course time is dedicated to the labs, mini projects, and the final project. Our training courses help you
to acquire the technical skills which are highly required to get a job in the semiconductor industry.

100% Placement Support

03
Maven Silicon provides 100% placement assistance to the eligible trainees of the job-oriented programs and keeps supporting
them until 12 months after course completion. Our primary objective is to help electronics engineers successfully build a career
in the semiconductor/VLSI Industries. We work closely with various VLSI products & services companies and identify the right
opportunities. Most of our students have been successfully placed in reknowned semiconductor companies.

Excellent Support
04
Maven Silicon offers 1:1 mentoring and 24/7 online support through the MASS platform. The trainees have 24/7 lab access to
enhance technical skills and participate in group discussions to gain new knowledge. Business communication sessions and
mock interviews provide the necessary skills to succeed in a professional setting.

Free Internship
05
Maven Silicon's free internship program offers trainees the opportunity to gain hands-on experience working with complex IPs,
VIPs, and SoCs, as well as a thorough understanding of the entire project life cycle from architecture to synthesis, making the
trainees industry-ready.

EDA Partner

Siemens is a leader in Electronic Design Automation. Synopsys is at the forefront of Smart Everything
Its innovative products and solutions help engineers with the world's most advanced tools for silicon
conquer design challenges in the seemingly daunting chip design, verification, IP integration, and
world of board and chip design. application.
https://eda.sw.siemens.com/en-US/ https://www.synopsys.com/

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Advanced VLSI Physical Design

COURSE CURRICULUM

& Verification Course

Advanced VLSI Design
& Verification Course ONLINE | OFFLINE | BLENDED

21 Modules OS - Linux Ubuntu EDA Tools - Synopsys, Siemens, Xilinx, Aldec

Introduction to VLSI Verilog

MODULEHDL
IV - RTL Coding and Synthesis Verilog HDL - RTL Coding and Synthesis

Module I Module IV Continued...

VLSI Design Flow Introduction to Verilog HDL Synthesis Coding

ASIC vs FPGA Applications of Verilog HDL Unwanted latches
RTL Design Methodologies Verilog HDL language concept Synthesizable operators
Introduction to ASIC Verification Verilog language basics and RTL coding styles
Methodologies constructs Synthesis errors
Abstraction levels
VLSI Design Flow Steps – Demo
Data Types
Type Concept Static Timing Analysis
Introduction to Linux Nets and registers
Non-hardware equivalent Module V
Module II
variables Introduction to STA
Components of the UNIX system Arrays Comparison with DTA
Directory Structure Timing Path and Constraints
Verilog Operators
Utilities and Commands Different types of clocks
Logical operators
Vi Editor
Bitwise and Reduction operators Clock domain and Variations
Concatenation and conditional Clock Distribution Networks
operators How to fix timing failure
Advanced Digital Design Relational and arithmetic operators Methods to improve timing
MODULE III
Shift and Equality operators
Module III
Operators precedence
Introduction to Digital Electronics
Assignments FPGA Architecture
Arithmetic Circuits
Type of assignments Module VI
Data processing Circuits
Continuous assignments
Universal Logic Elements PLD
Timing references
Combinational Circuits - Design General Structure and
Procedures
and Analysis Classification
Blocking and Non-Blocking
CPLD Vs FPGA
Latches and Flip flops assignments
Shift Registers and Counters Execution branching Xilinx CPLD - Xc9500

Sequential Circuits - Design and Analysis Tasks and Functions Block Diagram of CPLD
Detailed study of each block
Memories and PLD
Finite State Machine Timing Model
Finite State Machine
Basic FSM structure
Microcontroller Design Xilinx FPGA
Moore Vs Mealy
FPGA Architecture
Common FSM
coding styles CLBs and Input/Output Blocks
Registered outputs Luts, SLICE DFFs
Dedicated MUXes
Advanced Verilog for Verification Programmable Interconnects
System Tasks Architectural Resources
Compiler directives Power Distribution and
Internal variable Configuration
monitoring FPGA Architecture of Xilinx
File input and output Families

C O P Y R I G H T 2 0 2 4 M AV E N S I L I C O N , A L L R I G H T S R E S E R V E D
A D VA N C E D V L S I D E S I G N & V E R I F I C AT I O N C O U R S E M AV E N - S I L I C O N . C O M

COURSE CURRICULUM

Advanced VLSI Design

& Verification Course ONLINE | OFFLINE | BLENDED

21 Modules OS - Linux Ubuntu EDA Tools - Synopsys, Siemens, Xilinx, Aldec

Code Coverage ASIC Verification Methodologies SystemVerilog HVL

Module VII Module XI Continued...

Statement coverage Directed Vs Random Direct Programming Interface

Branch Coverage Functional verification process
Functional Coverage
Expression Coverage Monitors and reference
models Coverage models
Path Coverage
Coverpoints and bins
Toggle Coverage Stimulus Generation
Cross coverage
FSM - State, Transition coverage Verification Planning and manage-
Regression testing
ment
Bus functional model
Coverage Driven Verification
Verilog Mini Project RTL Coding and Synthesis Advanced SystemVerilog

Module XIII
Module VIII
SystemVerilog HVL Environment Configuration
Project Specification Analysis
Module XII Reference Models and Predictor Logics
Understanding the architecture
Introduction to SystemVerilog Using Legacy BFMs
Module level implementation and
verification New Data types Scenario Generation

Building the top-level module Tasks and Functions Testcases - Random, Directed, and
Interfaces corner case
Clocking blocks Coding styles for VIP
CMOS Fundamentals
Object Oriented Programming and
Module IX Randomization
UVM - Universal Verification Methodology
Non-Ideal characteristics OOP Basics
Classes - Objects and handles Module XIV
BJT vs FET
Polymorphism and Inheritance Introduction to UVM Methodology
CMOS Characteristics
Randomization Overview of Project
CMOS circuit design
Constraints UVM TB Architecture
Fabrication Process
Overview Stimulus Modeling
Threads and Virtual Interfaces
Transistor sizing Creating UVCs and
Fork Join Environment
Layout and Stick Diagrams
Fork Join_any
CMOS Technology - Current UVM Simulation Phases
Fork Join_none
Trends Testcase Classes
Event controls
CMOS Processing Steps TLM Overview
Mailboxes and semaphores
Virtual Interfaces Configuring TB Environment
Transactors UVM Sequencers
Design Automation using Scripts - Perl
Building verification environment Connecting DUT-
Module X Testcases Virtual Interface
Introduction to Perl Virtual Sequences and Sequencers
Functions and Statements Callbacks Creating TB Infrastructure
Numbers, Strings, and Quotes Facade Class Connecting multiple UVCs
Comments and Loops Building Reusable Transactors Building a Scoreboard
Regular Expressions Inserting Callbacks Introduction to Register Modeling
File Operations Registering Callbacks
Building reusable environments

C O P Y R I G H T 2 0 2 4 M AV E N S I L I C O N , A L L R I G H T S R E S E R V E D
A D VA N C E D V L S I D E S I G N & V E R I F I C AT I O N C O U R S E M AV E N - S I L I C O N . C O M

COURSE CURRICULUM

Advanced VLSI Design

& Verification Course ONLINE | OFFLINE | BLENDED

21 Modules OS - Linux Ubuntu EDA Tools - Synopsys, Siemens, Xilinx, Aldec

Verification Mini Project Business communication RISC V Processor

Module XV Module XIX Module XX

Verification and RTL sign-off Transition from College to Corporate RISC-V Instruction Set Architecture
Project specification analysis Interpersonal skills and RISC-V processor overview
Defining verification plan Presentation Skills RISC-V ISA Overview
Creating Testbench architecture Email Etiquette RV32I – R and I Type Instruction
Implementing the transactors - Genera- Resume writing RV32I – S and B Type Instructions
tor, Driver, Receiver, and Scoreboard RV32I – J and U Type Instructions
Mockup Interviews Technical/HR
Defining Transaction RV32I – Assembly Programs
Interview Skills: Group Discussion
Implementing the coverage model and HR Round Preparation
RISC-V RV32I RTL Architecture Design
Building the top-level verification
RISC-V Execution Stages and Flow
environment
Building regression test suite RISC-V Register File and RV32I
Instructions Format
Coverage Analysis and Coverage Design for Testability - DFT
RV32I – R and I Type ALU Datapath
Closure ELECTIVE MODULE
RV32I – S Type ALU Datapath -
Introduction to DFT Load and Store
Types of Testing RV32I – B and U Type ALU Datapath
Interfaces and Protocols
Basic Testing Principles RV32I – J Type ALU Datapath –
Module XVI Fault Collapsing JAL and JALR

Lectures by Industry Experts Introduction to Tessent Shell

RISC-V RV32I 5 Stage Pipelined RTL
Structured Techniques
Design
BIST & Boundary Scan
CPU Performance and RISC-V 5 Stage
DFT Techniques - Ad-hoc
Verification Planning and Management Pipeline Overview
Techniques
RISC-V 5 Stage Pipeline – Data
Module XVII Scan Chain
Hazards and Design Approach
Verification Plan Test Coverage
RISC-V 5 Stage Pipeline – Control
TB Architecture Fault Change Hazards and Design Approach
Coverage Model Tessent Shells

Tracking the simulation process System Modes & TSDB

Building regression test suite Industry Standard Project

Test suite optimization
Module XXI

Design specification analysis

Creating the design architecture
Assertion Based Verification - SVA Partitioning the design

Module XVIII
RTL coding in Verilog

Introduction to ABV RTL functional verification

Immediate Assertions RTL Synthesis

Building regression test suite
Simple Assertions
Coverage Analysis and Coverage
Sequences
Closure
Sequence Composition
Advanced SVA Features
Assertion Coverage

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