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VLSI SoC Design Using Verilog HDL 14th Feb

The document outlines a schedule for VLSI SoC Design using Verilog HDL training sessions that will take place over multiple days and times each week. Various topics will be covered like VLSI introduction, design flow, Verilog HDL, operators, tasks and functions through a combination of live sessions, elearning portal, quizzes and labs using tools like Modelsim and Quartus Prime.

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Ankit Pandey

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0% found this document useful (0 votes)

157 views1 page

VLSI SoC Design Using Verilog HDL 14th Feb

Uploaded by

Ankit Pandey

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

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VLSI SoC Design using Verilog HDL

Live sessions are planned on: https://elearn.maven-silicon.com/

Days of week Timing Topic Mode of Learning

06.00 PM to 7:00 PM Induction and Elearn Demo Live Q & A

Wednesday
VLSI Introduction, SOC design & ASIC
6:00 PM to 7:00 PM Elearn portal
v/s FPGA

Thursday 6:00 PM to 7:00 PM Week 2: Live Q & A Live Q & A

VLSI design flow & Knowledge check

Friday 5:00 PM to 7:00 PM
Quiz

Introduction to Verilog HDL

Monday 5:00 PM to 7:00 PM Elearn portal
Knowledge check

Data types
Elearn portal Tools-Modelsim
Tuesday 5:00 PM to 7:00 PM Knowledge check
& Quartus prime
Lab1

Verilog Operators
Elearn portal &Tools-
Wednesday 5:00 PM to 7:00 PM Knowledge check
Modelsim & Quartus prime
Lab2

Thursday 6:00 PM to 7:00 PM Week 2: Live Q & A Live Q & A

System task & functions Elearn portal Tools-Modelsim

Friday 5:00 PM to 7:00 PM
Knowledge check & Quartus prime

Assignments (Processes) Elearn portal Tools-Modelsim

Monday 5:00 PM to 7:00 PM
Knowledge check & Quartus prime

Elearn portal
Tuesday 5:00 PM to 7:00 PM Lab3 Tools-Modelsim & Quartus
prime

Download the Certificate

Feel free to reach at training_support@maven-silicon.com for any queries

Maven Silicon Softech Pvt Ltd.

21/1A, III Floor, MS Plaza, Gottigere, Bannerghatta Main Rd, Bengaluru, Karnataka 560076 | www.maven-silicon.com

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VLSI SoC Design Using Verilog HDL 14th Feb

Uploaded by

VLSI SoC Design Using Verilog HDL 14th Feb

Uploaded by

VLSI SoC Design using Verilog HDL

Live sessions are planned on: https://elearn.maven-silicon.com/

Days of week Timing Topic Mode of Learning

06.00 PM to 7:00 PM Induction and Elearn Demo Live Q & A

Thursday 6:00 PM to 7:00 PM Week 2: Live Q & A Live Q & A

VLSI design flow & Knowledge check

Introduction to Verilog HDL

Thursday 6:00 PM to 7:00 PM Week 2: Live Q & A Live Q & A

System task & functions Elearn portal Tools-Modelsim

Assignments (Processes) Elearn portal Tools-Modelsim

Download the Certificate

Feel free to reach at training_support@maven-silicon.com for any queries

Maven Silicon Softech Pvt Ltd.

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