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CS3351 DPCO UNIT 4 notes

DPCO (Anna University)

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CS3351 DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION 3 0 2 4

UNIT IV PROCESSOR
Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired Control,
Micro programmed Control – Pipelining – Data Hazard – Control Hazards.

INSTRUCTION EXECUTION
 The execution of an instruction in a processor can be split up into a number of stages.
How many stages there are, and the purpose of each stage is different for each
processor design.
 Examples: 2 stages (Instruction Fetch / Instruction Execute) and 3 stages (Instruction
Fetch, Instruction Decode, Instruction Execute).
 The MIPS processor has 5 stages of Instruction Execution
1. IF:The Instruction Fetch stage fetches the next instruction from memory using the
address in the PC (Program Counter) register and stores this instruction in the IR
(Instruction Register)
2. ID:The Instruction Decode stage decodes the instruction in the IR, calculates the
next PC, and reads any operands required from the register file.
3. EX:The Execute stage "executes" the instruction. In fact, all ALU operations are done
in this stage. (The ALU is the Arithmetic and Logic Unit and performs operations
such as addition, subtraction, shifts left and right, etc.)
4. MA:The Memory Access stage performs any memory access required by the current
instruction, So, for loads, it would load an operand from memory. For stores, it
would store an operand into memory. For all other instructions, it would do nothing.
5. WB:Write Back For instructions that have a result (a destination register), the Write
Back writes this result back to the register file. Note that this includes nearly all
instructions, except nops (a nop, no-op or no-operation instruction simply does
nothing) and s (stores).

1.Basis MIPS Implementation

 The basic MIPS implementation that has three kinds of core instruction set such as,
1. The memory-reference instructions load word (lw) and store word (sw)
2. The arithmetic-logical instructions add, sub, AND, OR, and slt
3. The instructions branch equal (beq) and jump (j)
 An Overview of the Implementation
For every instruction, the first two steps are identical:
1. Send the program counter (PC) to the memory that contains the code and fetch the
instruction from that memory.
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2. Read one or two registers, using fields of the instruction to select the registers to
read. For the load word instruction, we need to read only one register, but most
other instructions require reading two registers.
 For example, all instruction classes, except jump, use the arithmetic-logical
unit(ALU) after reading the registers.
 The memory-reference instructions use the ALU for an address calculation, the
arithmetic-logical instructions for the operation execution, and branches for
comparison.
 A memory-reference instruction will need to access the memory either to read
data for a load or write data for a store.
 An arithmetic-logical or load instruction must write the data from the ALU or
memory back into a register.
 Lastly, for a branch instruction, we may need to change the next instruction
address based on the comparison; otherwise, the PC should be incremented by 4
to get the address of the next instruction.
Figure 4.1 An abstract view of the implementation of the MIPS
The following figure shows the high-level view of a MIPS implementation, focusing on
the various functional units and their interconnection.

 A logic element need to be added that chooses from among the multiple
sources and steers one of those sources to its destination.
 This selection is commonly done with a device called a multiplexor, also called a
data selector.
 The multiplexor selects from among several inputs based on the setting of its
control lines. The control lines are set based primarily on information taken from
the instruction being executed.
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Figure 4.2 Basic implementation of the MIPS

The figure shows the data path of Figure 4.1 with the three required multiplexors added, as
well as control lines for the major functional units.
 A control unit, which has the instruction as an input, is used to determine how to set
the control lines for the functional units and two of the multiplexors.

 The top multiplexor controls the value of PC(PC+4 or the branch destination
address.
 The middle multiplexor is used to steer the output of the ALU for writing in to the
register file.
 The bottom most multiplexor is used to determine whether the second ALU input
is from the registers

2.BUILDING A DATAPATH
 Types of data path
 Single-cycle Datapath: Each instruction executes in a single cycle
 Multi-cycle Datapath: Each instruction is broken up into a series of shorter steps
 Pipelined Datapath: Each instruction is broken up into a series of steps; Multiple
instructions execute at once

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 This simplest data path will attempt to execute all instructions in one clock cycle.
 No data path resource can be used more than once per instruction, so any element
needed more than once must be duplicated need a memory for instructions separately
 Many of the elements can be shared by different instruction flows.
 To share a data path element between two different instruction classes, multiple
connections to the input of an element, using a multiplexor and control signal to select
among the multiple inputs.
 A reasonable way to start a data path design is to examine the major components
required to execute each class of MIPS instructions.
 To share a data path element between two different instruction classes, need to allow
multiple connections to the input of an element.
 If two instructions have two different formats to store result so need to support two
different sources for the data stored into the register file.
 For that need two multiplexers, one multiplexor is placed at the ALU input and another
at the data input to the register file.

2.1Differences between single cycle and multi cycle datapath

Single cycle Data Path: Multi-cycle Data Path:
Each instruction is processed in Divide the processing of each instruction into 5
one (long) clock cycle stages and allocate one clock cycle per stage
Two separate memory units for Single memory unit for both instructions and
instructions and data. data

2.2Data path Element:

 It is a unit used to operate on or hold data within a processor.
 In the MIPS implementation, the data path elements includes
1. The instruction and data memories
2. The register file
3. The ALU
4. Adders.

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 Instruction memory:
 The instruction memory need only provide read access because the data path
does not write instructions.
 The instruction memory is called as combinational element because it will
perform only read access.
 The output at any time reflects the contents of the location specified by the
address input,
 No read control signal is needed.
 Program Counter:
 The program counter is a 32-bit register that is written at the end of every
clock cycle
 Does not need a write control signal.
 The register containing the address of the instruction in the program being
executed.
 Adder:
 The adder is an ALU wired to always add its two 32-bit inputs and place the sum
on its output.
 Fetching Phase:
 To execute any instruction, must start by fetching the instruction from memory.
 To prepare for executing the next instruction, must also increment the
program counter
 So that it points at the next instruction, 4 bytes (PC+4).

Instruction classes are,

 Arithmetic and logical instructions
 Memory reference instructions
 Branch Instructions
2.3 Data Path for ALU instructions
 It is also called as R-format instructions
 To perform an ALU operation these instructions read two registers, and write the

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result to a one register.

 This instruction class includes add, sub, AND, OR, and slt.
 The processors having 32 general-purpose registers and special purpose registers.
 General-purpose registers and special purpose registers are stored in separate space
of memory.
 These 32 general-purpose registers are stored in a structure called a register file.
 Register File
 A register file is a state element that contains set of registers that can be read or
written by specifying the number to be accessed.
 The register file contains the register state of the computer.
 R format instructions operand
 R-format instructions have three register operands to perform ALU operation.
 Two registers data are read from the register file and write one data word into
the register file for each instruction.
 To read data word from the registers, have to specify the register number.
 Register number specifies which data has to be read from which register present
in the register file.
 To write a data word, we will need two inputs:
1. One to specify the register number to be written
2. One to supply the data to be written into the register.
 Write operations are controlled by the write control signal, which must be
asserted for a write to occur at the clock edge.

 There are two elements need to implement the R-format ALU operations such as
1. Register file
2. ALU
1.Register file:
 The register file contains all the registers and has two read ports and one write
port.
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 The register file always outputs the contents of the registers corresponding to
the Read register inputs on the outputs
 No other control inputs are needed.
 Register write must be explicitly indicated by asserting the write control signal.
 The register number to the register file is all 5 bits wide to specify one of 32 bits
wide.
2.ALU:
 ALU takes two 32 bit inputs and produces a 32 bit result as well as 1 bit signal if
the result is 0.
 The operation to be performed by the ALU is controlled with the ALU operation
signal, which will be 4 bits wide.
 The Zero detection output used to implement branches.
2.4 Data path for Memory reference instructions
 Consider the MIPS load word and store word instructions, which have the general form.
 lw $t1,offset_value($t2)
 2.sw $t1,offset_value ($t2).
 These instructions compute a memory address by adding the base register, which is
 $t2, to the 16-bit signed off set field contained in the instruction.
 Memory address= base register+16-bit signed off set field
 If the instruction is a store, the value to be stored must also be read from the register
file where it resides in $t1.
 If the instruction is a load, the value read from memory must be written into the
register file in the specified register, which is $t1.
 Units needed to implement loads and stores
 To implement MIPS load and store instructions - four units required
1.Register file
2.ALU
3.Data Memory
4.Sign extension unit

1.
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Register file:
 The register file contains all the registers and has two read ports and one write
port.
 The register file always outputs the contents of the registers corresponding to
the Read register inputs on the outputs
 No other control inputs are needed.
 Register write must be explicitly indicated by asserting the write control signal.
 The register number to the register file is all 5 bits wide to specify one of 32 bits
wide.
2.ALU:
 ALU takes two 32 bit inputs and produces a 32 bit result as well as 1 bit signal if
the result is 0.
 The operation to be performed by the ALU is controlled with the ALU operation
signal, which will be 4 bits wide.
 The Zero detection output used to implement branches.
3.Data Memory unit:
 The memory unit is a state element with inputs for the address and the write
data.
 It produces a single output for the read result.
 Data Memory unit has separate read and write control lines for read and write
operation.
 Register file does not require read signal but memory unit needs a read signal
 Because the register file, reading the value of an invalid address can cause
problems.
4.Sign Extension unit:
 The sign extension unit has a 16-bit data input and that sign-extended into a 32-
bit result.
2.5 Data Path for Branch Instructions
 There are two kinds of branch instructions are available beq-branch equal,bnq-branch
unequal
 The beq instruction has three operands, in that
 1.Two operands are registers that are compared for equality
 2.One operand is a 16-bit off set used to compute the branch target address
relative to the branch instruction address.
 Ex: beq $t1,$t2,offset,
 To implement this instruction, must compute the branch target address
 Branch target address:
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 It is an address specified in a branch, which becomes the new program counter

(PC) if the branch is taken.
 If the operands are equal, the branch target address becomes the new PC, and it
is called as branch is taken.
 If the operands are not equal, the incremented PC should replace the current PC
and it is called as branch is not taken.
 The branch data path will perform two kinds of operations:
 Compute the branch target address
 Compare the register contents.
 To compute the branch target address, the branch data path includes a sign extension
unit
 To perform the compare, need to use the register file
 Adder circuit is used to compute the branch target and it is sum of the incremented PC
and sign extended lower 16 bits of the instruction shifted left 2 units.
 Control logic is used to decide whether the incremented PC or branch target should
replace the PC, based on the Zero output of the ALU.
 Shift left 2is simply a direction of the signals between input and output that adds 00two
to the low-order end of the sign-extended off set field

2.6 Creating a single data path

 By combining individual instruction class data path components can form a single data
path and add the control to complete the implementation.
 Single data path will execute all instructions in one clock cycle. In single data path if
any element needed more than once must be duplicated.
 The simple data path for the core MIPS architecture. is obtained by adding the data
path for instruction fetch and the data path from R-type instruction and memory
instructions and the data path for branches
 The branch instruction uses the main ALU for comparison of the register operands.
So need to use the adder circuit for the data path components of branch instruction
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 An additional multiplexor is required to select either the sequentially following

instruction address (PC + 4) or the branch target address to be written into the PC.
 To complete this simple data path, must add the control unit.
 The control unit must be able to take inputs and generate a write signal for each
state element, the selector control for each multiplexor, and the ALU control.
 The ALU control is different in a number of ways, and it will be useful to design it
first before design the rest of the control unit.
 The Simple data path for the core MIPS architecture by combining elements
required by different instruction classes as shown in

3.DESIGNING A CONTROL UNIT

A simple Implementation scheme is implementing all the data path elements required for
execution of all instruction classes with control units
3.1The ALU Control Unit
Depending on the instruction class, the ALU will need to perform one of these functions.
 Load word and store word instructions- ALU to compute the memory address by
addition.
 R-type instructions- ALU needs to perform one of the five actions (AND,OR, subtract,
add, or set on less than), depending on the value of the 6‑bit funct (or function) field
in the low-order bits of the instruction.
 Branch equal-ALU must perform a subtraction.
 We can generate the 4-bit ALU control input using a small control unit.
 It has input function field of the instruction and a 2-bit control field, called ALUOp.
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 ALUOp indicates three kinds of operations to be performed

1. add (00) for loads and stores,
2. subtract (01) for beq, or
3. determined by the operation encoded in the funct field (10).
 The output of the ALU control unit is a 4-bit signal that directly controls the ALU by
generating one of the 4-bit combinations.
 In figure shows how to set the ALU control inputs based on the 2 bit ALUOp control and
the 6‑bit function code
 When the ALuOP is 00 or 01, the ALU action does not depend on the function code
field.

 When the ALUOP value is 10, then the function code is used to set the ALU control
input.
 Multiple levels of decoding functions:
1. The main control unit generates the ALUOP bits.
2. ALUOP bit is used as a input to the ALU control.
3. That ALU control generates the actual signals to control the ALU unit.
 Mapping 2‑bit ALU Op field and 6‑bit funct field
 2‑bit ALUOp field and the 6‑bit funct field mapped 4-bit ALU control bits.
 There are 64 possible values are available for function field .
 The function field is used only when the ALUOP bits equal to 10.
 A small piece of logic that recognizes the subset of possible values and causes
the correct setting of the ALU control bits.
 Don’t-care term: An element of a logical function in which the output does not depend
on the values of all the inputs. Don’t-care terms may be specified in different ways.

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3.2 Designing the Main Control Unit:

 To understand how to connect the fields of an instruction to the data path, it is
useful to review the formats of the three instruction classes:
 Opcode: The field that denotes the operation and format of an instruction.
 3 instruction classes
 The R-type instruction classes,
 Branch instruction classes, and
 Load-store instruction classes
 Instruction format for load (opcode = 35ten) and store (opcode = 43ten) instructions.
 The register rs is the base register that is added to the 16-bit address field to
form the memory address.
 For load, rt is the destination register for the loaded value.
 For store rt is the source register whose value should be stored into memory.
 Instruction format for branch equal (opcode =4).
 The registers rs and rt are the source registers that are compared for equality.
 The 16-bit address field is sign-extended, shifted, and added to the PC + 4 to
compute the branch target address.
 There are several major observations about this instruction format:
 The op field, also called the opcode, is always contained in bits 31:26.
 The two registers to be read are always specified by the rs and rt fields, at
positions 25:21 and 20:16.The base register for load and store instructions is
always in bit positions 25:21 (rs).
 The 16‑bit offset for branch equal, load, and store is always in positions 15:0.
 The destination register is in one of two places. For a load it is in bit positions
20:16 (rt), For R-type it is in bit positions 15:11(rd).
 So we need to add a multiplexor to select which field of the instruction is used
to indicate the register number to be written.
 Using this information, we can add the instruction labels and extra multiplexor to
the simple datapath These additions plus the ALU control block, the write signals
forstate elements, the read signal for the data memory, and the control signals for
the multiplexors. Since all the multiplexors have two inputs, they each require a
single control line.
 Seven single bit control lines plus the 2‑bit ALUOp controlsignal. The ALU control
block has also been added. The PC does not require a write control,the branch control
logic determines whether it is written with the incremented PC or the branch target
address

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 When the 1‑bit control to a two-way multiplexor is asserted, the multiplexor

selects the input corresponding to 1. Otherwise, 0 input.
 Remember that the state elements all have the clock as an implicit input and that the
clock is used in controlling writes.

 Truth table for the control unit:

 Setting of the control lines depends only on the opcode and we have to define
whether each control signal should be 0,1 or don’t care (X) for each of the opcode
values.

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 R-Format:
 The first row of the table corresponds to the R-format instructions (add, sub, AND,
OR, and slt).
 For all these instructions, the source register fields are rs and rt, and the
destination register field is rd; this defines how the signals ALUSrc and RegDst
are set.
 R-type instruction writes a register (Reg-Write = 1), but neither reads nor writes
data memory.
 The ALUOp field for R-type instructions is set to 10 to indicate that the ALU
control should be generated from the funct field.
 Load Word and store word:
 The second and third rows of this table give the control signal settings for lw and
sw.
 These ALUSrc and ALUOp fi elds are set to perform the address calculation.
 The MemRead and MemWrite are set to perform the memory access.
 RegDst and RegWrite are set for a load to cause the result to be stored into the
rt register.
 Branch instruction:
 The branch instruction is similar to an R-format operation, since it sends the rs
and rt registers to the ALU.
 The ALUOp field for branch is set for a subtract (ALU control = 01), which is
used to test for equality. Notice that the MemtoReg field is irrelevant when the
RegWrite signal is 0: since the register is not being written, the value of the
data on the register data write port is not used.
 Thus, the entry MemtoReg in the last two rows of the table is replaced with X
for don’t care. Don’t cares can also be added to RegDst when RegWrite is 0.

4 .OPERATION OF THE DATA PATH

 R-type instruction operations in four steps:
1. In R-type instruction consider add $t1,$t2,$t3 and remaining four operations
(sub, AND, OR,slt) occurs in one clock cycle
2. The instruction is fetched, and the PC is incremented.
3. Two registers, $t2 and $t3, are read from the register file; also, the main control
unit computes the setting of the control lines during this step.
4. The ALU operates on the data read from the register file, using the function code
(bits 5:0, which is the funct field, of the instruction) to generate the ALU function.
5. The result from the ALU is written into the register file using bits 15:11 of the
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instruction to select the destination register ($t1).

 Load instruction operating in five steps:

1. An instruction is fetched from the instruction memory, and the PC is incremented.
2. A register ($t2) value is read from the register file.
3. The ALU computes the sum of the value read from the register file and the
sign-extended, lower 16 bits of the instruction (offset).
4. The sum from the ALU is used as the address for the data memory.
5. The data from the memory unit is written into the register file; the register
destination is given by bits 20:16 of the instruction ($t1).

 Branch-on-equal instruction operation in five steps:

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 beq, $t1, $t2, offset

 An instruction is fetched from the instruction memory, and the PC is incremented.
 Two registers, $t1 and $t2, are read from the register file. The data path in
operation for a branch-on-equal instruction.
 The ALU performs a subtract on the data values read from the register file. The
value of PC + 4.
 It is added to the sign-extended, lower 16 bits of the instruction (offset) shifted
left by two; the result is the branch target address.
 The Zero result from the ALU is used to decide which adder result to store into
the PC.

5 SIMPLE IMPLIMENTATION:
 Single cycle implementation also called single clock cycle implementation.
 Single cycle implementation is an instruction which is executed in one clock cycle.
 The jump instruction looks somewhat like a branch instruction but computes the
target PC differently and is not conditional.
 Like a branch, the low-order 2 bits of a jump address are always 00two.
 The next lower 26 bits of this 32-bit address come from the 26-bit immediate field in
the instruction.
 The upper 4 bits of the address that should replace the PC come from the PC of the
jump instruction plus 4.
 Thus, we can implement a jump by storing into the PC the concatenation of
 The upper 4 bits of the current PC + 4
 The 26-bit immediate field of the jump instruction
 The bits 00two

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 An additional multiplexor (at the upper right) is used to choose between the jump
target and either the branch target or the sequential instruction following this one.
 This multiplexor is controlled by the jump control signal.
 The jump target address is obtained by shifting the lower 26 bits of the jump
instruction left 2 bits, effectively adding 00 as the low-order bits, and then
concatenating the upper4 bits of PC + 4 as the high-order bits, thus yielding a 32-bit

address.
Why single cycle implementation is not used today?
Single cycle implementation is not used mostly because of the following reasons:
1. It is inefficient.
2. Clock cycle have same length for every instruction.
3. Overall performance is very poor because it has too long clock cycle.
6 CONTROL DESIGN TYPES
A control unit based on the received inputs generates control signals, which are then sent to
the central processor. The computer’s processor then tells the attached hardware what
operations to perform.

 Functions of the Control Unit –

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 It coordinates the sequence of data movements into, out of, and between a
processor’s many sub-units and data flow inside the processor.
 It interprets instructions.
 It receives external instructions or commands to which it converts to sequence of
control signals.
 It controls many execution units (i.e. ALU, data buffers and registers) contained
within a CPU.
 Types of Control Unit
 There are two types of control units:
1. Hardwired control unit
2. Micro programmable control unit.
6.1 Hardwired Control Unit
In the Hardwired control unit, the control signals are generated by specially designed
hardware logical circuits, the signal generation method cannot be modified without physical
change of the circuit structure.
 The circuit that generates specific sequences of control signals in response to the
supplied instruction
 The opcode of an instruction contains the basic data for control signal generation.
 In the instruction decoder, the operation code is decoded.
 The instruction decoder constitutes a set of many decoders that decode different
fields of the instruction opcode.
 As a result, few output lines going out from the instruction decoder obtains active
signal values.
 These output lines are connected to the inputs of the matrix that generates control
signals for executive units of the computer.
 This matrix implements logical combinations of the decoded signals from the
instruction opcode with the outputs from the matrix that generates signals
representing consecutive control unit states and with signals coming from the
outside of the processor, e.g. interrupt signals.
 The matrices are built in a similar way as a programmable logic arrays
 Control signals for an instruction execution are generated till the end of the
instruction execution cycle.
 A number of signals generated by the control signal generator matrix are sent back
to inputs of the next control state generator matrix.
 This matrix combines these signals with the timing signals

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 When a new instruction arrives at the control unit, the control units is in the initial
state of new instruction fetching.
 Instruction decoding allows the control unit enters the first state relating to
execution of the new instruction
 A change of any of the earlier mentioned signals stimulates the change of the
control unit state.
 When an external signal appears, (e.g. an interrupt) the control unit takes entry into
a next control state that is the state concerned with the reaction to this external
signal (e.g. interrupt processing).
 The values of flags and state variables of the computer are used to select suitable
states for the instruction execution cycle.
 The last states in the cycle are control states that commence fetching the next
instruction of the program: sending the program counter content to the main
memory address buffer register and next, reading the instruction word to the
instruction register of computer.
 When the ongoing instruction is the stop instruction that ends program execution,
the control unit enters an operating system state, in which it waits for a next user
directive.
 It is designed with usual goals of minimizing the number of components used and
maximizing the speed of operation.
 The control unit is implemented using hardware (gates, flip-flops, and counters).
 This circuit uses the bits from the Opcode field in our instructions, bits from the flag
(or status) register, signals from the bus, and signals from the clock. as inputs
 Advantages:
1. Hardwired Control Unit is fast.
2. Optimized design with low number of components and fast mode of operation.
3. Faster than micro- programmed control unit.
4. It does not require control memory.
Disadvantage
o Modifications or addition in the design is very difficult, complex and expensive.

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6.2. Micro programmable control unit

Microprogrammed control unit generates the control signals with the help of micro
instructions stored in control memory
 A program made up of microinstructions is used to carry out a series of micro-
operations. The control unit’s control memory stores a microprogram composed of
microinstructions. The creation of a set of control signals is dependent on the execution
of a microinstruction.
 Block diagram

 The microinstruction address is specified in the control address register.

 All the control information is saved in the control memory
 Control signals are generated by a program
 The micro-programmed control unit is slower in speed because of the time it takes to
fetch microinstructions from the control memory.
 Control Word: A control word is a word whose individual bits represent various control
signals. A control word in the microinstruction specifies one or multiple micro-
operations for a data processor. The control signals associated with operations are
stored in special memory units inaccessible by the programmer as Control Words.
 Micro-routine: A sequence of control words corresponding to the control sequence of
a machine instruction constitutes the micro-routine for that instruction.
 Micro-instruction: Individual control words in this micro-routine are referred to as
microinstructions. The microinstruction specifies one or more micro operations for the
system
 Micro-program: A sequence of micro-instructions is called a micro-program which is
stored in Control Memory (CM).
 Control Memory:A memory that is part of a control unit is referred to as a control
memory
 Control Store: the micro-routines for all instructions in the instruction set of a
computer are stored in a special memory called the Control Store.
Control Register: The microinstruction received from memory is stored in the control register.
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 A more advanced development known as dynamic microprogramming permits a micro

program to be loaded initially from an auxiliary memory such as a magnetic disk.
 Control units that use dynamic microprogramming employ a writable control memory
 The next address is calculated in the circuit of the next address generator and then
transferred to the control address register for reading the next microinstruction when
the micro-operations are being executed.
 Because it determines the sequence of addresses received from control memory, the
next address generator is also known as a microprogram sequencer.
 The control memory address register specifies the address of the microinstruction and
the control data register holds the microinstruction read from memory the
microinstruction contains a control word that specifies one or more micro operations
for the data processor.
 While the micro operations are being executed, the next address is computed in the
next address generator circuit and then transferred into the control address register to
read the next microinstruction.
 The address sequencing capabilities required in a control memory are:
 1. Incrementing of the control address register.
 2. Unconditional branch or conditional branch, depending on status bit
conditions.
 3. A mapping process from the bits of the instruction to an address for control
memory.
 4. A facility for subroutine call and return.
 Advantages:
 No change required once hardware configuration is established, if needed micro
program can be changed

6.2.1With a single-level control store:

 the instruction opcode from the instruction register is sent to the control store address
register.
 Based on this address, the first microinstruction of a microprogram that interprets
execution of this instruction is read to the microinstruction register.
 This microinstruction contains in its operation part encoded control signals, normally as
few bit fields. In a set microinstruction field decoders, the fields are decoded.
 The microinstruction also contains the address of the next microinstruction of the given
instruction microprogram and a control field used to control activities of the
microinstruction address generator.

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 The last microinstruction in the instruction of the given microprogram is the

microinstruction that fetches the next instruction from the main memory to the
instruction register.

6.2.2With a two-level control store :

 In this, in a control unit with a two-level control store, besides the control memory for
microinstructions, a Nano-instruction memory is included.
 microinstructions do not contain encoded control signals.
 The operation part of microinstructions contains the address of the word in the Nano-
instruction memory, which contains encoded control signals.
 The Nano-instruction memory contains all combinations of control signals that appear
in microprograms that interpret the complete instruction set of a given computer,
written once in the form of Nano-instructions.
 The microinstruction memory contains the control for selection of consecutive
microinstructions, while those control signals are generated at the basis of Nano-
instructions.
 In Nano-instructions, control signals are frequently encoded using 1 bit/ 1 signal
method that eliminates decoding

7.PIPELINING
Pipelining is an implementation technique in which multiple instructions are executed
simultaneously by overlapping them in execution. Ie Multiple instructions are executed
simultaneously to save time
 A technique used in advanced microprocessors where the microprocessor begins
executing a second instruction before the first has been completed. –
 A Pipeline is a series of stages, where some work is done at each stage and the work
is not finished until it has passed through all stages
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 With pipelining, the computer architecture allows the next instructions to be fetched
while the processor is executing an instruction
 How Pipelines Works :
 The pipeline is divided into segments and each segment can execute its operation
concurrently with the other segments.
 Once a segment completes an operation, it passes the result to the next segment
in the pipeline and fetches the next operations from the preceding segment.
 The pipelined approach takes much less time since all steps—called stages in
pipelining are executed concurrently.
 If all the stages take about the same amount of time then the speed-up due to
pipelining is equal to the number of stages in the pipeline,
 In this way, the number of operations performed per second is increased even
though the elapsed time needed to perform anyone operation is not changed.
 Pipelining is a particularly effective way of organizing concurrent activity in a
computer system.
 Pipelining improves performance by increasing instruction throughput
 Thus the overall performance of the processor is improved both in terms of resource
utilization and throughput
7.1Stages in MIPS Pipelining
1. Instruction Fetch(IF): Fetch instruction from memory.
2. Instruction Decode(ID):Read registers while decoding the instruction. The
regular format of MIPS instructions allows reading and decoding to occur
simultaneously.
3. Excute(Ex):Execute the operation or calculate an address
4. Memory Access(MEM):Access an operand in data memory.
5. Write Back(WB)Write the result into a register

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7.2 MIPS Designing Instruction sets for Pipelining

 The MIPS instructions are of same length that makes easier to fetch instructions in
the first pipeline stage and to decode them in the second stage.
 MIPS has only a few instruction formats, with the source register fields being located
in the same place in each instruction allows reading the register file at the same time
 Memory operands only appear in loads or stores this allows execute stage to
calculate the memory address and then access memory in the stages as address stage,
memory stage, and then execute stage.
 operands must be aligned in memory. hence a single data transfer instruction
requiring two data memory accesses can be in a single pipeline stage.

7.3Pipelined Datapath
 The division of an instruction into five stages means a five-stage pipeline in which up
to five instructions will be in execution during any single clock cycle.
 Thus, the single cycle datapath is separated to five pieces, with each piece named
corresponding to a stage of instruction execution:
1. IF: Instruction fetch
2. ID: Instruction decode and register fi le read
3. EX: Execution or address calculation
4. MEM: Data memory access
5. WB: Write back
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Figure: the single-cycle datapath with the pipeline stages identified

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 The five components correspond roughly to the way the datapath is drawn;
instructions and data move generally from left to right through the five stages as they
complete execution.
 There are, however, two exceptions to this left -to-right flow of instructions:
 The write-back stage, which places the result back into the register fi le in the
middle of the datapath
 The selection of the next value of the PC, choosing between the incremented
PC and the branch address from the MEM stage
 Data flowing from right to left does not aff ect the current instruction; these reverse
data movements influence only later instructions in the pipeline. Note that the fi rst
right-toleft flow of data can lead to data hazards and the second leads to control
hazards. ❖
 One way to show what happens in pipelined execution is to pretend that each
instruction has its own datapath, and then to place these datapaths on a timeline to
show their relationship.
Figure: Instructions being executed using the single-cycle datapath assuming pipelined
execution.

 shows, the instruction memory is used during only one of the five stages of an
instruction, allowing it to be shared by following instructions during the other four
stages.
 To retain the value of an individual instruction for its other four stages, the value read
from instruction memory must be saved in a register.
 Below figure shows the pipelined datapath with the pipeline registers highlighted. All

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instructions advance during each clock cycle from one pipeline register to the next.
The registers are named for the two stages separated by that register.
 For example, the pipeline register between the IF and ID stages is called IF/ID. Notice
that there is no pipeline register at the end of the write-back stage.
 All instructions must update some state in the processor—the register file, memory,
or the PC.

7.3.1Execution of load instruction in a pipelined datapath

The five stages are the following:
1. Instruction fetch: The top portion of Figure shows the instruction being read from
memory using the address in the PC and then being placed in the IF/ID pipeline register. The
PC address is incremented by 4 and then written back into the PC to be ready for the next
clock cycle.
2. Instruction decode and register file read: The bottom portion of Figure shows the
instruction portion of the IF/ID pipeline register supplying the 16-bit immediate field, which
is sign-extended to 32 bits, and the register numbers to read the two registers. All three
values are stored in the ID/EX pipeline register, along with the incremented PC address.
3. Execute or address calculation: Figure shows that the load instruction reads the contents
of register 1 and the sign-extended immediate from the ID/EX pipeline register and adds
them using the ALU. That sum is placed in the EX/MEM pipeline register

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FIGURE IF and ID: First and second pipe stages of an instruction with the active portions of
the datapath highlighted

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FIGURE EX: The third pipe stage of a load instruction, highlighting the portions of the
datapath

4. Memory access: The top portion of Figure shows the load instruction reading the data
memory using the address from the EX/MEM pipeline register and loading the data into the
MEM/WB pipeline register.
5. Write-back: The bottom portion of Figure shows the final step: reading the data from the
MEM/WB pipeline register and writing it into the register file in the middle of the figure.
This walk-through of the load instruction shows that any information needed in a later pipe
stage must be passed to that stage via a pipeline register
FIGURE MEM and WB: The fourth and fifth pipe stages of a load instruction, highlighting
the portions of the datapath

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7.3.2 Execution of store instruction in a pipelined datapath

five pipe stages of the store instruction:
1. Instruction fetch: The instruction is read from memory using the address in the PC and
then is placed in the IF/ID pipeline register. This stage occurs before the instruction is
identified, so the top portion of Figure 3.25 works for store as well as load.
2. Instruction decode and register file read: The instruction in the IF/ID pipeline register
supplies the register numbers for reading two registers and extends the sign of the 16-bit
immediate. These three 32-bit values are all stored in the ID/EX pipeline register. The bottom
portion of Figure for load instructions also shows the operations of the second stage for
stores. These first two stages are executed by all instructions, since it is too early to know the
type of the instruction.
3. Execute and address calculation: the effective address is placed in the EX/MEM pipeline
register.
4. Memory access: The top portion of Figure shows the data being written to memory. Note
that the register containing the data to be stored was read in an earlier stage and stored in
ID/EX. The only way to make the data available during the MEM stage is to place the data into
the EX/MEM pipeline register in the EX stage, just as we stored the effective address into
EX/MEM. instruction.
5. Write-back: The bottom portion of Figure shows the final step of the store. For this
instruction, nothing happens in the write-back stage. For the store instruction we needed to
pass one of the registers read in the ID stage to the MEM stage, where it is stored in memory.
The data was first placed in the ID/EX pipeline register and then passed to the EX/MEM
pipeline register.
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7.4 Pipelined Control

Adding control to the pipelined datapath is referred to as pipelined control. It views the
problem through pipeline bars in between the stages.
The control lines are divided into fi ve groups according to the pipeline stage.
1. Instruction fetch: Th e control signals to read instruction memory and to write the PC are
always asserted, so there is nothing special to control in this pipeline stage.
2. Instruction decode/register fi le read: As in the previous stage, the same thing happens at
every clock cycle, so there are no optional control lines to set.
3. Execution/address calculation: Th e signals to be set are RegDst, ALUOp, and ALUSrc (see
Figures 4.47 and 4.48). Th e signals select the Result register, the ALU operation, and either
Read data 2 or a sign-extended immediate for the ALU.
4. Memory access: Th e control lines set in this stage are Branch, MemRead, and MemWrite.
Th e branch equal, load, and store instructions set these signals, respectively. Recall that
PCSrc in Figure 4.48 selects the next sequential address unless control asserts Branch and the
ALU result was 0.
5. Write-back: Th e two control lines are MemtoReg, which decides between sending the ALU
result or the memory value to the register fi le, and RegWrite, which writes the chosen value
Control signals

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8. HAZARDS
Hazards are situations that prevent the next instruction in the instruction cycle from being
executed during its designated clock cycle. Hazards reduce the performance of the Pipelining
 3 Types of hazard
1.Structural hazard.
2.Data hazard
3.Control hazard
8.1 Structural Hazard
 Structural Hazard occurs when a planned instruction cannot be executed in the proper
clock cycle because the hardware does not support the combination of instructions
that are set to execute.
 MIPS instruction set was designed to be pipelined, making it fairly easy for designers to
avoid structural hazards when designing a pipeline.
 However, If the pipeline in below Figure had a fourth instruction in the same clock cycle
the first instruction is accessing data from memory while the fourth instruction is
fetching an instruction from that same memory. Without two memories, this pipeline
could have a structural hazard.

8.2 Data Hazards

 It is called a pipeline data hazard, When a planned instruction cannot execute in the
proper clock cycle because data that is needed to execute the instruction is not yet
available.
 Data hazards occur when the pipeline must be stalled because one step must wait for
another to complete.
 In a computer pipeline, data hazards arise from the dependence of one instruction on
an earlier one that is still in the pipeline.
 Example: suppose we have an add instruction followed immediately by a subtract
instruction that uses the sum ($s0):
add $s0, $t0, $t1
sub $t2, $s0, $t3
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 Here the sub instruction uses the result of add instruction($s0). The add instruction
cannot write its result until the fifth stage. This result is wasting 3 clock cycle
 Since the stall occurs due to the non-availability of data, this is termed as data hazard.
 a data hazard could severely stall the pipeline.
 Figure below shows the connection to forward the value in $s0 after the execution
stage of the add instruction as input to the execution stage of the sub instruction.

Solutions to data hazard

1)forwarding or bypassing.
 Forwarding also called Bypassing is a method of resolving data hazard by retrieving the
missing data element from internal buffer rather than waiting for it to arrive from
programmer.
 This can be done by adding extra memory element or hardware that acts as an internal
buffer
 Forwarding paths are valid only if the destination stage is later in time than the source
stage. For example, there cannot be a valid forwarding path from the output of the
memory access stage in the first instruction to the input of the execution stage of the
following, since that would mean going backward in time.
 Forwarding cannot prevent all pipeline stalls
 Consider the following code
lw $s0, 20($t1)
sub $t2, $s0, $t3
 Here the desired data would be available only after the fourth stage of the first
instruction in the dependence, which is too late for the input of the third stage of sub
instruction.
 Hence even with forwarding, there will be hazard called as load use data hazard
 Load use data hazard- A specific form of data hazard in which the data requested by an
load instruction has not yet become available when it is requested

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 Even with forwarding, we would have to stall one stage for a load-use data hazard,
 Stalling A pipeline stall (also called bubble) is a delay in execution of an instruction in
order to resolve a hazard
 Problem :Reordering Code to Avoid Pipeline Stalls
Consider the following code segment in C:
a = b + e;
c = b + f;
 MIPS code for this segment, assuming all variables are in memory and are
addressable as off sets from $t0:
lw $t1, 0($t0)
lw $t2, 4($t0)
add $t3, $t1,$t2
sw $t3, 12($t0)
lw $t4, 8($t0)
add $t5, $t1,$t4
sw $t5, 16($t0)
 Find the hazards in the above code segment and reorder the instructions to
avoid any pipeline stall
 Both add instructions have a hazard because of their respective dependence on
the immediately preceding lw instruction. Notice that bypassing eliminates
several other potential hazards, including the dependence of the first add on the
first lw and any hazards for store instructions. Moving up the third lw instruction
to become the third instruction eliminates both hazards:
lw $t1, 0($t0)
lw $t2, 4($t0)
lw $t4, 8($t0)
add $t3, $t1, $t2

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sw $t3 12($t0)
add $t5, $t1,$t4
sw $t5, 16($t0)
.
8.3 Control Hazards
 Ths is also called as branch hazard, when the proper instruction cannot execute in the
proper pipeline clock cycle because the instruction that was fetched is not the one that
is needed, ie the flow of instruction addresses is not what the pipeline expected.
 A control hazard, arising from the need to make a decision based on the results of one
instruction while others are executing.
 If a branch instruction comes, the pipeline fetches it but cannot possibly know what the
next instruction should be, since it only just received the branch instruction from
memory.
 Control hazard occurs less than data hazard, nothing is effective as forwarding to data
hazard.
 Solution for Control Hazard
1. Pipeline Stall cycles
2. Branch delay slots
3. Branch predictors

8.3.1Stalling:
 One possible solution is to stall immediately after a branch is fetched, waiting until the
pipeline determines the outcome of the branch and knows what instruction address to
fetch from. Stalling the instruction until the branch is complete is too slow
 That an extra hardware can test registers, calculate the branch address, and update the
PC during the second stage of the pipeline

.
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 Even with this extra hardware, It cannot resolve the branch in the second stage as it is
often the case for longer pipelines and it is too high cost for more computers
 So need to focus on another method to resolve the control hazard that is called branch
prediction
8.3.2Delayed Branched
 MIPS processors use a branch delay slot to eliminate single-cycle stalls after branches.
 The instruction after a conditional branch is always executed , whether the branch is
taken or not!
 The effect is to execute one or more instructions following the conditional branch
before the branch is taken.
 the assembler automatically arrange the instruction to get the branch
 The branch performance is to reduce the cost of the taken branch
 Efficient for small pipelines, inefficient for long pipeline
 Moving the branch decision up requires two actions to occur earlier
1. Computing the Branch Target Address
2. Evaluating the branch decision
8.3.3Branch Prediction
 A method of resolving a branch hazard that assumes a given outcome for the branch
and proceeds from that assumption rather than waiting to ascertain the actual
outcome
 One improvement over branch stalling is to predict that the branch will not be taken
and thus continue the execution of instructions
Figure shows the Pipeline when the branch is Taken/not Taken

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 If branches are untaken,half the time and if it costs little to discard the instructions,
this optimization halves the cost of control hazard
 If the branch is taken, the instructions that are being fetched and decoded must be
discarded, execution continues at branch target
 2 Types: static and dynamic
 Static Branch Prediction:A more sophisticated version of branch prediction
would have some branches predicted as taken and some as untaken. In the
case of programming, at the bottom of loops are branches that jump back to
the top of the loop. Always predict taken for branches that jump to an earlier
address.
 Dynamic Branch Prediction
 Prediction of branches at runtime using runtime information is called
dynamic branch prediction
 One approach is to look up the address of the instruction to see if a branch
was taken the last time this instruction was executed, and, if so, to begin
fetching new instructions from the same place as the last time. This
technique is called dynamic branch prediction.
 A branch prediction buffer is a small memory indexed by the lower portion
of the address of the branch instruction The memory contains a bit that says
whether the branch was recently taken or not
 Dynamic hardware predictors make their guesses depending on the
behavior of each branch and may change predictions for a branch over the
life of a program.
 adjusting the next prediction depending on the success of recent guesses.
One popular approach to dynamic prediction of branches is keeping a
history for each branch as taken or untaken, and then using the recent past
behavior to predict the future.
 2 Types
1. One-bit prediction scheme
2 States : Taken or Not Taken

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 If branch is taken, the state change from NotTaken to Taken , otherwise

remain in Not Taken
 Th is simple 1-bit prediction scheme has a performance shortcoming:
even if a branch is almost always taken, we can predict incorrectly twice,
rather than once, when it is not taken. Th e following example shows this
dilemma.
2 Two-bit prediction scheme
 In a 2-bit scheme, a prediction must be wrong twice before it is
changed. A branch prediction buff er can be implemented as a small,
special buff er accessed with the instruction address during the IF
pipe stage.
 If the instruction is predicted as taken, fetching begins from the
target as soon as the PC is known, it can be as early as the ID stage.
Otherwise, sequential fetching and executing continue. If the
prediction turns out to be wrong, the prediction bits are changed

9.Exceptions in MIPS
 Exceptions and interrupts are unexpected events that disrupt the normal flow of
instruction execution.
 An exception is an unexpected event from within the processor. An interrupt is an
unexpected event from outside the processor.
 Exception and interrupt handling is implemented multicycle CPU design.
 Events that trigger exceptions and interrupt
 Arithmetic overflow occurs during the execution of an add, addi, or sub
instruction. If the result of the computation is too large or too small to hold in
the result register, the Overflow output of the ALU will become high during the
execute state. This event triggers an exception.
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 Undefined instruction occurs when an unknown instruction is fetched. This

exception is caused by an instruction in the IR that has an unknown opcode or an
R-type instruction that has an unknown function code.
 Systemcall occurs when the processor executes
a syscall instruction. Syscall instructions are used to implement operating system
services (functions).
 I/O Request
 Break Point
 Page Fault
 Misaligned memory access
 Memory Protection violation
 Hardware failure
 What to do when an exception or interrupt occurs
 When an exception or interrupt occurs, The processor may perform the
following actions:
 The pipeline has to stop executing
 Let all the preceeding instruction to complete
 Flush all succeeding instruction
 move the current PC into another register, call the EPC
 record the reason for the exception in the Cause register
 automatically disable further interrupts or execptions from occuring, by left-
shifting the Status register
 change control (jump) to a hardwired exception handler address
 To return from a handler, your processor may perform the following actions:
o move the contents of the EPC register to the PC.
o re-enable interrupts and exceptions, by right-shifting the Status register

PART -A
1.Define Instruction execution
The execution of an instruction in a processor can be split up into a number of stages. How
many stages there are, and the purpose of each stage is different for each processor design.

2.Write the MIPS pipeline stages of instruction Execution

6. IF:The Instruction Fetch stage fetches the next instruction from memory using the
address in the PC (Program Counter) register and stores this instruction in the IR
(Instruction Register)
7. ID:The Instruction Decode stage decodes the instruction in the IR, calculates the
next PC, and reads any operands required from the register file.
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8. EX:The Execute stage "executes" the instruction. In fact, all ALU operations are done
in this stage. (The ALU is the Arithmetic and Logic Unit and performs operations
such as addition, subtraction, shifts left and right, etc.)
9. MA:The Memory Access stage performs any memory access required by the current
instruction, So, for loads, it would load an operand from memory. For stores, it
would store an operand into memory. For all other instructions, it would do nothing.
10.WB:Write Back For instructions that have a result (a destination register), the Write
Back writes this result back to the register file. Note that this includes nearly all
instructions, except nops (a nop, no-op or no-operation instruction simply does
nothing) and s (stores).

3.List the 3 classes of instructions in MIPS

4. The memory-reference instructions load word (lw) and store word (sw)
5. The arithmetic-logical instructions add, sub, AND, OR, and slt
6. The instructions branch equal (beq) and jump (j)

4.List the types of datapath

 Single-cycle Datapath: Each instruction executes in a single cycle
 Multi-cycle Datapath: Each instruction is broken up into a series of shorter steps
 Pipelined Datapath: Each instruction is broken up into a series of steps; Multiple
instructions execute at once

5.Differences between single cycle and multi cycle datapath

Single cycle Data Path: Multi-cycle Data Path:
Each instruction is processed in Divide the processing of each instruction into 5
one (long) clock cycle stages and allocate one clock cycle per stage
Two separate memory units for Single memory unit for both instructions and
instructions and data. data

6.Define Data path Element:

 It is a unit used to operate on or hold data within a processor.
 In the MIPS implementation, the data path elements includes
5. The instruction and data memories
6. The register file
7. The ALU
8. Adders.
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7. Define Instruction memory:

 The instruction memory need only provide read access because the data path
does not write instructions.
 The instruction memory is called as combinational element because it will
perform only read access.
 The output at any time reflects the contents of the location specified by the
address input,
 No read control signal is needed.
8.What is Program Counter?
 The program counter is a 32-bit register that is written at the end of every clock
cycle
 Does not need a write control signal.
9.What is Fetching Phase?
 To execute any instruction, must start by fetching the instruction from memory.
 To prepare for executing the next instruction, must also increment the program
counter
 So that it points at the next instruction, 4 bytes (PC+4).

10.What is Register File?

 A register file is a state element that contains set of registers that can be read or
written by specifying the number to be accessed.
 The register file contains the register state of the computer.

11.Write Memory reference instructions

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 lw $t1,offset_value($t2)
 2.sw $t1,offset_value ($t2).
12.What is Data Memory unit?
 The memory unit is a state element with inputs for the address and the write
data.
 It produces a single output for the read result.
 Data Memory unit has separate read and write control lines for read and write
operation.
 Register file does not require read signal but memory unit needs a read signal
 Because the register file, reading the value of an invalid address can cause
problems.
13.Define Sign Extension unit
 The sign extension unit has a 16-bit data input and that sign-extended into a 32-
bit result.
14.What is Branch target address?
 It is an address specified in a branch, which becomes the new program counter
(PC) if the branch is taken.
 If the operands are equal, the branch target address becomes the new PC, and it
is called as branch is taken.
 If the operands are not equal, the incremented PC should replace the current PC
and it is called as branch is not taken.

15.Why single cycle implementation is not used today?

Single cycle implementation is not used mostly because of the following reasons:
4. It is inefficient.
5. Clock cycle have same length for every instruction.
6. Overall performance is very poor because it has too long clock cycle.
16.What is a control unit
A control unit based on the received inputs generates control signals, which are then sent to
the central processor. The computer’s processor then tells the attached hardware what
operations to perform.

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17. Write the Functions of the Control Unit –

 It coordinates the sequence of data movements into, out of, and between a
processor’s many sub-units and data flow inside the processor.
 It interprets instructions.
 It receives external instructions or commands to which it converts to sequence of
control signals.
 It controls many execution units (i.e. ALU, data buffers and registers) contained
within a CPU.
18.Write the Types of Control Unit
 There are two types of control units:
3. Hardwired control unit
4. Micro programmable control unit.
17.Define Hardwired Control Unit
In the Hardwired control unit, the control signals are generated by specially designed
hardware logical circuits, the signal generation method cannot be modified without physical
change of the circuit structure. The circuit that generates specific sequences of control signals
in response to the supplied instruction

18.Write the Advantages and Disadvantages of Hardwires Control Unit

 Advantages:
5. Hardwired Control Unit is fast.
6. Optimized design with low number of components and fast mode of operation.
7. Faster than micro- programmed control unit.
8. It does not require control memory.
Disadvantage
o Modifications or addition in the design is very difficult, complex and expensive.
o
19.Define Micro programmable control unit
Microprogrammed control unit generates the control signals with the help of micro
instructions stored in control memory
A program made up of microinstructions is used to carry out a series of micro-operations. The
control unit’s control memory stores a microprogram composed of microinstructions. The
creation of a set of control signals is dependent on the execution of a microinstruction.

20.Define Pipelining
Pipelining is an implementation technique in which multiple instructions are executed
simultaneously by overlapping them in execution. Ie Multiple instructions are executed
simultaneously to save time
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A Pipeline is a series of stages, where some work is done at each stage and the work is not
finished until it has passed through all stages
Types: Instruction Pipeline and Arithmetic Pipeline
.
21.What is a Hazard
Hazards are situations that prevent the next instruction in the instruction cycle from being
executed during its designated clock cycle. Hazards reduce the performance of the Pipelining
 3 Types of hazard
4.Structural hazard.
5.Data hazard
6.Control hazard
22.Define Structural Hazard
 Structural Hazard occurs when a planned instruction cannot be executed in the proper
clock cycle because the hardware does not support the combination of instructions
that are set to execute.

23 Define Data Hazards
 It is called a pipeline data hazard, When a planned instruction cannot execute in the
proper clock cycle because data that is needed to execute the instruction is not yet
available.
 Data hazards occur when the pipeline must be stalled because one step must wait for
another to complete.
 In a computer pipeline, data hazards arise from the dependence of one instruction on
an earlier one that is still in the pipeline.
 Example: suppose we have an add instruction followed immediately by a subtract
instruction that uses the sum ($s0):
add $s0, $t0, $t1
sub $t2, $s0, $t3
24. Write solutions to data hazard
1) forwarding or bypassing.
2) Stalling
3) Reordering Code to Avoid Pipeline Stalls
25 What is Control Hazards
 Ths is also called as branch hazard, when the proper instruction cannot execute in the
proper pipeline clock cycle because the instruction that was fetched is not the one that
is needed, ie the flow of instruction addresses is not what the pipeline expected.
 A control hazard, arising from the need to make a decision based on the results of one
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instruction while others are executing.

26 Write Solution for Control Hazard
4. Pipeline Stall cycles
5. Branch delay slots
6. Branch predictors
27.Define Branch Prediction
 A method of resolving a branch hazard that assumes a given outcome for the branch
and proceeds from that assumption rather than waiting to ascertain the actual
outcome
 One improvement over branch stalling is to predict that the branch will not be taken
and thus continue the execution of instructions
28.List Types: static and dynamic
 Static Branch Prediction:A more sophisticated version of branch prediction
would have some branches predicted as taken and some as untaken. In the
case of programming, at the bottom of loops are branches that jump back to
the top of the loop. Always predict taken for branches that jump to an earlier
address.
 Dynamic Branch Prediction
 Prediction of branches at runtime using runtime information is called
dynamic branch prediction
29.Define Branch Prediction Buffer
A branch prediction buffer is a small memory indexed by the lower portion of the address of
the branch instruction The memory contains a bit that says whether the branch was
recently taken or not
30.What are exceptions in MIPS
Exceptions and interrupts are unexpected events that disrupt the normal flow of instruction
execution.
An exception is an unexpected event from within the processor. An interrupt is an
unexpected event from outside the processor.

31 Define branch penalty.

The time lost as a result of a branch instruction is often referred to as the branch penalty.
This will cause the pipeline to stall. So we can reduce branch penalty by calculating the
branch address in early stage.

32 What is meant by branch folding and what is the condition to implement it?
The instruction fetch unit has executed the branch instruction concurrently with in the
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execution of other instructions is called branch folding.

This occurs only if at the time of branch is encountered at least one instruction is available
in the queue than the branch instruction.

33.What is meant by delay branch slot?

A location following branch instruction is called as branch delay slot. There may be more
than one branch delay slot, depending on the execution time.
The instruction in the delay slot is always fetched and at least partially executes before the
branch decision is made.

34. Define delayed branching.

It is a technique by using it we can handle the delay branch slot instructions. We can place
some useful instruction in the branch delay slot and execute these instruction s when the
processor is executing the branch instruction.
If there is no useful instruction in the program we can simply place NOP instruction in delay
slot. This technique will minimize the branch penalty.

PART B
1.Explain the building data path in detail with data path segment for 3 instruction classes
2.Explain the control design unit in detail
3. Write in detail about i)Hardwired control ii)Microprogrammed control
4.what is Pipelining? Explain in detail
5.Write about pipelined datapath and control in detail
6.Define Hazards.What are the types of Hazards?Explain in detail

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