UNIT 1 8086 MICROPROCESSOR

8086 Architecture – Memory interfacing–I/O ports and data transfer concepts – Timing Diagram –
Interrupt structure- DMA - Instruction set and addressing modes - Interfacing: 8255 PPI,
8279Keyboard display controller, and 8254 Timer/Counter.

INTRODUCTION
What is a Microprocessor?

Computer's Central Processing Unit (CPU) built on a single Integrated Circuit (IC) is called
a microprocessor.

A digital computer with one microprocessor which acts as a CPU is called microcomputer.

It is a programmable, multipurpose, clock -driven, register-based electronic device that reads

binary instructions from a storage device called memory, accepts binary data as input and
processes data according to those instructions and provides results as output.

The microprocessor contains millions of tiny components like transistors, registers, and diodes that
work together.

Evolution of Microprocessors

We can categorize the microprocessor according to the generations or according to the size of the
microprocessor:

First Generation (4 - bit Microprocessors)

The first generation microprocessors were introduced in the year 1971-1972 by Intel Corporation.
It was named Intel 4004 since it was a 4-bit processor.

It was a processor on a single chip. It could perform simple arithmetic and logical operations such
as addition, subtraction, Boolean OR and Boolean AND.

I had a control unit capable of performing control functions like fetching an instruction from
storage memory, decoding it, and then generating control pulses to execute it.

Second Generation (8 - bit Microprocessor)

The second generation microprocessors were introduced in 1973 again by Intel. It was a first 8 -
bit microprocessor which could perform arithmetic and logic operations on 8-bit words. It was
Intel 8008, and another improved version was Intel 8088.
Third Generation (16 - bit Microprocessor)

The third generation microprocessors, introduced in 1978 were represented by Intel's 8086, Zilog
Z800 and 80286, which were 16 - bit processors with a performance like minicomputers.

Fourth Generation (32 - bit Microprocessors)

Several different companies introduced the 32-bit microprocessors, but the most popular one is
the Intel 80386.

Fifth Generation (64 - bit Microprocessors)

From 1995 to now we are in the fifth generation. After 80856, Intel came out with a new processor
namely Pentium processor followed by Pentium Pro CPU, which allows multiple CPUs in a
single system to achieve multiprocessing.

Other improved 64-bit processors are Celeron, Dual, Quad, Octa Core processors.

Basic Terms used in Microprocessor

Here is a list of some basic terms used in microprocessor:

Instruction Set - The group of commands that the microprocessor can understand is called
Instruction set. It is an interface between hardware and software.
Bus - Set of conductors intended to transmit data, address or control information to different
elements in a microprocessor. A microprocessor will have three types of buses, i.e., data bus,
address bus, and control bus.
IPC (Instructions Per Cycle) - It is a measure of how many instructions a CPU is capable of
executing in a single clock.
Clock Speed - It is the number of operations per second the processor can perform. It can be
expressed in megahertz (MHz) or gigahertz (GHz). It is also called the Clock Rate.
Bandwidth - The number of bits processed in a single instruction is called Bandwidth.
Word Length - The number of bits the processor can process at a time is called the word length
of the processor. 8-bit Microprocessor may process 8 -bit data at a time. The range of word length
is from 4 bits to 64 bits depending upon the type of the microcomputer.
Data Types - The microprocessor supports multiple data type formats like binary, ASCII, signed
and unsigned numbers.
 Working of Microprocessor

The microprocessor follows a sequence to execute the instruction: Fetch, Decode, and then
Execute.
Initially, the instructions are stored in the storage memory of the computer in sequential order. The
microprocessor fetches those instructions from the stored area (memory), then decodes it and
executes those instructions till STOP instruction is met. Then, it sends the result in binary form to
the output port. Between these processes, the register stores the temporary data and ALU
(Arithmetic and Logic Unit) performs the computing functions.

Features of Microprocessor

o Low Cost - Due to integrated circuit technology microprocessors are available at very low cost. It
will reduce the cost of a computer system.
o High Speed - Due to the technology involved in it, the microprocessor can work at very high
speed. It can execute millions of instructions per second.
o Small Size - A microprocessor is fabricated in a very less footprint due to very large scale and
ultra large scale integration technology. Because of this, the size of the computer system is reduced.
o Versatile - The same chip can be used for several applications, therefore, microprocessors are
versatile.
o Low Power Consumption - Microprocessors are using metal oxide semiconductor technology,
which consumes less power.
o Less Heat Generation - Microprocessors uses semiconductor technology which will not emit
much heat as compared to vacuum tube devices.
o Reliable - Since microprocessors use semiconductor technology, therefore, the failure rate is very
less. Hence it is very reliable.
o Portable - Due to the small size and low power consumption microprocessors are portable.
 Block diagram of a Microcomputer

Architecture of 8086 :

8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit)
and BIU (Bus Interface Unit).

ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.
FLAG REGISTER
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result
stored in the accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags and
Control Flags.

Bits D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Flags O D I T S Z AF P CY

CONDITIONAL FLAGS
It represents the result of the last arithmetic or logical instruction executed. Following is the list of
conditional flags −

• Carry flag − This flag indicates an overflow condition for arithmetic operations.
• Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow from
lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry
given by D3 bit to D4 is AF flag. The processor uses this flag to perform binary to BCD
conversion.
• Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order
8-bits of the result contains even number of 1’s, then the Parity Flag is set. For odd number
of 1’s, the Parity Flag is reset.
• Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero
else it is set to 0.
• Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is
negative, then the sign flag is set to 1 else set to 0.
• Overflow flag − This flag represents the result when the system capacity is exceeded.

CONTROL FLAGS
Control flags controls the operations of the execution unit. Following is the list of control flags −
• Trap flag − It is used for single step control and allows the user to execute one instruction
at a time for debugging. If it is set, then the program can be run in a single step mode.
 • Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the
interruption of a program. It is set to 1 for interrupt enabled condition and set to 0 for
interrupt disabled condition.
• Direction flag − It is used in string operation. As the name suggests when it is set then string
bytes are accessed from the higher memory address to the lower memory address and vice-
a-versa.

GENERAL PURPOSE REGISTER

There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers
can be used individually to store 8-bit data and can be used in pairs to store 16bit data. The valid
register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to the AX,
BX, CX, and DX respectively.

• AX register − It is also known as accumulator register. It is used to store operands for

arithmetic operations.
• BX register − It is used as a base register. It is used to store the starting base address of the
memory area within the data segment.
• CX register − It is referred to as counter. It is used in loop instruction to store the loop
counter.
• DX register − This register is used to hold I/O port address for I/O instruction.

STACK POINTER REGISTER

It is a 16-bit register, which holds the address from the start of the segment to the memory
location, where a word was most recently stored on the stack.

BIU (Bus Interface Unit)

BIU takes care of all data and addresses transfers on the buses for the EU like sending
addresses, fetching instructions from the memory, reading data from the ports and the memory as
well as writing data to the ports and the memory. EU has no direction connection with System
Buses so this is possible with the BIU. EU and BIU are connected with the Internal Bus.
It has the following functional parts −
• Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of next
instructions and stores them in the instruction queue. When EU executes instructions and
is ready for its next instruction, then it simply reads the instruction from this instruction
queue resulting in increased execution speed.
• Fetching the next instruction while the current instruction executes is called pipelining.
• Segment register − BIU has 4 segment buses, i.e. CS, DS, SS & ES. It holds the addresses
of instructions and data in memory, which are used by the processor to access memory
locations. It also contains 1 pointer register IP, which holds the address of the next
instruction to executed by the EU.

o CS − It stands for Code Segment. It is used for addressing a memory location in the
code segment of the memory, where the executable program is stored.

o DS − It stands for Data Segment. It consists of data used by the program andis
accessed in the data segment by an offset address or the content of other register that
holds the offset address.

o SS − It stands for Stack Segment. It handles memory to store data and addresses
during execution.

o ES − It stands for Extra Segment. ES is additional data segment, which is used by

the string to hold the extra destination data.

• Instruction pointer − It is a 16-bit register used to hold the address of the next instruction
to be executed.

8086 PIN CONFIGURATION

8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package)
chip. Let us now discuss in detail the pin configuration of a 8086 Microprocessor.

8086 PIN DIAGRAM

Here is the pin diagram of 8086 microprocessor –

Power supply and frequency signals
It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.
Clock signal is provided through Pin-19. It provides timing to the processor for operations. Its
frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.

Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and AD8AD15
carries higher order byte data. During the first clock cycle, it carries 16-bit address and after that
it carries 16-bit data.

Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries
4-bit address and later it carries status signals.

S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer
of data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is active.
Read
It is available at pin 32 and is used to read signal for Read operation.
Ready
It is available at pin 22. It is an acknowledgement signal from I/O devices that data is transferred.
It is an active high signal. When it is high, it indicates that the device is ready to transfer data.
When it is low, it indicates wait state.

RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to immediately
terminate its present activity. This signal is active high for the first 4 clock cycles to RESET the
microprocessor.

INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the last clock
cycle of each instruction to determine if the processor considered this as an interrupt or not.

NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input, which
causes an interrupt request to the microprocessor.

TEST
This signal is like wait state and is available at pin 23. When this signal is high, then the processor
has to wait for IDLE state, else the execution continues.
MN/MX
It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the processor
is to operate in; when it is high, it works in the minimum mode and vice-aversa.
INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor
receives this signal, it acknowledges the interrupt.

ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated each time
the processor begins any operation. This signal indicates the availability of a valid address on the
address/data lines.
DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The
transreceiver is a device used to separate data from the address/data bus.

DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction
of data flow through the transreceiver. When it is high, data is transmitted out and vice-a-versa.

M/IO
This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicates the memory operation. It is available at pin 28.
WR
It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.
HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.
HOLD
This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.
QS1 and QS0
These are queue status signals and are available at pin 24 and 25. These signals provide the
status of instruction queue. Their conditions are shown in the following table −

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

S0, S1, S2
 These are the status signals that provide the status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O control signals. These are available at pin 26, 27, and
28. Following is the table showing their status −

S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to leave the
system bus. It is activated using the LOCK prefix on any instruction and is available at pin 29.

RQ/GT1 and RQ/GT0

These are the Request/Grant signals used by the other processors requesting the CPU to release
the system bus. When the signal is received by CPU, then it sends acknowledgment. RQ/GT0 has
a higher priority than RQ/GT1.

The 8086 microprocessor supports

• Data Transfer Instructions

• Arithmetic Instructions
• Bit Manipulation Instructions
• Program Execution Transfer Instructions (Branch & Loop Instructions)
• Interrupt Instructions
Let us now discuss these instruction sets in detail.
Data Transfer Instructions
These instructions are used to transfer the data from the source operand to the destination operand.
Following are the list of instructions under this group −
Instruction to transfer a word

• MOV − Used to copy the byte or word from the provided source to the provided destination.
• PPUSH − Used to put a word at the top of the stack.
• POP − Used to get a word from the top of the stack to the provided location.
• PUSHA − Used to put all the registers into the stack.
• POPA − Used to get words from the stack to all registers.
• XCHG − Used to exchange the data from two locations.
• XLAT − Used to translate a byte in AL using a table in the memory.

Instructions for input and output port transfer

• IN − Used to read a byte or word from the provided port to the accumulator.
• OUT − Used to send out a byte or word from the accumulator to the provided port.

Instructions to transfer the address

• LEA − Used to load the address of operand into the provided register.
• LDS − Used to load DS register and other provided register from the memory
• LES − Used to load ES register and other provided register from the memory.

Arithmetic Instructions
These instructions are used to perform arithmetic operations like addition, subtraction,
multiplication, division, etc.
Following is the list of instructions under this group −
Instructions to perform addition

• ADD − Used to add the provided byte to byte/word to word.

• ADC − Used to add with carry.
• INC − Used to increment the provided byte/word by 1.
 • AAA − Used to adjust ASCII after addition.
• DAA − Used to adjust the decimal after the addition/subtraction operation.

Instructions to perform subtraction

• SUB − Used to subtract the byte from byte/word from word.

• SBB − Used to perform subtraction with borrow.
• DEC − Used to decrement the provided byte/word by 1.
• NPG − Used to negate each bit of the provided byte/word and add 1/2’s complement.
• CMP − Used to compare 2 provided byte/word.
• AAS − Used to adjust ASCII codes after subtraction.
• DAS − Used to adjust decimal after subtraction.

Instruction to perform multiplication

• MUL − Used to multiply unsigned byte by byte/word by word.

• IMUL − Used to multiply signed byte by byte/word by word.
• AAM − Used to adjust ASCII codes after multiplication.

Instructions to perform division

• DIV − Used to divide the unsigned word by byte or unsigned double word by word.
• IDIV − Used to divide the signed word by byte or signed double word by word.
• AAD − Used to adjust ASCII codes after division.
• CBW − Used to fill the upper byte of the word with the copies of sign bit of the lower byte.
• CWD − Used to fill the upper word of the double word with the sign bit of the lower word.

Bit Manipulation Instructions

These instructions are used to perform operations where data bits are involved, i.e. operations like
logical, shift, etc.
Following is the list of instructions under this group −
Instructions to perform logical operation

• NOT − Used to invert each bit of a byte or word.

• AND − Used for adding each bit in a byte/word with the corresponding bit in another
byte/word.
• OR − Used to multiply each bit in a byte/word with the corresponding bit in another
byte/word.
• XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with the
corresponding bit in another byte/word.

Instructions to perform shift operations

• SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.
• SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.
• SAR − Used to shift bits of a byte/word towards the right and copy the old MSB into the
new MSB.

Instructions to perform rotate operations

• ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to Carry Flag
[CF].
• ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to Carry
Flag [CF].
• RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to MSB.
• RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to LSB.

Program Execution Transfer Instructions (Branch and Loop Instructions)

These instructions are used to transfer/branch the instructions during an execution. It
includes the following instructions −
Instructions to transfer the instruction during an execution without any condition −
• CALL − Used to call a procedure and save their return address to the stack.
• RET − Used to return from the procedure to the main program.
• JMP − Used to jump to the provided address to proceed to the next instruction.
Instructions to transfer the instruction during an execution with some conditions −
• JA/JNBE − Used to jump if above/not below/equal instruction satisfies.
• JAE/JNB − Used to jump if above/not below instruction satisfies.
• JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.
• JC − Used to jump if carry flag CF = 1
• JE/JZ − Used to jump if equal/zero flag ZF = 1
• JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.
• JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.
• JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.
• JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.
• JNC − Used to jump if no carry flag (CF = 0)
• JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
• JNO − Used to jump if no overflow flag OF = 0
• JNP/JPO − Used to jump if not parity/parity odd PF = 0
• JNS − Used to jump if not sign SF = 0
• JO − Used to jump if overflow flag OF = 1
• JP/JPE − Used to jump if parity/parity even PF = 1
• JS − Used to jump if sign flag SF = 1

Interrupt Instructions
These instructions are used to call the interrupt during program execution.
• INT − Used to interrupt the program during execution and calling service specified.
• IRET − Used to return from interrupt service to the main program

Microprocessor - 8086 Interrupts

Interrupt is the method of creating a temporary halt during program execution and allows
peripheral devices to access the microprocessor. The microprocessor responds to that interrupt
with an ISR (Interrupt Service Routine), which is a short program to instruct the microprocessor
on how to handle the interrupt.
The following image shows the types of interrupts we have in a 8086 microprocessor −

Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin
to the microprocessor.

The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt
and INTR is a maskable interrupt having lower priority. One more interrupt pin associated is INTA
called interrupt acknowledge.

NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt
request pin (INTR)and it is of type 2 interrupt.

When this interrupt is activated, these actions take place −

• Completes the current instruction that is in progress.

• Pushes the Flag register values on to the stack.
• Pushes the CS (code segment) value and IP (instruction pointer) value of the return address
on to the stack.
• IP is loaded from the contents of the word location 00008H.
• CS is loaded from the contents of the next word location 0000AH.
• Interrupt flag and trap flag are reset to 0.
INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts
are enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag
instruction.

The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled,
then the microprocessor first completes the current execution and sends ‘0’ on INTA pin twice.
The first ‘0’ means INTA informs the external device to get ready and during the second ‘0’ the
microprocessor receives the 8 bit, say X, from the programmable interrupt controller.

These actions are taken by the microprocessor −

• First completes the current instruction.

• Activates INTA output and receives the interrupt type, say X.
• Flag register value, CS value of the return address and IP value of the return address are
pushed on to the stack.
• IP value is loaded from the contents of word location X × 4
• CS is loaded from the contents of the next word location.
• Interrupt flag and trap flag is reset to 0
Software Interrupts
Some instructions are inserted at the desired position into the program to create interrupts.
These interrupt instructions can be used to test the working of various interrupt handlers. It includes

INT- Interrupt instruction with type number

It is 2-byte instruction. First byte provides the op-code and the second byte provides the
interrupt type number. There are 256 interrupt types under this group.

Its execution includes the following steps −

• Flag register value is pushed on to the stack.

• CS value of the return address and IP value of the return address are pushed on to the stack.
• IP is loaded from the contents of the word location ‘type number’ × 4
• CS is loaded from the contents of the next word location.
 • Interrupt Flag and Trap Flag are reset to 0

The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly for
type2 is 00008H and ……so on. The first five pointers are dedicated interrupt pointers. i.e. −

• TYPE 0 interrupt represents division by zero situation.

• TYPE 1 interrupt represents single-step execution during the debugging of a program.
• TYPE 2 interrupt represents non-maskable NMI interrupt.
• TYPE 3 interrupt represents break-point interrupt.
• TYPE 4 interrupt represents overflow interrupt.

The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and
interrupts from 32 to Type 255 are available for hardware and software interrupts.

INT 3-Break Point Interrupt Instruction

It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the program
so that when the processor reaches there, then it stops the normal execution of program and follows
the break-point procedure.

Its execution includes the following steps −

• Flag register value is pushed on to the stack.

• CS value of the return address and IP value of the return address are pushed on to the stack.
• IP is loaded from the contents of the word location 3×4 = 0000CH
• CS is loaded from the contents of the next word location.
• Interrupt Flag and Trap Flag are reset to 0
INTO - Interrupt on overflow instruction
It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is
CEH. As the name suggests it is a conditional interrupt instruction, i.e. it is active only when the
overflow flag is set to 1 and branches to the interrupt handler whose interrupt type number is 4. If
the overflow flag is reset then, the execution continues to the next instruction.

Its execution includes the following steps −

• Flag register values are pushed on to the stack.

• CS value of the return address and IP value of the return address are pushed on to the stack.
 • IP is loaded from the contents of word location 4×4 = 00010H
• CS is loaded from the contents of the next word location.
• Interrupt flag and Trap flag are reset to 0

I/O Interfacing Overview

In this chapter, we will discuss Memory Interfacing and IO Interfacing with 8086.

Interface is the path for communication between two components. Interfacing is of two types,
memory interfacing and I/O interfacing.

Memory Interfacing

When we are executing any instruction, we need the microprocessor to access the memory
for reading instruction codes and the data stored in the memory. For this, both the memory and the
microprocessor requires some signals to read from and write to registers.

The interfacing process includes some key factors to match with the memory requirements and
microprocessor signals. The interfacing circuit therefore should be designed in such a way that it
matches the memory signal requirements with the signals of the microprocessor.

IO Interfacing

There are various communication devices like the keyboard, mouse, printer, etc. So, we
need to interface the keyboard and other devices with the microprocessor by using latches and
buffers. This type of interfacing is known as I/O interfacing.

Block Diagram of Memory and I/O Interfacing

8086 Interfacing Pins
Following is the list of 8086 pins used for interfacing with other devices −

• A15 - A8 (Higher Address Bus)

• AD7 - AD0(Lower Address/Data Bus)
• ALE
• RD
• WR
• READY

Ways of Communication − Microprocessor with the Outside World?

There are two ways of communication in which the microprocessor can connect with the
outside world.

• Serial Communication Interface

• Parallel Communication interface

Serial Communication Interface − In this type of communication, the interface gets a single
byte of data from the microprocessor and sends it bit by bit to the other system serially and vice-
a-versa.

Parallel Communication Interface − In this type of communication, the interface gets a byte of
data from the microprocessor and sends it bit by bit to the other systems in simultaneous (or)
parallel fashion and vice-a-versa.

8086 Addressing Modes

The different ways in which a source operand is denoted in an instruction is known
as addressing modes. There are 8 different addressing modes in 8086 programming −
Immediate addressing mode
The addressing mode in which the data operand is a part of the instruction itself is known
as immediate addressing mode.
Example

MOV CX, 4929 H, ADD AX, 2387 H, MOV AL, FFH

Register addressing mode

It means that the register is the source of an operand for an instruction.
 Example

MOV CX, AX ; copies the contents of the 16-bit AX register into the 16-bit CX
register), ADD BX, AX

Direct addressing mode

The addressing mode in which the effective address of the memory location is written
directly in the instruction.
Example

MOV AX, [1592H], MOV AL, [0300H]

Register indirect addressing mode

This addressing mode allows data to be addressed at any memory location through an offset
address held in any of the following registers: BP, BX, DI & SI.
Example

MOV AX, [BX] ; Suppose the register BX contains 4895H, then the contents
4895H are moved to AX
ADD CX, {BX}

Based addressing mode

In this addressing mode, the offset address of the operand is given by the sum of contents
of the BX/BP registers and 8-bit/16-bit displacement.
Example

MOV DX, [BX+04], ADD CL, [BX+08]

Indexed addressing mode

In this addressing mode, the operands offset address is found by adding the contents of SI
or DI register and 8-bit/16-bit displacements.
Example

MOV BX, [SI+16], ADD AL, [DI+16]

Based-index addressing mode

In this addressing mode, the offset address of the operand is computed by summing the
base register to the contents of an Index register.
Example

ADD CX, [AX+SI], MOV AX, [AX+DI]

Based indexed with displacement mode
In this addressing mode, the operands offset is computed by adding the base register
contents. An Index registers contents and 8 or 16-bit displacement.
Example

MOV AX, [BX+DI+08], ADD CX, [BX+SI+16]

8279 - Programmable Keyboard

8279 programmable keyboard/display controller is designed by Intel that interfaces a
keyboard with the CPU. The keyboard first scans the keyboard and identifies if any key has been
pressed. It then sends their relative response of the pressed key to the CPU and vice-a-versa.

How Many Ways the Keyboard is Interfaced with the CPU?

The Keyboard can be interfaced either in the interrupt or the polled mode. In the Interrupt
mode, the processor is requested service only if any key is pressed, otherwise the CPU will
continue with its main task.

In the Polled mode, the CPU periodically reads an internal flag of 8279 to check whether
any key is pressed or not with key pressure.

How Does 8279 Keyboard Work?

The keyboard consists of maximum 64 keys, which are interfaced with the CPU by using
the key-codes. These key-codes are de-bounced and stored in an 8-byte FIFORAM, which can be
accessed by the CPU. If more than 8 characters are entered in the FIFO, then it means more than
eight keys are pressed at a time. This is when the overrun status is set.

If a FIFO contains a valid key entry, then the CPU is interrupted in an interrupt mode else
the CPU checks the status in polling to read the entry. Once the CPU reads a key entry, then FIFO
is updated, and the key entry is pushed out of the FIFO to generate space for new entries.
Architecture and Description

I/O Control and Data Buffer

This unit controls the flow of data through the microprocessor. It is enabled only when D
is low. Its data buffer interfaces the external bus of the system with the internal bus of the
microprocessor. The pins A0, RD, and WR are used for command, status or data read/write
operations.

Control and Timing Register and Timing Control

This unit contains registers to store the keyboard, display modes, and other operations as
programmed by the CPU. The timing and control unit handles the timings for the operation of the
circuit.

Scan Counter

It has two modes i.e. Encoded mode and Decoded mode. In the encoded mode, the counter
provides the binary count that is to be externally decoded to provide the scan lines for the keyboard
and display.
In the decoded scan mode, the counter internally decodes the least significant 2 bits and provides
a decoded 1 out of 4 scan on SL0-SL3.

Return Buffers, Keyboard Debounce, and Control

This unit first scans the key closure row-wise, if found then the keyboard debounce unit
debounces the key entry. In case, the same key is detected, then the code of that key is directly
transferred to the sensor RAM along with SHIFT & CONTROL key status.

FIFO/Sensor RAM and Status Logic

This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code of every pressed
key is entered into the RAM as per their sequence. The status logic generates an interrupt request
after each FIFO read operation till the FIFO gets empty.

In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is
loaded with the status of their corresponding row of sensors into the matrix. When the sensor
changes its state, the IRQ line changes to high and interrupts the CPU.

Display Address Registers and Display RAM

This unit consists of display address registers which holds the addresses of the word
currently read/written by the CPU to/from the display RAM.

8279 − Pin Description

The following figure shows the pin diagram of 8279 −
Data Bus Lines, DB0 - DB7
These are 8 bidirectional data bus lines used to transfer the data to/from the CPU.
CLK
The clock input is used to generate internal timings required by the microprocessor.
RESET
As the name suggests this pin is used to reset the microprocessor.
CS Chip Select
When this pin is set to low, it allows read/write operations, else this pin should be set to
high.
A0
This pin indicates the transfer of command/status information. When it is low, it indicates
the transfer of data.
RD, WR
This Read/Write pin enables the data buffer to send/receive data over the data bus.
IRQ
This interrupt output line goes high when there is data in the FIFO sensor RAM. The
interrupt line goes low with each FIFO RAM read operation. However, if the FIFO RAM further
contains any key-code entry to be read by the CPU, this pin again goes high to generate an interrupt
to the CPU.

Vss, Vcc

These are the ground and power supply lines of the microprocessor.

SL0 − SL3

These are the scan lines used to scan the keyboard matrix and display the digits. These lines
can be programmed as encoded or decoded, using the mode control register.

RL0 − RL7

These are the Return Lines which are connected to one terminal of keys, while the other
terminal of the keys is connected to the decoded scan lines. These lines are set to 0 when any key
is pressed.
SHIFT

The Shift input line status is stored along with every key code in FIFO in the scanned
keyboard mode. Till it is pulled low with a key closure, it is pulled up internally to keep it high

CNTL/STB - CONTROL/STROBED I/P Mode

In the keyboard mode, this line is used as a control input and stored in FIFO on a key
closure. The line is a strobe line that enters the data into FIFO RAM, in the strobed input mode. It
has an internal pull up. The line is pulled down with a key closure.

BD

It stands for blank display. It is used to blank the display during digit switching.

OUTA0 – OUTA3 and OUTB0 – OUTB3

These are the output ports for two 16x4 or one 16x8 internal display refresh registers. The
data from these lines is synchronized with the scan lines to scan the display and the keyboard.

Operational Modes of 8279

There are two modes of operation on 8279 − Input Mode and Output Mode.

Input Mode

This mode deals with the input given by the keyboard and this mode is further classified into 3
modes.

• Scanned Keyboard Mode − In this mode, the key matrix can be interfaced using either
encoded or decoded scans. In the encoded scan, an 8×8 keyboard or in the decoded scan, a
4×8 keyboard can be interfaced. The code of key pressed with SHIFT and CONTROL
status is stored into the FIFO RAM.

• Scanned Sensor Matrix − In this mode, a sensor array can be interfaced with the processor
using either encoder or decoder scans. In the encoder scan, 8×8 sensor matrix or with
decoder scan 4×8 sensor matrix can be interfaced.
 • Strobed Input − In this mode, when the control line is set to 0, the data on the return lines
is stored in the FIFO byte by byte.

Output Mode

This mode deals with display-related operations. This mode is further classified into two output
modes.

• Display Scan − This mode allows 8/16 character multiplexed displays to be organized as
dual 4-bit/single 8-bit display units.
• Display Entry − This mode allows the data to be entered for display either from the right
side/left side.

8257 DMA Controller

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest
rate. It allows the device to transfer the data directly to/from memory without any interference of
the CPU.

Using a DMA controller, the device requests the CPU to hold its data, address and control
bus, so the device is free to transfer data directly to/from the memory. The DMA data transfer is
initiated only after receiving HLDA signal from the CPU.

How DMA Operations are Performed?

Following is the sequence of operations performed by a DMA −

• Initially, when any device has to send data between the device and the memory, the device
has to send DMA request (DRQ) to DMA controller.
• The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert
the HLDA.
• Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU
leaves the control over bus and acknowledges the HOLD request through HLDA signal.
• Now the CPU is in HOLD state and the DMA controller has to manage the operations over
buses between the CPU, memory, and I/O devices.
Features of 8257
Here is a list of some of the prominent features of 8257 −
• It has four channels which can be used over four I/O devices.
• Each channel has 16-bit address and 14-bit counter.
• Each channel can transfer data up to 64kb.
• Each channel can be programmed independently.
• Each channel can perform read transfer, write transfer and verify transfer operations.
• It generates MARK signal to the peripheral device that 128 bytes have been transferred.
• It requires a single phase clock.
• Its frequency ranges from 250Hz to 3MHz.
• It operates in 2 modes, i.e., Master mode and Slave mode.

8257 Architecture
The following image shows the architecture of 8257 −
8257 Pin Description
The following image shows the pin diagram of a 8257 DMA controller −

DRQ0−DRQ3
These are the four individual channel DMA request inputs, which are used by the peripheral
devices for using DMA services. When the fixed priority mode is selected, then DRQ0 has the
highest priority and DRQ3 has the lowest priority among them.

DACKo − DACK3

These are the active-low DMA acknowledge lines, which updates the requesting peripheral
about the status of their request by the CPU. These lines can also act as strobe lines for the
requesting devices.

Do − D7

These are bidirectional, data lines which are used to interface the system bus with the
internal data bus of DMA controller. In the Slave mode, it carries command words to 8257 and
status word from 8257. In the master mode, these lines are used to send higher byte of the generated
address to the latch. This address is further latched using ADSTB signal.

IOR

It is an active-low bidirectional tri-state input line, which is used by the CPU to read
internal registers of 8257 in the Slave mode. In the master mode, it is used to read data from the
peripheral devices during a memory write cycle.
IOW

It is an active low bi-direction tri-state line, which is used to load the contents of the data
bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or terminal
count register. In the master mode, it is used to load the data to the peripheral devices during DMA
memory read cycle.

CLK

It is a clock frequency signal which is required for the internal operation of 8257.

RESET

This signal is used to RESET the DMA controller by disabling all the DMA channels.

Ao - A3

These are the four least significant address lines. In the slave mode, they act as an input,
which selects one of the registers to be read or written. In the master mode, they are the four least
significant memory address output lines generated by 8257.

CS

It is an active-low chip select line. In the Slave mode, it enables the read/write operations
to/from 8257. In the master mode, it disables the read/write operations to/from 8257.

A4 - A7

These are the higher nibble of the lower byte address generated by DMA in the master
mode.

READY

It is an active-high asynchronous input signal, which makes DMA ready by inserting wait
states.

HRQ
This signal is used to receive the hold request signal from the output device. In the slave
mode, it is connected with a DRQ input line 8257. In Master mode, it is connected with HOLD
input of the CPU.
HLDA
It is the hold acknowledgement signal which indicates the DMA controller that the bus has
been granted to the requesting peripheral by the CPU when it is set to 1.
MEMR
It is the low memory read signal, which is used to read the data from the addressed memory
locations during DMA read cycles.
MEMW
It is the active-low three state signal which is used to write the data to the addressed
memory location during DMA write operation.
ADST
This signal is used to convert the higher byte of the memory address generated by the DMA
controller into the latches.
AEN
This signal is used to disable the address bus/data bus.
TC
It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present
peripheral devices.
MARK
The mark will be activated after each 128 cycles or integral multiples of it from the
beginning. It indicates the current DMA cycle is the 128th cycle since the previous MARK output
to the selected peripheral device.
Vcc
It is the power signal which is required for the operation of the circuit.

8255 - Programmable Peripheral Interface

The 8255A is a general purpose programmable I/O device designed to transfer the data
from I/O to interrupt I/O under certain conditions as required. It can be used with almost any
microprocessor.

It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as
per the requirement.

Ports of 8255

8255 has three ports, i.e., PORT A, PORT B, and PORT C.

 • Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
• Port B is similar to PORT A.
• Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-
PC4) by the control word.

These three ports are further divided into two groups, i.e. Group A includes PORT A and upper
PORT C. Group B includes PORT B and lower PORT C. These two groups can be programmed
in

three different modes, i.e. the first mode is named as mode 0, the second mode is named as
Mode 1 and the third mode is named as Mode 2.

Operating Modes

8255 has three different operating modes −

• Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit
ports. Each port can be programmed in either input mode or output mode where outputs are
latched and inputs are not latched. Ports do not have interrupt capability.
• Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be configured as
either input or output ports. Each port uses three lines from port C as handshake signals.
Inputs and outputs are latched.
• Mode 2 − In this mode, Port A can be configured as the bidirectional port and Port B either
in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals for data
transfer. The remaining three signals from Port C can be used either as simple I/O or as
handshake for port B.
Features of 8255

The prominent features of 8255A are as follows −

• It consists of 3 8-bit IO ports i.e. PA, PB, and PC.

• Address/data bus must be externally demux'd.
• It is TTL compatible.
• It has improved DC driving capability.
8255 Architecture
The following figure shows the architecture of 8255A −

8255 - Pin Description

Let us first take a look at the pin diagram of Intel 8255A −
 Now let us discuss the functional description of the pins in 8255A.

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data
bus. Data is transmitted or received by the buffer as per the instructions by the CPU. Control words
and status information is also transferred using this bus.

Read/Write Control Logic

This block is responsible for controlling the internal/external transfer of data/control/status

word. It accepts the input from the CPU address and control buses, and in turn issues command to
both the control groups.

CS

It stands for Chip Select. A LOW on this input selects the chip and enables the
communication between the 8255A and the CPU. It is connected to the decoded address, and A0 &
A1 are connected to the microprocessor address lines.

Their result depends on the following conditions −

CS A1 A0 Result

0 0 0 PORT A

0 0 1 PORT B

0 1 0 PORT C

0 1 1 Control Register

1 X X No Selection

WR
It stands for write. This control signal enables the write operation. When this signal goes
low, the microprocessor writes into a selected I/O port or control register.
RESET
This is an active high signal. It clears the control register and sets all ports in the input mode.
RD
It stands for Read. This control signal enables the Read operation. When the signal is low, the
microprocessor reads the data from the selected I/O port of the 8255.
A0 and A1
These input signals work with RD, WR, and one of the control signal. Following is the table
showing their various signals with their result.

A1 A0 RD WR CS Result

Input Operation
0 0 0 1 0
PORT A → Data Bus

0 1 0 1 0 PORT B → Data Bus

1 0 0 1 0 PORT C → Data Bus

Output Operation
0 0 1 0 0
Data Bus → PORT A

0 1 1 0 0 Data Bus → PORT A

1 0 1 0 0 Data Bus → PORT B

1 1 1 0 0 Data Bus → PORT D

8253/8254 - Programmable Interval Timer

The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for
microprocessors to perform timing and counting functions using three 16-bit registers. Each
counter has 2 input pins, i.e. Clock & Gate, and 1 pin for “OUT” output. To operate a counter, a
16-bit count is loaded in its register. On command, it begins to decrement the count until it reaches
0, then it generates a pulse that can be used to interrupt the CPU.
Difference between 8253 and 8254

The following table differentiates the features of 8253 and 8254 −

8253 8254

Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 -

10 MHz

It uses N-MOS technology It uses H-MOS technology

Read-Back command is not available Read-Back command is

available

Reads and writes of the same counter Reads and writes of the same
cannot be interleaved. counter can be interleaved.

Features of 8253 / 54
The most prominent features of 8253/54 are as follows −

• It has three independent 16-bit down counters.

• It can handle inputs from DC to 10 MHz.
• These three counters can be programmed for either binary or BCD count.
• It is compatible with almost all microprocessors.
• 8254 has a powerful command called READ BACK command, which allows the user to
check the count value, the programmed mode, the current mode, and the current status of
the counter.
8254 Architecture
The architecture of 8254 looks as follows −

8254 Pin Description

Here is the pin diagram of 8254 −

In the above figure, there are three counters, a data bus buffer, Read/Write control logic,
and a control register. Each counter has two input signals - CLOCK & GATE, and one output
signal - OUT.
Data Bus Buffer

It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the system
data bus. It has three basic functions −

• Programming the modes of 8253/54.

• Loading the count registers.
• Reading the count values.

Read/Write Logic

It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1. In the peripheral I/O
mode, the RD and WR signals are connected to IOR and IOW, respectively. In the memorymapped
I/O mode, these are connected to MEMR and MEMW.

Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and CS
is tied to a decoded address. The control word register and counters are selected according to the
signals on lines A0 & A1.

A1 A0 Result

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control Word Register

X X No Selection

Control Word Register

This register is accessed when lines A0 & A1 are at logic 1. It is used to write a command
word, which specifies the counter to be used, its mode, and either a read or write operation.
Following table shows the result for various control inputs.
 A1 A0 RD WR CS Result

0 0 1 0 0 Write Counter 0

0 1 1 0 0 Write Counter 1

1 0 1 0 0 Write Counter 2

1 1 1 0 0 Write Control Word

0 0 0 1 0 Read Counter 0

0 1 0 1 0 Read Counter 1

1 0 0 1 0 Read Counter 2

1 1 0 1 0 No operation

X X 1 1 0 No operation

X X X X 1 No operation

Counters
Each counter consists of a single, 16 bit-down counter, which can be operated in either
binary or BCD. Its input and output is configured by the selection of modes stored in the control
word register. The programmer can read the contents of any of the three counters without
disturbing the actual count in process.

8253/54 - Operational Modes

8253/54 can be operated in 6 different modes. In this chapter, we will discuss these
operational modes.

Mode 0 ─ Interrupt on Terminal Count

• It is used to generate an interrupt to the microprocessor after a certain interval.

• Initially the output is low after the mode is set. The output remains LOW after the count
value is loaded into the counter.
 • The process of decrementing the counter continues till the terminal count is reached, i.e.,
the count become zero and the output goes HIGH and will remain high until it reloads a
new count.
• The GATE signal is high for normal counting. When GATE goes low, counting is
terminated and the current count is latched till the GATE goes high again.
Mode 1 – Programmable One Shot

• It can be used as a mono stable multi-vibrator.

• The gate input is used as a trigger input in this mode.
• The output remains high until the count is loaded and a trigger is applied.
Mode 2 – Rate Generator

• The output is normally high after initialization.

• Whenever the count becomes zero, another low pulse is generated at the output and the
counter will be reloaded.
Mode 3 – Square Wave Generator

• This mode is similar to Mode 2 except the output remains low for half of the timer period
and high for the other half of the period.

Mode 4 − Software Triggered Mode

• In this mode, the output will remain high until the timer has counted to zero, at which point
the output will pulse low and then go high again.
• The count is latched when the GATE signal goes LOW.
• On the terminal count, the output goes low for one clock cycle then goes HIGH. This low
pulse can be used as a strobe.
Mode 5 – Hardware Triggered Mode

• This mode generates a strobe in response to an externally generated signal.

• This mode is similar to mode 4 except that the counting is initiated by a signal at the gate
input, which means it is hardware triggered instead of software triggered.
• After it is initialized, the output goes high.
• When the terminal count is reached, the output goes low for one clock cycle.