Memory Interface
Bus Timing
It is essential to understand system bus timing before choosing a memory or I/O device for interfacing to
the 8086 or 8088 microprocessors. The three buses of the 8086 and 8088: address, data, and control
function exactly the same way as those of any other microprocessor. If data are written to the memory,
the microprocessor outputs the memory address on the address bus, outputs the data to be written into
memory on the data bus, and issues a write (𝑊𝑅̅̅̅̅̅) to memory and 𝐼𝑂/𝑀 ̅̅̅ =
̅ = 0 for the 8088 and 𝑀/𝐼𝑂
1 for the 8086. If data are read from the memory, the microprocessor outputs the memory address on
the address bus, issues a read memory signal (𝑅𝐷̅̅̅̅ ), and accepts the data via the data bus.
Timing Diagrams
The 8086/8088 microprocessors use the memory and I/O in periods called bus cycles. Each bus cycle
equals four system-clocking periods (T states). Newer microprocessors divide the bus cycle into as few
as two clocking periods. If the clock is operated at 5 MHz (the basic operating frequency for these two
microprocessors), one 8086/8088 bus cycle is complete in 800 ns. This means that the microprocessor
reads or writes data between itself and memory or I/O at a maximum rate of 1.25 million times a sec-
ond. (Because of the internal queue, the 8086/8088 can execute 2.5 million instructions per second
[MIPS] in bursts.) Other available versions of these microprocessors operate at much higher transfer
rates due to higher clock frequencies. Figure 1a shows a read cycle while 1b shows a write cycle.
During the first clocking period in a bus cycle, which is called T1, many things happen. The address of the
memory or I/O location is sent out via the address bus and the address/data bus connections. (The ad-
dress/data bus is multiplexed and sometimes contains memory-addressing information, sometimes
data.) During TI, control signals ALE,𝐷𝑇/𝑅̅ , and 𝐼𝑂/𝑀 ̅ (8088) or ̅̅̅
𝐼𝑂/𝑀 (8086) are also output. The 𝐼𝑂/𝑀̅
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̅̅̅/𝑀 signal indicates whether the address bus contains a memory address or an I/O device (port)
or 𝐼𝑂
number.
During T2, the 8086/8088 microprocessors tri-states the multiplexed address/data bus in preparation
for the data read which take place in T3. Address lines 𝐴16 through 𝐴19 switch over to status outputs 𝑆3
through 𝑆6 and a zero is output on ̅̅̅̅
𝑅𝐷 to specify a memory- read cycle to the external hardware.
̅̅̅̅̅̅ signal turns
These events cause the memory or I/O device to begin to perform a read action. The, 𝐷𝐸𝑁
on the data bus buffers, so the microprocessor can accept the data read from the memory.
READY is sampled at the end of T2. If READY is low at this time, T3 becomes a wait state (Tw). This clock-
ing period is provided to allow the memory time to access data. The data bus is sampled at the end of
T3.
In T4, all bus signals are deactivated in preparation for the next bus cycle.
̅̅̅̅̅ instead of 𝑅𝐷
The most noticeable difference (aside from the use of 𝑊𝑅 ̅̅̅̅ ) is the activity on the data bus.
Unlike the read cycle, the data bus switches from address-out information to data-out information and
keeps a valid copy of the output data on the bus for the remainder of the cycle. This should eliminate
any setup times required by the memory chips.
Ready and the Wait State
The READY input causes wait states for slower memory and I/O components. A wait state (Tw) is an ex-
tra clocking period, inserted between T2 and T3 to lengthen the bus cycle. If one “wait state” is inserted,
then the memory access time, normally 460 ns with a 5 MHz clock, is lengthened by one clocking period
(200 ns) to 660 ns.
To introduce a wait state, a delay circuit is introduced as seen in figure 2. The output of the select de-
coder is connected to the to the chip select (CS) pin of the memory and to the input of a delay circuit.
The delay circuit extends the bus cycle for a time equal to the access time of the memory. The processor
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samples READY during T2 of each bus cycle and will not proceed into T3 until READY is at a high level.
Figure 2b shows the timing diagram. From the timing diagram, it can be seen that wait time (𝑇𝑤 ) is
equal to the access time (𝑇𝑎𝑐𝑐 )
Figure 2: Block diagram of the synchronization of memory speed to the microprocessor speed. (a) block
diagram of delay circuit, (b) associated timing diagram.
The READY Input
The READY input is sampled at the end of T2 and again, if applicable, in the middle of Tw. If READY is a
logic 0 at the end of T2, T3 is delayed and Tw is inserted between T2 and T3. READY is next sampled at
the middle of Tw to determine whether the next state is Tw or T3. It is tested for a logic 0 on the 1-to-0
transition of the clock at the end of T2, and for a 1 on the 0-to-1 transition of the clock in the middle of
Tw.
The timing diagram in Figure 3 shows READY causing one wait state (Tw), along with the required setup
and hold times from the system clock. The timing requirement for this operation is met by the internal
READY synchronization circuitry of the 8284A clock generator. When the 8284A is used for READY, the
RDY (ready input to the 8284A) input occurs at the end of each T state.
Figure 3: 8086/8088 READY input timing.
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RDY and the 8284A
RDY is the synchronized ready input to the 8284A clock generator (see figure 4). The timing diagram for
this input is provided in Figure 5. Although it differs from the timing for the READY input to the
8086/8088, the internal 8284A circuitry guarantees the accuracy of the READY synchronization provided
to the 8086/8088 microprocessors.
Figure 4: Connection of clock generator connection to 8088.
Figure 5: 8284A RDY input timing
Figure 6 illustrates a circuit used to introduce almost any number of wait states for the 8086/8088 mi-
croprocessors. Here, an 8-bit serial shift register (74LS164) shifts a logic 0 for one or more clock periods
from one of its Q outputs through to the RDY1 input of the 8284A. With appropriate strapping, this cir-
cuit can provide various numbers of wait states. Notice also how the shift register is cleared back to its
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starting point. The output of the register is forced high when the 𝑅𝐷 ̅̅̅̅ ,𝑊𝑅 ̅̅̅̅̅̅̅ and pins are all logic
̅̅̅̅̅ ,𝐼𝑁𝑇𝐴
1s. These three signals are high until state T2, so the shift register shifts for the first time when the posi-
tive edge of the T2 arrives. If one “wait” is desired, output QB is connected to the OR gate. If two waits
are desired, output QC is connected, and so forth.
Figure 6: A circuit that will cause between 0 and 7 wait states.
Address Decoding
In order to attach a memory device to the microprocessor, it is necessary to decode the address sent
from the microprocessor. Decoding makes the memory function at a unique section or partition of the
memory map. Without an address decoder, only one memory device can be connected to a micropro-
cessor, which would make it virtually useless.
Simple NAND Gate Decoder
When the 2𝐾 × 8 EPROM is used, address connections 𝐴10 − 𝐴0 of the 8088 are connected to address
inputs 𝐴10 − 𝐴0 of the EPROM. The remaining nine address pins 𝐴19 − 𝐴11 are connected to the inputs
of a NAND gate decoder (see 7). The decoder selects the EPROM from one of the 2K-byte sections of the
1M-byte memory system in the 8088 microprocessor.
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In this circuit, a single NAND gate decodes the memory address. The output of the NAND gate is a logic 0
whenever the 8088 address pins attached to its inputs (𝐴19 − 𝐴11 ) are all logic 1s. The active low, logic 0
output of the NAND gate decoder is connected to the 𝐶𝐸 ̅̅̅̅ input pin that selects (enables) the EPROM.
Whenever 𝐶𝐸 ̅̅̅̅ is a logic 0, data will be read from the EPROM only if ̅̅̅̅
𝑂𝐸 is also a logic 0. The ̅̅̅̅
𝑂𝐸 pin is
̅̅̅̅ ̅̅̅̅̅̅̅̅̅
activated by the 8088 𝑅𝐷signal or the 𝑀𝑅𝐷𝐶 (memory read control) signal of other family members.
If the 20-bit binary address, decoded by the NAND gate, is written so that the leftmost nine bits are 1s
and the rightmost 11 bits are don’t cares (X), the actual address range of the EPROM can be determined.
(A don’t care is a logic 1 or a logic 0, whichever is appropriate). Example 1 illustrates how the address
range for this EPROM is determined by writing down the externally decoded address bits (𝐴19 − 𝐴11 )
and the address bits decoded by the EPROM (𝐴10 − 𝐴0 ) as don’t cares. We really do not care about the
address pins on the EPROM because they are internally decoded. As the example illustrates, the don’t
cares are first written as 0s to locate the lowest address and then as 1s to find the highest address.
Although this example serves to illustrate decoding, NAND gates are rarely used to decode memory be-
cause each memory device requires its own NAND gate decoder. Because of the excessive cost of the
NAND gate decoder and inverters that are often required, this option requires that an alternate be
found.
Figure 7: A simple NAND gate decoder that selects a 2716 EPROM for memory location FF800H–FFFFFH.
Figure 8a shows a block diagram of a memory address decoder connected to a memory chip. Figure 8b
shows a simplified timing diagram representing the activity on the address bus and the 𝐼𝑂/𝑀 ̅ output.
The memory address decoder waits for a particular pattern on the address lines and a low on 𝐼𝑂/𝑀 ̅ be-
̅̅̅̅̅ low. When these conditions are satisfied, the low on 𝑆𝐸𝐿
fore making 𝑆𝐸𝐿 ̅̅̅̅̅ causes the 𝐶𝑆
̅̅̅̅ (chip select)
input on the memory chip to go low, which enables the internal circuitry, thus connecting the RAM or
EPROM to the processor’s data bus. When the address bus contains an address different from the one
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the address decoder expects to see, or if 𝐼𝑂/𝑀̅ is high, the output of the decoder will remain high, disa-
bling the memory chip and causing its internal buffers to tri-state themselves. Thus, the RAM or EPROM
is effectively dis connected from the data bus.
Figure 8: Simple memory decoder. 8a block diagram, 8b timing diagram.
The challenge presented to the memory address decoder circuit designer is to chip- enable the memory
device at the correct time. The following examples illustrate the steps involved in the design.
The 3-to-8 Line Decoder (74LS138)
One of the more common, although not only, integrated circuit decoders found in many microproces-
sor-based systems is the 74LS138 3-to-8-line decoder. Figure 9 illustrates this decoder and its truth ta-
ble. The truth table shows that only one of the eight outputs ever goes low at any time. For any of the
decoder’s outputs to go low, the three enable inputs ( 𝐺2𝐴̅̅̅̅̅̅, 𝐺2𝐵
̅̅̅̅̅̅, and 𝐺1) must all be active. To be ac-
̅̅̅̅̅̅ and 𝐺2𝐵
tive, the𝐺2𝐴 ̅̅̅̅̅̅ inputs must both be low (logic 0), and 𝐺1 must be high (logic 1). Once the
74LS138 is enabled, the address inputs (C, B, and A) select which output pin goes low. It is used to select
one of eight different memory devices at the same time (see figure 10).
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Figure 9: The 74LS138 3-to-8-line decoder and function table.
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Figure 10: Selection of address F0000H–FFFFFH in an 8088 using 74LS138 decoder.
Figure 10 is a circuit that uses eight 2764 EPROMs for a 64K × 8 section of memory in an 8088 micropro-
cessor-based system. The addresses selected in this circuit are F0000H–FFFFFH.
Example 1
a. A circuit containing 32KB of RAM is to be interfaced to an 8088 based system, so that the first
address of the RAM is at 48000H. Determine:
i. the entire range of the RAM address
ii. the address lines used to select the chip.
b. Draw the decoder for the chip select (CS) input.
Solution
32𝐾𝐵 = 25 × 210 = 215 , therefore 15 lines will be required to address the RAM. These lines are 𝐴0
through 𝐴14 .
Write the twenty address lines 𝐴0 through 𝐴19 . Below the lines write 01001 in that order for
𝐴19 , 𝐴18 , 𝐴17 𝐴16 . 𝐴15 , below the other lines write 𝑋 for a 1 𝑜𝑟 0. Repeat second row with all 𝑋𝑠 replace
by Zeros. This is the first memory location. Repeat second row with all 𝑋𝑠 replaced by Ones. This is the
last memory location.
i. The range is from the first location to the last.
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ii. Check the lines that are not changing in value, these are 𝐴19 , 𝐴18 , 𝐴17 𝐴16 . 𝐴15 . These are the
lines to select the chip.
The decoder for chip select is as shown below.
Exercise
With the aid of a hardware configuration diagram and timing waveforms, describe the process of multi-
plexing and demultiplexing of the lines of the bus between data and address, in an 8088 microproces-
sor- to- memory interface during a read cycle.
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