MODULE: 2

1. INTERFACING MEMORY AND I/O DEVICES WITH 8085

The programs and data that are executed by the microprocessor have to be stored in
ROM/EPROM and RAM, which are basically semiconductor memory chips. The programs
and data that are stored in ROM/EPROM are not erased even when power supply to the
chip is removed. Hence, they are called non-volatile memory. They can be used to store
permanent programs.

In a RAM, stored programs and data are erased when the power supply to the chip is
removed. Hence, RAM is called volatile memory. RAM can be used to store programs and
data that include, programs written during software development for a microprocessor based
system, program written when one is learning assembly language programming and data
enter while testing these programs.

Input and output devices, which are interfaced with 8085, are essential in any
microprocessor based system. They can be interfaced using two schemes: I/O mapped I/O
and memory-mapped I/O. In the I/O mapped I/O scheme, the I/O devices are treated
differently from memory. In the memory-mapped I/O scheme, each I/O device is assumed
to be a memory location.

2. INTERFACING MEMORY CHIPS WITH 8085

8085 has 16 address lines (A0 - A15), hence a maximum of 64 KB (= 216 bytes) of memory
locations can be interfaced with it. The memory address space of the 8085 takes values from
0000H to FFFFH.

The 8085 initiates set of signals such as IO/M , RD and WR when it wants to read from and
write into memory. Similarly, each memory chip has signals such as CE or CS (chip enable
or chip select), OE or RD (output enable or read) and WE or WR (write enable or write)
associated with it.

Generation of Control Signals for Memory:

When the 8085 wants to read from and write into memory, it activates IO/M , RD and WR
signals as shown in Table 8.

Table 8 Status of IO/M , RD and WR signals during memory read and write operations

IO/M RD WR Operation
0 0 1 8085 reads data from memory
0 1 0 8085 writes data into memory

Using IO/M , RD and WR signals, two control signals MEMR (memory read) and
MEMW (memory write) are generated. Fig. 16 shows the circuit used to generate these
signals.
 Fig. 16 Circuit used to generate MEMR and MEMW signals

When is IO/M high, both memory control signals are deactivated irrespective of the status
of RD and WR signals.

Ex: Interface an IC 2764 with 8085 using NAND gate address decoder such that the address
range allocated to the chip is 0000H – 1FFFH.

Specification of IC 2764:

 8 KB (8 x 210 byte) EPROM chip

 13 address lines (213 bytes = 8 KB)

Interfacing:

 13 address lines of IC are connected to the corresponding address lines of 8085.

 Remaining address lines of 8085 are connected to address decoder formed using
logic gates, the output of which is connected to the CE pin of IC.
 Address range allocated to the chip is shown in Table 9.
 Chip is enabled whenever the 8085 places an address allocated to EPROM chip in
the address bus. This is shown in Fig. 17.

Fig. 17 Interfacing IC 2764 with the 8085

Table 9 Address allocated to IC 2764

Ex: Interface a 6264 IC (8K x 8 RAM) with the 8085 using NAND gate decoder such that
the starting address assigned to the chip is 4000H.

Specification of IC 6264:

 8K x 8 RAM
 8 KB = 213 bytes
 13 address lines

The ending address of the chip is 5FFFH (since 4000H + 1FFFH = 5FFFH). When the
address 4000H to 5FFFH are written in binary form, the values in the lines A15, A14, A13
are 0, 1 and 0 respectively. The NAND gate is designed such that when the lines A15 and
A13 carry 0 and A14 carries 1, the output of the NAND gate is 0. The NAND gate output is
in turn connected to the CE1 pin of the RAM chip. A NAND output of 0 selects the RAM
chip for read or write operation, since CE2 is already 1 because of its connection to +5V.
Fig. 18 shows the interfacing of IC 6264 with the 8085.

Fig. 18 Interfacing 6264 IC with the 8085

Ex: Interface two 6116 ICs with the 8085 using 74LS138 decoder such that the starting
addresses assigned to them are 8000H and 9000H, respectively.
Specification of IC 6116:

 2 K x 8 RAM
 2 KB = 211 bytes
 11 address lines

6116 has 11 address lines and since 2 KB, therefore ending addresses of 6116 chip 1 is and
chip 2 are 87FFH and 97FFH, respectively. Table 10 shows the address range of the two
chips.

Table 10 Address range for IC 6116

Interfacing:

 Fig. 19 shows the interfacing.

 A0 – A10 lines of 8085 are connected to 11 address lines of the RAM chips.
 Three address lines of 8085 having specific value for a particular RAM are
connected to the three select inputs (C, B and A) of 74LS138 decoder.
 Table 10 shows that A13=A12=A11=0 for the address assigned to RAM 1 and
A13=0, A12=1 and A11=0 for the address assigned to RAM 2.
 Remaining lines of 8085 which are constant for the address range assigned to the
two RAM are connected to the enable inputs of decoder.
 When 8085 places any address between 8000H and 87FFH in the address bus, the
select inputs C, B and A of the decoder are all 0. The Y0 output of the decoder is
also 0, selecting RAM 1.
 When 8085 places any address between 9000H and 97FFH in the address bus, the
select inputs C, B and A of the decoder are 0, 1 and 0. The Y2 output of the decoder
is also 0, selecting RAM 2.
 Fig. 19 Interfacing two 6116 RAM chips using 74LS138 decoder

3. PERIPHERAL MAPPED I/O INTERFACING

In this method, the I/O devices are treated differently from memory chips. The control
signals I/O read ( IOR ) and I/O write ( IOW ), which are derived from the IO/M , RD and
WR signals of the 8085, are used to activate input and output devices, respectively.
Generation of these control signals is shown in Fig. 20. Table 11 shows the status of IO/M ,
RD and WR signals during I/O read and I/O write operation.

Fig. 20 Generation of IOR and IOW signals

IN instruction is used to access input device and OUT instruction is used to access output
device. Each I/O device is identified by a unique 8-bit address assigned to it. Since the
control signals used to access input and output devices are different, and all I/O device use
8-bit address, a maximum of 256 (28) input devices and 256 output devices can be
interfaced with 8085.

Table 11 Status of IOR and IOW signals in 8085.

IO/M RD WR IOR IOW Operation

1 0 1 0 1 I/O read operation
1 1 0 1 0 I/O write operation
0 X X 1 1 Memory read or write operation
Ex: Interface an 8-bit DIP switch with the 8085 such that the address assigned to the DIP
switch if F0H.

IN instruction is used to get data from DIP switch and store it in accumulator. Steps
involved in the execution of this instruction are:

i. Address F0H is placed in the lines A0 – A7 and a copy of it in lines A8 – A15.

ii. The IOR signal is activated ( IOR = 0), which makes the selected input device to
place its data in the data bus.
iii. The data in the data bus is read and store in the accumulator.

Fig. 21 shows the interfacing of DIP switch.

A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 0 0 0 0 = F0H

A0 – A7 lines are connected to a NAND gate decoder such that the output of NAND gate is
0. The output of NAND gate is ORed with the IOR signal and the output of OR gate is
connected to 1G and 2G of the 74LS244. When 74LS244 is enabled, data from the DIP
switch is placed on the data bus of the 8085. The 8085 read data and store in the
accumulator. Thus data from DIP switch is transferred to the accumulator.

Fig. 21 interfacing of 8-bit DIP switch with 8085

4. MEMORY MAPPED I/O INTERFACING

In memory-mapped I/O, each input or output device is treated as if it is a memory location.

The MEMR and MEMW control signals are used to activate the devices. Each input or
output device is identified by unique 16-bit address, similar to 16-bit address assigned to
memory location. All memory related instruction like LDA 2000H, LDAX B, MOV A, M
can be used.
Since the I/O devices use some of the memory address space of 8085, the maximum
memory capacity is lesser than 64 KB in this method.

Ex: Interface an 8-bit DIP switch with the 8085 using logic gates such that the address
assigned to it is F0F0H.

Since a 16-bit address has to be assigned to a DIP switch, the memory-mapped I/O
technique must be used. Using LDA F0F0H instruction, the data from the 8-bit DIP switch
can be transferred to the accumulator. The steps involved are:

i. The address F0F0H is placed in the address bus A0 – A15.

ii. The MEMR signal is made low for some time.
iii. The data in the data bus is read and stored in the accumulator.

Fig. 22 shows the interfacing diagram.

Fig. 22 Interfacing 8-bit DIP switch with 8085

When 8085 executes the instruction LDA F0F0H, it places the address F0F0H in the
address lines A0 – A15 as:

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 = F0F0H

The address lines are connected to AND gates. The output of these gates along with MEMR
signal are connected to a NAND gate, so that when the address F0F0H is placed in the
address bus and MEMR = 0 its output becomes 0, thereby enabling the buffer 74LS244.
The data from the DIP switch is placed in the 8085 data bus. The 8085 reads the data from
the data bus and stores it in the accumulator.