UNIT-III 8086 Interfacing: Semiconductor memories interfacing (RAM, ROM), Intel 8255

programmable peripheral interface, Interfacing switches and LEDS, Interfacing seven segment
displays, software and hardware interrupt applications, Intel 8251 USART architecture and
interfacing, Intel 8237a DMA controller, stepper motor, A/D and D/A converters, Need for 8259
programmable interrupt controllers.

3.0 Semiconductor Memory interfacing:

Memory is an integral part of a microcomputer system. There are two main
types of memory.
(i) Read only memory (ROM): As the name indicates this
memory is available only for reading purpose. The
various types available under this category are PROM,
EPROM, EEPROM which contain system software and
permanent system data.
(ii) Random Access memory (RAM): This is also known
as Read Write Memory. It is a volatile memory. RAM
contains temporary data and software programs
generally for different applications.
Memory Interface using RAMS, EPROMS and EEPROMS
Semiconductor Memory Interfacing: Semiconductor memories are of two
types, viz. RAM (Random Access Memory) and ROM (Read Only Memory).
Static RAM Interfacing:
The semiconductor RAMs are of broadly two types-static RAM and
dynamic RAM. The semiconductor memories are organised as two
dimensional arrays of memory locations. For example, 4K x 8 or 4K byte
memory contains 4096 locations, where each location contains 8-bit data and
only one of the 4096 locations can be selected at a time. Obviously, for
addressing 4K bytes of memory, twelve address lines are required. In
general, to address a memory location out of N memory locations, we will
require at least n bits of address, i.e. n address lines where n = Log2 N. Thus
if the microprocessor has n address lines, then it is able to address at the
most N locations of memory, where 2n = N. However, if out of N locations
only P memory locations are to be interfaced, then the least significant p
address lines out of the available n lines can be directly connected from the
microprocessor to the memory chip while the remaining (n-p) higher order
address lines may be used for address decoding (as inputs to the chip
selection logic). The memory address depends uponthe hardware circuit used
for decoding the chip select ( CS ). The output of the decoding circuit is
connected with the CS pin of the memory chip. The general procedure of
static memory interfacing with 8086 is briefly described as follows:
1. Arrange the available memory chips so as to obtain 16-bit data
bus width. The upper 8-bit bank is called ‘odd address memory bank’ and
the lower 8-bit bank is called ‘even address memory bank’.

2. Connect available memory address lines of memory chips with

those of themicroprocessor
and also connect the memory RD and WR inputs to the corresponding
processor control signals. Connect the 16-bit data bus of the memory bank
with that of the microprocessor 8086.
 3. The remaining address lines of the microprocessor, BHE and A0
are used for decoding the required chip select signals for the odd and even
memory banks. CS of memory is derived from the O/P of the decoding
circuit.
3.1 8255 PPI
Input and output devices, which are interfaced with 8085, are essential
in any microprocessor-based-system. They can be interfaced using two
schemes- I/O mapped I/O and memory mapped I/O. Both of these schemes
has been designed by complex hardware circuit and also it is dedicated for
only one type of device, such as Buffer based designed is accomplished only
for I/P devices and Latch based designed is accomplished only for O/P
devices; both of these design could not be used for reverse action.
To reduce this complex hardware circuit and versatility Intel
Corporation has introduce 8255 chip, which is commonly called
Programmable Peripheral Interface [PPI]. The 8255 has 24 I/O pins divided
into 3 groups of 8 pins each. The groups are denoted by port A, port B and
port C respectively. Every one of the ports can be configured as either an
input port or an output port.

Form the above block diagram it is noticed that any kind of I/O devices could
be connected with three ports like Port A, Port B, Port C. due to this features
buffer and latch devices are not needed for particular input or output
application so, user has flexibility to use same ports as input or output
application. Another advantage of this chip, that it can be operated in three
different modes which are basically not included in simple I/O interfacing;
these different types of operation extended the data transfer policies.
Functions of each block and pins: Data Bus Buffer- The tri-state
bidirectional 8 bit buffer is used to interface the 8255A to the microprocessor
data bus (D0-D7). Data is transmitted or received by buffer upon the
execution of input or output instructions by the CPU. Control word and status
word also transferred through this data bus buffer.
Read write control logic- The function of this block is to manage all the
internal and external transfers of both data and control or status word. This
block also handles user information regarding operational mode selection,
configuration of ports as an input or output; all of this information stored in
8-bit control word register (CWR). The details of each pin connected with this
block are described below,
𝑪 𝑺 (Chip Select)- A “Low” on this input pin enables the communication
between the 8085 and MPU.
A0 and A1 - These are the address lines of 8255 which are directly
connected to the MPU lower address lines (A0, A1). In conjunction with chip
select, control the selection of one of the three ports or the control word
register has been made. The bit combination of these signals are shown
bellow-

Group A and Group B controls- The functional configuration of each port is

programmed by the system software. The MPU “outputs” a control word to
the 8255 to set some information such as mode, bit-set/reset, etc. that
initialize the functional configuration of 8255. Each of control blocks (Group A
and Group B) accept commands from read/write control logic, receives
“control words” from the internal data bus and issue the proper commands to
its associate ports. Group A control- port A and Port C upper (PC4 – PC7)
Group B control – Port B and Port C lower (PC0 – PC3) The control word
register can be used for write operation and NO read operation is allowed in
this register.
Ports A, B and C- The 8255A contains three 8-bit ports (A, B and C). All can
be configured in a wide variety of functional characteristics by the system
software but each has its own special features to enhance the power and
flexibility of the 8255A. The major function of each ports has 8-bit Input or
Output, buffer or latch and only Port C can be configured as double 4-bit
latch, it is used for control signal output and status signal inputs in
conjunction with ports A and B.
8255 MODES
There are two different modes of 8255. These modes are:
 Bit Set Reset (BSR) Mode
 Input/ Output Mode(I/O Mode)
Bit Set Reset (BSR) Mode
This mode is used to set or reset the bits of the Port-C only. For BSR mode
always D7 will be 0. The control register is looking like this:
The (D3, D2, D1) will be 000 to 111. In this mode it affects only one bit of
Port C at a time. When user set the bit, it remains set until user unset it. The
user needs to load the bit pattern in control register to change the bit.

Input/ Output Mode

This mode is selected when the D7 bit of the control register is 1.
This mode has also three different modes. These modes are Mode 0 and Mode
1 and Mode 3.
Mode 0 – Simple or basic I/O Mode
Mode 0 (Basic Input/Output) : This functional configuration provides simple input and output
operations for each of the three ports. No handshaking is required, data is simply written to or read
from a specific port.
• Mode 0 Basic Functional Definitions:
 Two 8-bit ports and two 4-bit ports
 Any Port can be input or output
 Outputs are latched
 Input are not latched
 16 different Input/Output configurations possible
Mode 1 – Handshake or Strobed I/O
This functional configuration provides a means for transferring I/O data to or
from a specified port in conjunction with strobes or “hand shaking” signals. In
mode 1, port A and port B use the lines on port C to generate or accept these
“hand shaking” signals.
Mode 1 Basic Function Definitions:
 Two Groups (Group A and Group B)
 Each group contains one 8-bit port and one 4-bit control/data
port
 The 8-bit data port can be either input or output. Both inputs and
outputs are latched.
 The 4-bit port is used for control and status of the 8-bit port.
Mode 3 – Bidirectional I/O
In this mode only Port A can work, and port B can either be in mode 0 or
mode 1, and the port C are used for handshaking. In this mode the inputs
and outputs are latched. The control register is looking like below in this
mode:
 Used in Group A only
 One 8-bit, bi-directional bus Port (Port A) and a 5-bit control Por t (Por
t C)
 Both inputs and outputs are latched
 The 5-bit control port (Port C) is used for control and status for the 8-
bit, bi-directional bus port (Por t A)
Bits Function

D7 1 for IO mode and 0 for BSR mode

D6 & D5 These are used to set port A mode. for 00, it is m0 mode, for 01, it is m2
mode and 10 or 11, it is m2 mode.
D4 1 when port A is taking input, 0 when port A is sending output.

D3 1 when higher nibble of port C is taking input, and 0 when higher nibble is
sending output.
D2 It tells the mode of Port B. For 0, it is m0 mode, and for 1, it is m1 mode.

D1 1 when port B is taking input, 0 when port B is sending output.

D0 1 when lower nibble of port C is taking input, and 0 when lower nibble is
sending output.
3.2 Interfacing switches and LEDS
Example 1:- Interface an 8255 chip with 8086 to work as an I/O port.
Initialize port A as output port, Port B as I/P port and Port C as O/P port. Port
A address should be 0740H. Write an ALP to sense switch positions SW0–SW7
connected at port B. The sensed pattern is to be displayed on port A, to which
8 LED's are connected, while port C lower displays number of on switches out
of the total eight switches ?
The 8255 is to be interfared with lower order data bus; i.e. D0-D7.
The A0 and A1 pins of 8255 are connected to A1 and A2 pins of the
microprocessor respectively. We will use absolute decoding scheme that uses
all the 16 address lines.
For deriving the device address pulse. Out of A0– A15 lines, two
address lines A2 and A1 are directly required by 8255 for three port and CWR
address decoding. Hence only A3 to A15 are used for decoding addresses.
Circuit diagram, the 8086 is assumed to be in the maximum mode so
that IORD and I OWR are readily available.
3.3 Interfacing seven segment displays,
Example 3:- Interface an 8255 with 8086 at 80H as an I/O address of Port A.
Interface five 7 segment displays with the 8255. Write an ALP to display 1, 2,
3, 4 and 5 over the 5 displays continuously as per their positions starting with
1 at the least significant position ?
 3.4 software and hardware interrupt applications
Hardware interrupt-
These interrupts occur as signals on the external pins of the
microprocessor. 8086 has two pins to accept hardware interrupts, NMI
and INTR.
Software interrupt-
These interrupts are caused by writing the software interrupt instruction
INT n where ‘n’ can be any value from 0 to 255 (00H to FFH). Hence all
256 interrupts can be invoked by software.
Applications of interrupts:
1. Applications of interrupts include the following: system timers, disk I/O,
power-off signals, and traps.
2. Other interrupts exist to transfer data bytes using UARTs or Ethernet;
sense key-presses; or anything else the equipment must do.
3. Another typical use is to generate periodic interrupts by dividing the
output of a crystal oscillator and having an interrupt handler count the
interrupts in order for a processor to keep time.
4. These periodic interrupts are often used by the OS's task scheduler to
reschedule the priorities of running processes.
5. Some older computers generated periodic interrupts from the power
line frequency because it was controlled by the utilities to eliminate
long-term drift of electric clocks.
6. For example, a disk interrupt signals the completion of a data transfer
from or to the disk peripheral; a process waiting to read or write a file
starts up again.
7. As another example, a power-off interrupt predicts or requests a loss of
power, allowing the computer equipment to perform an orderly shut-
down.
8. Also, interrupts are used in type ahead features for buffering events
like keystrokes.
3.5 ADC 0808/0809:
 The analog to digital converter chips 0808 and 0809 are 8-bit CMOS,
successive approximation converters. This technique is one of the fast
techniques for analog to digital conversion. The conversion delay is 100µs at
a clock frequency of 640 KHz, which is quite low as compared to other
converters. These converters do not need any external zero or full scale
adjustments as they are already taken care of by internal circuits.
 These converters internally have a 3:8 analog multiplexer so that at a time
eight different analog conversion by using address lines - ADD A, ADD B,
ADD C, as shown. Using these address inputs, multichannel data acquisition
system can be designed using a single ADC. The CPU may drive these lines
using output port lines in case of multichannel applications. In case of
single input applications, these may be hardwired to select the proper
input.
 There are uni polar analog to digital converters, i.e. they are able to
convert only positive analog input voltage to their digital equivalent. These
chips do not contain any internal sample and hold circuit.
 If one needs a sample and hold circuit for the conversion of fast signal into
equivalent digital quantities, it has to be externally connected at each of the
analog inputs.
Table.1

Address lines
Analog I/P selected
C B A
I/P 0 0 0 0
I/P 1 0 0 1
I/P 2 0 1 0
I/P 3 0 1 1
I/P 4 1 0 0
I/P 5 1 0 1
I/P 6 1 1 0
I/P 7 1 1 1
Some Electrical Specifications Of The ADC 0808/0809 Are Given In Table.2.
3.6 DAC 0808 Interfacing to 8086

 DAC 0808 is an 8 bit Digital to Analog Converter. It can convert an 8 bit

digital data input into an analog voltage output.
 Reference voltage for conversion is provided using +Vref and –Vref.
The output can be amplified (optional) using an op-amp.
 DACs are used in various applications such as Waveform generation,
PWM, Motor control Applications, DSP etc. Here we connect the output
to a display device like a CRO.
 By simple programming we can generate several types of wave forms
like Ramp, Saw-tooth, Triangular waveform etc.
 The output from 0808 DAC is current, so we need current to voltage
converter at output of DAC as shown in figure below:
 The DAC will accept a digital (binary) input and convert to analog
voltage or current. Every DAC will have "n" input lines and an analog
output.
 The DAC require a reference analog voltage (Vref) or current (Iref)
source.
 The smallest possible analog value that can be represented by the n-bit
binary code is called resolution. The resolution of DAC with n-bit binary
input is 1/2n of reference analog value. Every analog output will be a
multiple of the resolution. In some converters the input reference
analog signal will be multiplied or divided by a constant to get full scale
value. Now the resolution will be 1/2n of full scale value.
Forexample:
Consider an 8-bit DAC with reference analog voltage of 5 volts.
Now the resolution of the DAC is (1/28) x 5 volts.
The 8-bit digital input can take, 28 = 256 different values.
The analog values for all possible digital input are as shown in table
below.

 The maximum input digital signal will have an analog value which
is equal to reference analog value minus resolution.
 The digital-to-analog converters can be broadly classified into
three categories, and they are
• Currentoutput
• Voltageoutput
• Multiplyingtype
 The current output DAC provides an analog current as output
signal.In voltage output DAC, the analog current signal is
internally converted to voltage signal.
3.7 Stepper Motor Interfacing:
 A stepper motor is a device used to obtain an accurate position control of
rotating shafts. It employs rotation of its shaft in terms of steps, rather
than continuous rotation as in case of AC or DC motors. To rotate the
shaft of the stepper motor, a sequence of pulses is needed to be applied
to the windings of the stepper motor, in a proper sequence.
 The number of pulses required for one complete rotation of the shaft of
the stepper motor is equal to its number of internal teeth on its rotor.
The stator teeth and the rotor teeth lock with each other to fix a position
of the shaft.
 With a pulse applied to the winding input, the rotor rotates by one teeth
position or an angle x. The angle x may be calculated as:
X=3600/no. of rotor teeth
 After the rotation of the shaft through angel x, the rotor locks itself with
the next tooth in the sequence on the internal surface of stator.
 The internal schematic of a typical stepper motor with four windings is
shown in fig.1.
 The stepper motors have been designed to work with digital circuits.
Binary level pulses of 0-5V are required at its winding inputs to obtain
the rotation of shafts. The sequence of the pulses can be decided,
depending upon the required motion of the shaft.

 The circuit for interfacing a winding Wn with an I/O port is given in fig.4.
Each of the windings of a stepper motor needs this circuit for its
interfacing with the output port. A typical stepper motor may have
parameters like torque 3 Kg-cm, operating voltage 12V, current rating
0.2 A and a step angle 1.80 i.e. 200 steps/revolution (number of rotor
teeth).
 A simple schematic for rotating the shaft of a stepper motor is called a
wave scheme. In this scheme, the windings Wa, Wb, Wc and Wd are
applied with the required voltages pulses, in a cyclic fashion. By
reversing the sequence of excitation, the direction of rotation of the
stepper motor shaft may be reversed.
Table.1 shows the excitation sequences for clockwise and anticlockwise
rotations. Another popular scheme for rotation of a stepper motor shaft
applies pulses to two successive windings at a time but these are shifted only
by one position at a time. This scheme for rotation of stepper motor shaft is
shown in table2.
3.8 8251 USART
8251 USART is a universal synchronous and asynchronous controller
designed by Intel basically to facilitate communication.USART stands
for Universal Synchronous and Asynchronous Receiver Transmitter and
functions as an intermediary that allows serial and parallel communication
between the microprocessor and the peripheral devices.
We know that microprocessors allow parallel communication. And in
parallel communication, the number of cables required for data transmission
is equal to the number of bits to be transmitted per cycle.
Thus the approach of transmitting data parallelly to long distance is cost-
ineffective.
So, to reduce the overall cost of the system despite parallel data
communication between the processor and peripheral devices, the serial
transfer of data is permitted.
Hence for this purpose, USART acts as a mediator between the
processor and peripheral devices so, that the parallel data from the processor
can be converted into serial data and efficiently transferred to the peripheral
devices.
In a similar way, the serial data from the peripheral devices is
converted by the USART into the parallel form so that it can be accepted by
the processor.
Also, it allows both synchronous and asynchronous transmission and
reception thus is called so.Architecture and Working of 8251 USART
The figure below shows the architectural representation of 8251:

Let us
now understand the operation performed by each unit in detail:
1. Data Bus Buffer: It basically interfaces the 8251 with the internal system
buses of the processor.
The data bus buffer has 8-bit bidirectional data bus that allows the transfer of
data bytes, status or command word between the processor and external
devices.
2. Read/Write Control Logic: This functional unit generates a control signal
for the operation of 8251 according to the signal present in the control bus of
the processor. Basically, it performs decoding operation of the control signal
produced by the processor, so that respective operation can be performed by
the USART.
The control formats for system operation is stored in control and command
word registers present in the read/write logic unit.
 CS: It is chip select. A low signal at this pin shows that processor has
selected 8251 in order to communicate with the peripheral devices.
 C/D: As the system has control, status and data register. So, when a high
signal is present at this pin then control or status register is addressed.
While in case of low signal data register is addressed.
 RD and WR: Both read and write are active low signal pins. A low signal at
RD shows that the processor is reading the control, status or data bytes
from the 8251. While at WR indicates the write operation over the data
bus of 8251.
 CLK and RESET: CLK stands for clock and it produces the internal timing
for the device. While an active high signal at the RESET pin puts the 8251
in the idle mode
3. Transmit Buffer: This unit is used to change the parallel data received
from the CPU into serial data by inserting the necessary framing information.
Once the data is transformed into serial form, then in order to transmit it to
the external devices, it is provided to the TxD pin of the 8251.
This unit consists of 2 registers. These are as follows:
 Buffer register: Basically the data provided by the processor is stored in
the buffer register. As we know that initially, the CPU provides parallel
data to 8251. So, the processor loads the parallel data to the buffer
register. Further, this data is fed to the output register.
 Output register: The parallel data from the buffer register is fed to the
empty output register.
This register changes the 8-bit parallel data into a stream of serial bits.
Then further the serial data is provided at the TxD pin so as to have its
transfer to the peripheral device.
4. Transmit Control: As the name of the unit is itself indicating that it is
controlling the transmission action. And it does so by accepting and sending
signals both externally and internally.
The various control signal generated by this unit are as given below:
 TxRDY: It implies transmit ready. This signal is used to notify the
processor that the buffer register of the 8251 is empty and ready to accept
the data.
The status read operation is utilized by the processor in order to check the
presence of the signal.
 TxE: This stands for transmitter empty. It is an active high signal that
indicates that the output buffer is empty and thus data received from the
processor can be loaded to it for conversion.
 TxC: It stands for transmitter clock and is an active low pin. It controls the
rate of character transmission by the USART.
However, 8251 offers programmable clock rate. As by writing appropriate
mode word in the mode set register the clock division can be programmed.
5. Receive Buffer: This unit takes the serial data from the external devices,
changes the serial data into the parallel form so that it can be accepted by
the processor. It consists of 2 registers: receiver input register and buffer
register.
When the external device is ready to send the data to the 8251 then it sends
a low signal to the RxD line of the 8251. In asynchronous mode, once 8251
receives a low signal it considers that signal as start bit of the data.
6. Receiver Control
This unit controls the operation of the receiver buffer. It manages the data
reception, along with that it also detects the presence of false start bit, error
in parity bit, framing errors etc.
 RxRDY: It stands for receiver ready. When this signal goes high then it
indicates that the receiver buffer register is holding the data and is ready
to transfer it to the processor. Once the CPU reads the data sent by the
8251 then this pin is reset.
 RxC: It stands for receiver clock. This clock signalling controls the rate at
which the 8251 receives the data in the synchronous mode of operation. It
is provided by the modem and is equal to the baud rate.
While asynchronous mode offers the clock rate as 1, 16 or 64 times of the
baud rate as it is programmable.
7. Modem Control: This unit of 8251 holds input and output control signals
that simplify the operation of the whole system. The control circuitry for
handing various signals is provided by the modem control unit. It includes
DTS, RTS, DTR and CTS.
These are all active low signals.
 DSR: Stands for data set ready and the signal is used to check whether
the data set is ready or not when the processor is in the urge of
communication.
 DTR: Implies data terminal ready. An active-low signal at this pin shows
that the 8251 is now ready to accept the data from the processor.
 RTS: It stands for the request to send. A low signal shows an assertion for
data transmission.
 CTS: Clear to send. When 8251 receives a low signal at this pin then it
clears all the data present in the modem in order to allow further
communication.
3.9 INTERFACING 8251A TO 8086 PROCESSOR
• The chip select for I/O mapped devices are generated by using a 3-to-8
decoder.
• The address lines A5, A6 and A7 are decoded to generate eight chip select
signals (IOCS-0 to IOCS-7) and in this, the chip select signal IOCS-2 is used
to select 825lA.
• The address line A0 and the control signal M/IO(low) are used as enable for
decoder.
• The line A1 of 8086 is connected to C/D(low) of 8251A to provide the
internal addresses.
• The lines D0 – D7 connected to D0 – D7 of the processor to achieve
parallel data transfer.
In 8251A the transmission and reception baud rates can be different or same.
• The TTL logic levels of the serial data lines and the control signals necessary
for serial transmission and reception are converted to RS232 logic levels
using MAX232 and then terminated on a standard 9-pin D-.type connector.
• The device, which requires serial communication with processor, can be
connected to this 9-pin D-type connector using 9-core cable.
• The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to
initiate interrupt driven data transfer scheme between processor and 8251 A.
• The I/O addresses allotted to the internal devices of 8251A are listed in
table.
3.10 8237 DMA
Direct Memory Access (DMA) is an I/O technique commonly used for
high-speed data transfer; for example , data transfer between memory and a
floppy disk. In DMA, µP releases the control of the buses to a device called
a DMA controller. The controller manages data transfer between memory and
a peripheral under its control, thus bypassing the MPU It introduces two new
signals HOLD (pin 39) and HLDA (pin 38) (Hold acknowledge)
HOLD:This is an active high input signal Pin number 39 The
processor relinquishes (gives up) the buses in the following machine cycle
once the MPU receives the HOLD request All buses are tri-stated and HLDA
(Hold Acknowledge) signal is sent out MPU regains the control of the buses
after HOLD goes low
HLDA:This is an active high output signal Pin number 38 It indicates
that the MPU is giving up the control of the buses
The DMA controller should have I. A data bus II. An address bus III.
Read/Write control signals, and IV. Control signals to disable its role as a
peripheral and to enable its role as a peripheral

Features: 8237 is a programmable Direct Memory Access controller

 (DMA) housed in a 40-pin package
 It has four independent channels with each channel capable of 
transferring 64K bytes
 It must interface with MPU and a peripheral device It is an I/O device
to MPU
 It is a data transfer processor to peripheral device  Many of its signals
that are input in the I/O mode become outputs in the processor mode
Description
 The block diagram shows a logical pin out and internal registers of the
8237. It also shows the interface with the 8085 using a 3-to-8 decoder
 8237 has four independent channels CH0-CH3. Two 16-bit registers
are internally associated with each channel
 These registers are determined by A3-A0 and the chip select line (CS)
 The 8237 signals are divided into two groups: 
 1) signals on left (used to communicate with MPU)
 2) signals on right (used to communicate with peripheral)
 Some of these signals are bidirectional and are determined by  the DMA
mode of operation (I/O or processor mode)
 To obtain DMA service , a request is generated by activating  the DREQ
line of the channel DACK are output lines to inform the individual
peripherals that DMA is granted. DREQ and DACK are eqvt to
handshake signals in I/O devices AEN and ADSTB-Address Enable and
Address Strobe are used to latch a high-order byte to generate a 16-
bit address After receiving the HRQ (Hold request), the MPU
completes the bus cycle in process and issues the HLDA (Hold
Acknowledgement) signal
 When a transfer begins, the DMA places the low-order byte on the
address bus and high-order byte on the data bus Then 8237 asserts
AEN (Address Enable) and ADSTB (Address Strobe) Theses two
signals are used to latch the high-order byte from the data bus and
8237 places the 16-bit address on the system bus
 When a transfer begins, the DMA places the low-order byte on the
address bus and high-order byte on the data bus Then 8237 asserts
AEN (Address Enable) and ADSTB (Address Strobe) Theses two
signals are used to latch the high-order byte from the data bus and
8237 places the 16-bit address on the system bus
3.11 8259 Programmable Interrupt Controller
Need of Programmable Interrupt Controller
We know whenever an interrupt occurs then the microprocessor
suspends the current program and switches to the Interrupt Service Routine
(ISR).
We know 8086 has 2 interrupts, which are: NMI and INTR.
Among all these, only INTR is a non-vectored type of interrupt, rest are
vectored interrupts.
We know vectored interrupts are those interrupts whose ISR address is
known to the processor. Or we can say in case of vectored interrupts, the
processor holds the address of the memory location where ISR is stored.
But in case of non-vectored interrupts, the processor has to reach the
ISR but it does not hold the address of ISR. So, in this case, the interrupt
generating device provides the ISR address to the microprocessor.
Features of 8259
1. The 8259 programmable interrupt controller has 8 interrupt pins thus can
handle 8 interrupt inputs.
2. The priority of interrupts in 8259 can be programmed. The priority of
interrupts is decided by the different operating modes.
3. We know that a single 8259 can handle 8 interrupt inputs but by cascading
multiple 8259, it can handle maximal 64 interrupt inputs.
4. 8259 allows individual masking of each generated interrupt using interrupt
mask register.
5. 8259 is programmed in a way that it can handle either edge-triggered or
level-triggered interrupt request at a time.
6. If multiple interrupts are generated, then 8259 holds the status of
interrupts that are masked, in-service and pending.
7. It reduces the software and real-time overhead generated due to handling
multilevel priority interrupts.
Architecture of 8259
The figure below shows the architectural representation of 8259
programmable interrupt controller:
It has an 8-bit of data bus. As we have already discussed that 8259
never services the interrupt, it simply forwards the interrupts to the
microprocessor.
Thus, the above architecture has different units that combinely
functions to increase the interrupts handled by the processor.
1. Data Bus Buffer: 8259 has tri-stated bidirectional 8-bit data bus buffer
(i.e., D0 to D7) that interfaces with the internal bus of the processor. The
8085 microprocessor sends/ receives, control or status words to/ from the
8259 using data bus buffer.
2. Read/ Write Logic: This unit is responsible for controlling the internal
read-write operations of the system. It holds initialization command word
register and operation command word register inside which various control
formats exist that are needed for the device operation.
RD, WR, A0 and CS are the pins that are associated with this unit. Basically,
these pins are used by the processor for read and write operations.
3. Control Logic: This unit is the heart of the architecture of 8259. It
controls the overall operation of the system by sending the INTR signal to the
processor whenever an interrupt request is generated.
4. Interrupt request register (IRR): This unit stores the interrupt
requests generated by the peripheral devices. We know that 8259 has 8
interrupt request pins (i.e., IR0 to IR7). So, the unit can store 8 interrupt
requests that are requesting the service from the processor.
5. Priority Resolver: This logic unit decides that among all the interrupt
request present in the IRR which holds the highest priority and needs to be
executed first.
6. In-service register: Here the name of the unit is itself indicating the
operation performed by it. This register unit stores the interrupts which are
currently being executed by the processor.
7. Interrupt mask register: This register unit holds the masking bit of
those interrupts which are to be masked. Through operation command word
(OCW) the processor sends the required information and programs the
interrupt mask register.
8. Cascade buffer/comparator: As we have already discussed that by
cascading multiple 8259, the number of interrupts handled by 8259 can be
expanded up to 64. The unit allows the comparison of IDs of different 8259s
cascaded together.
3.12 Interfacing of 8259 with 8086 in minimum mode.

1. Figure below shows that how an 8259 can be interfaced with the 8086
microprocessor system in minimum mode. In case of 8086
microprocessor same interfacing diagram can be used except M/I0
signal.

1. The 74LS138 address decoder will assert the CS input of the 8259 when
an I/O base address is FFF0H or FFF2H on the address bus.
2. The A_0 input of the 8259A is used to select one of the two internal
addresses in the device. Ao of the 8259A is connected to system line Al.
So the system addresses for the two internal addresses are FFF0H and
FFF2H.
3. The data lines of an 8259 are connected to the lower half of the system
data bus; because the 8086 expects to receive interrupt types on these
lower eight data lines.
4. RD and WR signals are connected to the system RD and WR lines.
5. The interrupt request signal INT from the 8259 is connected to the
INTR input of the 8086 and INTA from the 8086 is connected to INTA
on the 8259A. As we are using single 8259 in the system SP/EN pin is
tied high and CAS0-CAS2 lines are left open.
6. The eight IR inputs are available for interrupt signals.
7. Cascading :
8. The 8259 can be easily interconnected to get multiple interrupts. Fig
below shows how 8259 can be connected in the cascade mode. In
cascade mode one 8259 is configured in Master mode and other should
be configured in the Slave mode. In this figure 8259 is in the master
mode and others are in slave mode. Each slave 8259 is identified by the
number which is assigned as a part of its initialization. Since the 8086
has only one INTR input, only one of the 8259 INT pins is connected to
the 8086 INTR pin. The 8259 connected directly into the 8086 INTR pm
is referred as the master. The INT pins from other 8259 are connected
to the IR inputs of the master 8259. These cascaded 8259s are referred
as slave. The INTA signal is connected to both master and slave 8259.
9. The cascade pins CAS0 to CAS2 are connected from the master to the
corresponding pins of the slave. For the master these pins function as
outputs, and for the slave these pins function as inputs. The SP/EN
signal is tied high for the master. However it is grounded for the slave.
10. Each 8259A has its own addresses so that command words can
be written to it and status bytes read from it.