or cara wean, Yat area (seme Zi) GOVERNMENT OF INDIA ( MINISTRY OF DEFENCE (R&D) =f Sa gee - chen site werettereon arz ¢ an: Sra Grams : CEMILAC WH / Phone : 52 30355 ao ware qe rere (564 - eer) CENTRE FOR MILITARY a eee rr ag ot Fe = AIRWORTHINESS & CERTIFICATIC sftor & sem 8 regret caret (wee) Fi ceescaoice oud actos 0 MARATHAHALLI COLONY (POST) fe Chil Execuve Arworhness) and nto “dmratt- 560 037. wre anyone by ose BANGALORE - 560 037. INDIA CEMILAC! 539044 [© Jan 2004 CEMILAC DIRECTIVE NO. 81 / 2003 SCREENING PROCEDURE FOR COTS COMPONENTS / PCBs Due to non-availability of qualified MIL specification electronic components in some cases it may become unavoidable to resort to the use of “COTS” components. ‘These components are required to be screened before being used in the avionic equipments so as to ensure the reliability. Also, in some cases it is not practicable to carryout screening at component level. In these cases, the PCBs which are populated with unscreened COTS components will have to be Subjected to the screening. 2. The procedure to be followed for screening of both i.e discrete as well as PCB levels is enclosed at Appendix ‘A’ and is hereby promulgated for all airborne applications, 3 These screening procedures are also being proposed to be included in JSG 761:2001 of the Directorate of Standardisation as amendment to the existing JSG Ses \ pes (aK SHARMA) Sc Chief Executive (A) Encl: Appendix A Distribution ~ 1. AllGD's 2. AIlRCMA's Gp (Te 4S) fee py. rr [e390 Phone S2306A0 / 5234091 / 234674 Fax 5930856 | 5234607 / 5234781 Ema cecemilacktyahon vi «0.1 S SCREENING PROCEDURES FOR COTS COMPONENTS Purpose: This Test Procedure read in conjunction with clause 15 of JSG 761:2001 describes Screening test procedures for Service Electronic Components procured as COTS Components or PCBs. The tests specified herein are intended to screen out components having manufacturing defects and potential early life failures Screening test procedures are a group af tesis imposed on a production batch to assist in achieving the desired levels of Quality and Reliability for the Components commensurate with intended application. In general, options for performing screening tests are as follows a) Screening by the Manufacturer : Screening Tests may be done at the components Manufacturers end. The cost of such testing is likely to be low b) Screening by the User : Screening Tests may be performed by the User or Original Equipment Manufacturer (OEM) whenever such facilities exist with them. The test data integrity would be high in such cases ©) Screening by using independent test laboratories: Screening test may be performed by using the test facilities and services available at the independent test laboratories. In such cases also, the test data integrity would be high NOTE : In any case, use of COTS components of commercial grade wit! temperature 0 to+70°C is not permitted for aviation application This Screening procedure is applicable only for COTS components and is not called for MIL grade / QML components / screened as per JSS 50115 If any difficulties are encountered in adhering to the established component screening procedures, the Test Procedures in the subsequent paragraphs may be adopted. F the experience already gained, it is seen that SMDs (in roll or tape form) are not screenable at the components level at the User end. Therefore, the best option is to select SMDs from the QML source However, if SMOs of QML sources are not available, the SMDs of COTS category may be qualified at card level 0.2 Related Documents Joint Service Specifications JSS 50101 1996 ENVIRONMENT TEST METHODS FOR SERVICE ELECTRONIC COMPONENTS, JSS 50115 1999 SCREENING TEST PROCEDURES ON ELECTRONIC COMPONENTSmE JSG 755: 2001 UNIFORM IMPLEMENTATION OF COTS PERTAINING TO ELECTRONIC COMPONENTS IN THE SERVICES. JSG 761: 2001 FORMULATION OF QUALITY ASSURANCE PROCEDURE: COTS ITEMS (AVIONICS). Other Specifications: MIL STD 202 TEST METHOD FOR ELETRONIC AND ELECTRICAL COMPONENT PARTS MIL STD 883: TEST METHODS AND PROCEDURES FOR ey MICROELECTRONICS MiL-M-38535: GENERAL SPECIFICATION FOR INTEGRATED CIRCUITS (MICROCIRCUITS) 4 PART-A 1.0 SCREENING TESTS FOR DISCRETE COMPONENTS 1.1 HIGH TEMPERATURE STORAGE Title of Test_ TestDetails ______ [Requirements | High temperature | As per Test Number 22 of JSS 50101: |) Visual examination Storage NOTES: ii) Electrical parameters (Stabilisation la) Components requiring screening shall | tests at ambient NY « Bake) test be placed in a Metal tray be kept in the| temperature | chamber lo) The chamber temperature shall be increased to Maximum Rated Storage Temperature specified forthe components under test >) The components shall be exposed for | = 24 hours continuously at the specified Maximum storage temperature. j 1.4.1 After visual examination and electrical tests the components shall be selected which have met the requirements and be subjected to the following test(s)1.2 THERMAL SHOCK tle of Test Test Details - Requirements Thermal Shock | As per Tesi Number 20 of JSS 50101, | On completion of 10 Procedure 1, 10 Cycles, period of | Cycles of thermal shocks exposure is 30 minutes, transfer time is 2 | and recovery carry out minutes. a) Visual examination NOTES: b) Electrical Parameters / 2) The components shall be placed in| (DC electrical for ICs) the tray or any suitable container and] _ tests on the component: introduced in the chamber already] at ambient temperature stabilized at extreme low storage temperature of the components. b) The tay to be transferred to the chamber already stabilized at extreme high storage temperature of the components. 1.2.1 After completion of visual examination and electrical tests, the components which have met the requirements may be taken up for further tests 1.3 SEALING'TESTS Unless specified, hermetically sealed components shail be subjected to leak test in accordance with JSS 50101 Test Method 18 | MIL-STD-202E Method 1126 or Mit STD-883 Method 1014.1 as applicable. I hermetically sealed component has been screened for hermiticity on 100% basis at manufacturer's facility as a part of reliability program, then this test need not be carried out. Conformance certificate must be produced. 1.4 ELECTRICAL TESTS FOR NON-SMD COMPONENTS: ] Tests to be done for jo. | Value to be checked for 100% of the batch | Value to be checked for 100% atch "Value to be checked for 100% of the batch 1" Smooth rotation with value | No jerks or discontinuities Fates eater | (To be conducted on 100% of the batch) e) Potentiometer with switch = Smooth rotation with value \ No jerks or discontinuities | im Components Category N 2) Leaded Resistors of all varieties b) | Capacitors of all varieties ¢) _| Inductors of all varieties d) | Potentiometer - For positive switching action aia Site (To be conducted on 100% of the batch) Diodes, Transistors and Zener ' Checks for DC Parameters on curve tracer ‘or semiconductor tester. To be conducted Diodes on 100% of the batch f) Paved9) ] Sensor module PC checks to be done by inserling in to the reference Receivers a ne To be conducted on 100% of the batch. hy) | DC-DC Converter ‘As a module using separate fest Jig. To be conducted on 100% of the batch 1.5 ACCEPTANCE CRITERIA: The batch shall be accepted / rejected ater completion of screening tests on components, as per defined criteria established with the concerned Quality Assurance Authority 1.6 ASSEMBLY PRACTICES: The PCB shall be assembled with the components passed the above Screening tests, SMD components are permitted to be used provided they have been procured from MILIQMLQPL sources. The General Industry Standard/General Assembly drawing to be followed. The assemble« PCB shall be suitably marked for identification and traceability. NOTE : Caution to be exercised in control of moisture absorption in Plastic Encapsulated Microcitcuits (PEMs). This involves keeping the PEMs packages as dry as possible by any one of the methods such as stprage in a desiccant environment, high temperature bake (+125°C sfor 16 to 24 hours) and low temperature bake (limited to +40°C and iow RH < 10% using dry nitrogen or dry air purge). PART- B 2.0 SCREENING TESTS OF POPULATED PCBs Purpose: This procedure applies to PCBs populated with COTS Components The PCB level screening shall be adopted only when it is not possible to undertake 100% component level screening and in that case components are not required to be screened separately. 24 VISUAL EXAMINATION Title of Test: | Test Details ie [ Requirements Visual a) Carryout physical/visual examination | As specified Examination |” of the assembled PCB for non- | conformities / abnormalities and correct the same b] Performance check As specified in QTP/ATP.= 2.2. HIGH TEMPERATURE STORAGE (STABILISATION BAKE) TEST Title of Test Test Detai High Temperature | Storage | (Stabilisation Bake) test | Staeenealates chamber temperature tolerance +5°C J assembled PCB for 24 | continuously at +65°C. [Requirements ‘As per Test Number 22 of JSS 0101, | Visual examination and after Introduction of PCBs, increase the to +85°C with -0°C. Expose the Functional checks at ambient temperature Record failure observed, if hours | any. a z 2.3. REWORK. Repair/replace components as required using fresh components. The new components must undergo Stabilization Bake test before assembly 24 THERMAL SHOCK TEST: The PCB which has undergone the test at paragraph 2.2 above shall be subjected to 10 cycles of continuous Thermal Shook (in power “OFF' condition) as follows : » [Title of Test Test Details ‘Thermal ‘Shock Test Visual Examination Elecirical_ 0° /- 5°C of - OC/+5°C. Period of exposure : 30 Minutes Transfer time : 2 Minutes No. of Cycles : 10 Operation : OFF Condition. On completion of 10 cycles, carryout — | visual examination using magnifying | glass with magnification factor of 30 for detection of failures | Carryout Performance Checks | Measurements | sper OTP As per Test Number 20 Of JSS 50101 Low Temperature : -40°C with tolerance ligh Temperature : +85°C with tolerance Requirements t PCB assembly musi be free from any visual damages or distortions namely cracking | and delamination of finishes cracking and crazing of embedding and encapsulating | compounds, opening of | thermal seals and case | seams, leakage of filing materials, rupturing or cracking of hermetic seals, and changes in electrical characteristics due to mechanical displacement or rupture of conductors o of insulating material's t As specified in QTP 2.5 ACCEPTANCE CRITERIA In case of failure, analyze the defects in consultation with Certification / Quality Assurance Agency Failed component(s) shall be replaced and new components shall undergo Stabilisation Bake and Thermal Shock before assembly Repeat visual examination and performance checks26 Test 27 28 29 240 of Test [| BURN-IN 1 BURN-IN TEST Test Deta __[ Requirements PCB shall be placed in a chamber. All arrangements: ‘shall be made externally to carry out Functional Checks on the PCB at every five houre period. This constitutes one cycle of 5 hrs 2. The temperature of the chamber shall be raised to maximum rated operating temperature, the populated PCB is designed to perform with tolerance of +5°C /-0°C 3. PCB shall be maintained at this temperature continuously for'48 hours in Power ON concition. 4. In case of failure, the component(s) shall be replaced by components which have under gone and passed high | temperature storage and thermal shock before assembly | and continue the test for remaining hours. If the failure | occurs after the 46" / 47" /48 hour, expose the PCB for | further 03 hours to confirm the adequacy of the repair work The last 3 ‘hours shall be detect free 5. On completion of burn-in test, switch off the chamber 6. Take out the PCB assembly for conducting visual examination PCB assembly shall be ftee from any visual damages or distorlions as stipulated at 2.4 above 7. Carry out the performance checks as per QTP on the and record the results MARKING The assembled PCB on passing the above tests shall be marked Suitably for easy identification to avoid. mixing up of screened and unscreened PCBs POST BURN-IN: Subject the PCB assembly for complete Performance Checks as per-the respective test documents. If the PCB assembly cannot be tested independently insert it in the system / test rig and check for the performance Any non - conformities found during functional checks are to be recorded for further analysis ang intiate appropriate corrective action STORAGE Preserve the screened PCB assembly (duly marked for identification) in anti-static pouches safely and controlled environment for further integration with the equioment RECORD Keep a record of all stage inspections and performance checks on the PCB. identilied with its serial number for later verificanion and taceability