[go: up one dir, main page]
Scribd
Upload
86 views3 pages

Advanced Verification Syllabus

The course 'Advanced Formal and Functional Verification' provides an in-depth understanding of simulation-based and formal verification methodologies in digital system design, covering advanced strategies and real-world applications. Students will learn to differentiate between verification techniques, utilize simulation tools, and apply formal concepts like model checking and theorem proving. The syllabus includes topics on verification methodologies, simulation techniques, formal principles, advanced strategies, and industry practices, supported by key textbooks and reference materials.

Uploaded by

reskarthic
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
86 views3 pages

Advanced Verification Syllabus

The course 'Advanced Formal and Functional Verification' provides an in-depth understanding of simulation-based and formal verification methodologies in digital system design, covering advanced strategies and real-world applications. Students will learn to differentiate between verification techniques, utilize simulation tools, and apply formal concepts like model checking and theorem proving. The syllabus includes topics on verification methodologies, simulation techniques, formal principles, advanced strategies, and industry practices, supported by key textbooks and reference materials.

Uploaded by

reskarthic
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 3

Course Title: Advanced Formal and Functional Verification

Credits: 3 | Duration: 35 Hours | Level: UG/PG (Advanced Level)

Course Objectives
1. Provide a comprehensive understanding of simulation-based and
formal verification methodologies in digital system design.
2. Equip students with analytical skills to evaluate and apply simulation
tools for verification.
3. Build a solid foundation in formal verification techniques including
model checking and theorem proving.
4. Develop advanced verification strategies like constrained-random
testing and assertion-based approaches.
5. Study industrial practices and real-world case studies to connect
theoretical knowledge with practical design scenarios.

Course Learning Outcomes (CLOs)


After successful completion of the course, students will be able to:
 CLO1: Explain different verification methodologies and distinguish
between simulation-based and formal techniques.
 CLO2: Demonstrate proficiency in using simulation tools to identify
and rectify functional design issues.
 CLO3: Apply formal verification concepts such as model checking and
theorem proving to digital systems.
 CLO4: Utilize advanced verification strategies, including constrained-
random and assertion-based techniques.
 CLO5: Analyze real-world case studies and verification challenges in
digital design.

Syllabus Structure (No Lab Component)


Unit I: Introduction to Verification Methodologies (7 Hours)
 Role of verification in VLSI and SoC design
 Verification process and planning
 Comparison: Simulation vs. Formal methods
 Functional correctness and design validation
 Textbook Reference:
o Perry: Ch. 1–2
o Birtwistle: Ch. 1
Unit II: Simulation-Based Verification Techniques (7 Hours)
 Simulation flow and architecture
 Testbench architecture and stimulus generation
 Debugging and waveform analysis
 Coverage types: code, branch, toggle, FSM
 Textbook Reference:
o Perry: Ch. 3–4
o Seligman: Ch. 2
Unit III: Formal Verification Principles (7 Hours)
 Introduction to property specification languages (PSL, SVA)
 Temporal logic foundations
 Model checking basics: BDDs, SAT/SMT
 Theorem proving techniques
 Textbook Reference:
o Kropf: Ch. 2, 4
o Seligman: Ch. 3
Unit IV: Advanced Verification Strategies (7 Hours)
 Constrained-Random Verification (CRV)
 SystemVerilog randomization
 Assertion-Based Verification (ABV)
 Coverage-Driven Verification (CDV)
 Textbook Reference:
o Seligman: Ch. 5–6
o Birtwistle: Ch. 4–5
Unit V: Industry Tools and Real-World Applications (7 Hours)
 Overview of verification frameworks (UVM conceptually)
 Case studies: Bus protocols, FIFO, Memory controller
 Best practices and challenges in industrial verification
 Preparing verification plans and reports
 Textbook Reference:
o Perry: Ch. 6–8
o Seligman: Ch. 7–8

Textbooks
1. Douglas Perry, Applied Formal Verification, McGraw Hill, 2005.
2. Erik Seligman, Formal Verification, Elsevier, 2023.
Reference Books
1. Thomas Kropf, Introduction to Formal Hardware Verification, Springer,
2013.
2. Tool documentation and research publications (for advanced reading).

You might also like