WSystem Verilog:
Course Learning objectives
1. Learn the important concepts in SOC/ASIC/VLSI design verificationflow
2. Be ready and qualified for a Verification job in semiconductorindustry
3. Be able to code, simulate and verify SystemVerilogTestbenches
4. Learn the System Verilog language for Functional Verificationusage
Content
Unit-I (8 hours)
Data types: Built-in data types, Fixed-Size and Dynamic arrays, Queues, Associated
arrays, Linked list, Enumerated Data types, Constants, Strings, Nettypes
.
Unit-II (8 hours)
Procedural statements and routines: Tasks, Functions and Void functions, Routine
arguments, Local data storage and Time values.
Unit-III (7 hours)
Test Bench and Design, Interface construct, Stimulus timing, Top-Level scope, Module
interactions, System verilog assertions, the FOUR PORT ATM Router, directed test for the
LC3 fetchblock.
Unit-IV (8 hours)
OOP: class, objects, Static and Global Variables, Class routines, Public vs Local and
Building test bench, inheritance, factory patterns, type casting and virtual methods, copying
an object, callbacks.
Unit-V (7 hours)
Threads and inter process communication: working with threads, disabling threads, inter
process communication, events, semaphores, mail boxes, building a test bench with threads
andITC.
Unit-VI (7hours)
Virtual interfaces with ATM router, connecting to multiple design configurations,
procedural code in an interface.
Introduction to Verification, Verification Plan, Directed testing, Functional coverage,
Layered Test bench, Maximum code reuse.
Learning resources
Text book/Reference books
1. , Springer Publications 3rdedition.
Web resources
1.
URL: https://www.udemy.com/soc-verification-systemverilog/
Assessment Method:
Assessment Weeklytests Monthly tests End Semester Test Total
Tool (Insemester) (In semester)
Weightage (%) 10% 30% 60% 100%
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