A report on
Layout and Schematic Design of a
a 4-bit XOR gate using CMOS logic
By
Ritvik Rao 2020A3PS1232P
Saswat Pattnayak 2020A3PS0459P
Saurjyesh Nayak 2020A3PS1537P
Submitted in partial fulfillment of the course
EEE F313/ INSTRF313 – Analog & Digital VLSI Design
Under the Guidance of
Prof. Anu Gupta
EEE Department, BITS Pilani, Pilani Campus
September-October 2022
The Task:
W/L values
1.1 W/L values
Component W/L for NMOS W/L for PMOS
For CMOS (W/L) N : 3 (W/L) P : 6
Schematic Diagram
FULL SCHEMATIC
Layout Design
LAYOUT MAIN
1) Final Results
● DRC Check: the layout passed the DRC test on microwind software which
can also be seen in the full layout screenshot.
● LVS Check: this step was not mandatory but was done as a check using
microwind 3.8
Schematic Simulation
● Layout Simulation
● Few Results
Parameter Value
Power Dissipated: (visible in the layout simulation 65.09 uW
graph)
Average Propagation Delay: (visible in the layout
simulation graph)
● tpLH (Time taken by the output to rise from its ● 79 ps
least value to 50% of its maximumvalue and
50% value of input)
● tpHL(Time taken by the output to fall from its ● 86ps
peak value to 50% of its maximum value and
50% value of input)
● T = (tpHL+tpLH)/2 ● 165ps /
Area:
● Width ● 17.54µm
● Height ● 59.05µm
● Area ● 1035.737
µm^2
supporting screenshot
2) Verilog Assignment
6.1. Verilog Code
7 module counter(Q1,Q2,Q3,Q1bar,Q2bar,Q3bar,reset,clk);
8 input reset,clk;
9 output Q1,Q2,Q3,Q1bar,Q2bar,Q3bar;
10 wire Q2,Q3,Q3bar;
11 wire clk,reset;
12 assign Q3bar=~Q3;
13
14 wire J1,K1,J2,K3;
15 assign J1=Q2&Q3;
16 assign K1=Q2|Q3bar;
17 assign J2=Q3;
18 assign K3=Q3bar;
19
20 jk_ff A(J1,K1,reset,clk,Q1,Q1bar);
21 jk_ff B(J2,1'b1,reset,clk,Q2,Q2bar);
22 jk_ff C(1'b1,K3,reset,clk,Q3,Q3bar);
23 endmodule
24
25 module jk_ff(j,k,reset,CLK,Q,Q_bar);
26 input j,k,CLK,reset;
27 output Q,Q_bar;
28 reg Q;
29
30 assign Q_bar= ~Q;
31
32 always@(posedge CLK or posedge reset)
33 begin
34 if (reset==1'b1) begin
35 Q<=1'b0;
36 end
37 else begin
38 case({j,k})
39 {1'b0,1'b0}:begin
40 Q<=Q;
41 end
42 {1'b0,1'b1}:begin
43 Q<=1'b0;
44 end
45 {1'b1,1'b0}:begin
46 Q<=1'b1;
47 end
48 {1'b1,1'b1}:begin
49 Q<=~Q;
50 end
51 endcase
52 end
53 end
54 endmodule
55
Test Bench
`timescale 1ns/1ns
`include "syn_counter.v"
module syn_counter_tb;
reg reset=0,clk=0;
wire Q1,Q2,Q3,Q1bar,Q2bar,Q3bar;
counter uut(Q1,Q2,Q3,Q1bar,Q2bar,Q3bar,reset,clk);
always begin
clk=~clk;
#5;
end
initial begin
$dumpfile("syn_counter_tb.vcd");
$dumpvars(0,syn_counter_tb);
reset=1;#5;reset=0;#5
#50;
$finish;
end
endmodule
55.1. Verilog Simulation Result
3) References
● Rabaey Jan M., Chandrakasan Antha and Nikolic Borivoje, “Digital
Integrated Circuits”, Pearson Education Mcgraw Hill
● http://referencedesigner.com/tutorials/verilog
