Module VLSI Design

Module-05 (part 2)
Design of Testable Sequential Circuits

TOPICS
1. Controllability and Observability
2. Adhoc Design Rules
3. Diagnosable Sequential Circuits
4. Scan Path Technique
5. LSSD
6. Random Access Scan
7. Partial Scan

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Module-05 (part 2)
Design of Testable Sequential Circuits

5.1 Controllability and Observability

● There are two key concepts in designing for testability: controllability and
observability. Controllability refers to the ability to apply test patterns to the inputs of
a subcircuit via the primary inputs of the circuit. For example, in Fig. 5.1(a) if the
output of the equality checker circuit is always in the state of equal, it is not possible to
test whether the equality checker is operating correctly or not. If a control gate is
added to the circuit (Fig. 5.1(b)), the input of the equality checker and hence, the
operation of the circuit can be controlled. Therefore, to enhance the controllability of a
circuit, the state that cannot be controlled from its primary inputs has to be reduced.

Figure 5.1 Controllability

● Observability refers to the ability to observe the response of a subcircuit via the
primary outputs of the circuit or at some other output points. For example, in Fig. 5.2
the outputs of all three AND gates are connected to the inputs of the OR gate. A
stuck- at-0 fault at the output of the AND gate 3 is not detectable because the effect of
the fault is masked and cannot be observed at the primary output. To enhance the
observability, we must observe the output of the gate Separately as shown.

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Figure 5.2 Observability

● In general, the controllability/observability of a circuit can be enhanced by

incorporating some control gates and input lines (controllability), and by adding some
output lines (observability).

5.2 Ad Hoc Design Rules for Improving Testability

Ad hoc rules are used to improve testability of specific circuits. One of the simplest ways of
achieving this is to incorporate additional control and observation points in a circuit. For
example, the fault o stuck-at-1 in the circuit of Fig. 5,3(a)is undetectable at the circuit output.
The addition of an extra-output line in the circuit makes the fault detectable (Fig, 5.3(b)).

The usefulness of inserting a control point can be understood from the circuit shown in Fig.
5.4(a). The output of the NOR gate is always 0; therefore, it is not possible to determine
whether the gate is functioning correctly or not. If a control point is added to the circuit as
shown in Fig. 5.4(b), the NOR gate can be easily tested for single stuck-at fault.

Another way of improving testability is to insert; multiplexers to increase the number of

internal points that can be controlled or observed from the external pins. For example, in the
circuit of Fig. 5.5(a) the fault a stuck-at-0 is undetectable at the primary output Z. By
incorporating a multiplexer as shown in Fig. 5.5(b), input combination 010 can be applied to
detect the fault via the multiplexer output.

A different way of achieving access to internal points is to use tristate drivers as shown in Fig.
5.6. A test mode signal could be used to put the driver into the high impedance state. In this
mode, the internal point could be used as a control point. When the driver is activated, the
internal point becomes a test point.

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Another approach to improve, testability is to permit access to a subset of the logic as shown
in Fig. 5.7 [5.1,5.2]. Module 8 is physically embedded between the two modules A and C. A
set of gates G and H is inserted into each of the inputs and outputs, respectively, of module B.
In normal operation, the test control signal is such that modules A, B, and C are connected
and the complete network performs its desired function. In the test mode, the test control
input is changed;

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module B is connected to the primary inputs and outputs of the board. In this mode, the
control signal also causes the Outputs of module C to assume a high impedance state, and
hence C does not interfere with the test results generated by B, Basically, this approach is
similar to the previously discussed technique of using multiplexers to improve testability.

The test mode signals required by the 4 hardware such as multiplexers, tristate drivers, and so
forth cannot always be applied via the edge pins, because there may not be enough of them.
To overcome this problem, a “test state register” may be incorporated in the design. This
could in fact be a shift register that is loaded and controlled by just a few signals, The various
testability hardware in the circuit can then be controlled by the parallel outputs of the shift
register.

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Frequently, flip-flops, counter, shift registers, and other memory elements assume
unpredictable states when power is applied, and they must be set to known states before
testing can begin, Ideally, all memory elements should be reset from the external pins of the
circuit, whereas in some cases additional logic may be required (Fig, 5.8), With complex
circuits it may be desirable to set memory elements in several known states, This not only
allows independent initialization, it also simplifies generation of certain internal states
required to test the board adequately.

A long counter chain presents another practical test problem. For example, the counter chain
shown in Fig. 5.9 requires thousands of clock pulses to go through all the states, One way to
avoid this problem is to break up the long chain into smaller ones by using a multiplexer.
When the control input c of the multiplexer is al logic 0, the counter functions normally,
When c is at logic 1, the counter is partitioned into two smaller counters.

A feedback loop is difficult to test, because it hides the source of a fault. The Source can be
located by breaking the loop physically and bringing both lines to external pins that can be
short-circuited for normal operation. When not short-circuited, the separated lines provide a
control point and a test point. An alternative way of breaking a feedback loop, rather than
using more costly test/control points, is to add to the feedback path a gate that can be
interrupted by a signal from the tester (Fig. 5.10).

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5.3 Design of Diagnosable Sequential Circuits

The use of checking experiments to determine whether a sequential circuit represents the
behavior specified by its state table yields good results provided that

1. The circuit is reduced and strongly connected.

2. The circuit has a distinguishing sequence.
3. The actual circuit has no more states than the correctly operating circuit.

For circuits that do not have any distinguishing sequences, the checking experiments are very
long and consequently hard to apply in any practical situation. One approach to this problem
is to modify a given circuit by adding extra outputs so that the modified circuit has a
distinguishing sequence. A sequential circuit which possesses one or more distinguishing
sequences is said to be diagnosable.
A procedure for modifying a sequential circuit to possess a distinguishing
sequence if it does not already do so has been presented by Kohavi and Lavelle [5.3]. Let us
explain the procedure by considering the state table of Circuit M shown in Fig. 5.11(a);
Circuit M does not have a distinguishing sequence. The procedure begins with the
construction of the testing table of the circuit; the testing table for Circuit M is shown in Fig.
5.11(b). The column headings consist of all input/output combinations, where the pair X/Z
corresponds to input X and output Z. The entries of the table are the ‘‘next state.’’ For
example, from state A under input the circuit goes to state 8 with an output of 0. This is
denoted by entering B in column 1/0 and a dash (—) in column 1/1. In a similar manner, the
next states of A are entered in the upper half of the table.

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The lower half of the table is derived in a straightforward manner from the upper half. If the
entries in rows Si, and Sj column Xk/Z1 of the upper half are Sp and Sq respectively, the
entry in row SiSj, column Xk/Z1, of the lower half, is SrSq. For example, because the entries
in rows A and B, column 1/0, B and C, respectively, the corresponding entry in row AB,
column 1/0, is BC and so on. If for a pair Si and Sj either one or both corresponding entries in
some column Xk/Z1 are dashes, the corresponding entry in row SiSj, column Xk/Z1, is a
dash. For example, the entry in row BD, column 0/0, is a dash, because the, entry in row D,
column 0/0, is a dash. Whenever an entry in the testing table consists of a repeated state (e.g.,
AA in row AB), that entry is circled. A circle around AA implies that both states A and B are
merged under input 0 into state A and hence are indistinguishable by any experiment Starting
with an input 0.

The next step of the procedure is to form the testing graph of the circuit. The testing graph is
a directed graph with each node corresponding to a row in the lower half of the testing table.
A directed edge labeled Xk/Z1 is drawn from node SiSj to node SpSq, where p not equal q, if
there exists an entry in row SiSj column Xk/Z1 of the testing table. Figure 5.12 shows the
testing graph for Circuit M.
A circuit is definitely diagnosable if and only if its testing graph has no loops and
there are no repeated states, that is, no circled entries in its testing table. Circuit M is
therefore not definitely diagnosable, because AA exists in its testing table and its testing
graph contains tow loops: AB-BC-CD-AD-AB and AC-BD-AC.

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To make the circuit definitely diagnosable, additional output variables are required to
eliminate all repeated entries from its testing table and to open all loops in its testing graph.
The maximum number of extra output terminals re- quired to make a 2^k state circuit
definitely diagnosable is k; however, the addition of one output terminal is sufficient to make
Circuit M definitely diagnosable. The modified state table of Circuit M is shown in Fig. 5.13;
this version possesses the distinguishing sequences 0 and 11. The checking experiment for a
definitely diagnosable circuit can be derived as follows:
1. Apply a homing sequence, followed by a transfer sequence (Si, So) is necessary, to bring
the circuit into an initial state So.
2. Choose a distinguishing sequence so that it is the shorter one of the sequences of all 0s or
all 1s.
3. Apply the distinguishing sequence followed by a 1. (If the all-0s sequence has been
chosen, apply a 0 instead of a 1.)
4. If S01, that is, the 1-successor of S0, is different from S0, apply another 1 to check the
transition from S01, under a 1 input. Similarly, if S011 not equal to S01 and S011 not equal
to S0, apply another 1.Continue to apply 1 inputs in the same manner as long as new
transitions are c

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5. When an additional 1 input does not yield any new transition, apply an input of 0 followed
by the distinguishing sequence.
6. Apply inputs of 1s as long as new transitions can be checked. Repeat steps 5 and 6 when
no new transitions can be checked.
7. When steps 5 and 6 do not yield any new transitions and the circuit, which is in state Si, is
not yet completely checked, apply the transfer sequence T(Si, Sk), where Sk is a state the
transition of which has not been checked, such that T(Si, Sk) passes through checked
transitions only,
8. Repeat the last three steps until all transitions have been checked.

The checking experiment for the definitely diagnosable circuit of Fig. 5.13 has been designed
using the foregoing procedure. It required only 23 symbols and is illustrated here:

5.4 The Scan-Path Technique for Testable Sequential Circuit Design

The testing of sequential circuits is complicated because of the difficulties in setting and
checking the states of the memory elements. These problems can be overcome by modifying
the design of a general sequential circuit so that it will have the following two properties
[5.4]:
1. The circuit can easily be set to any desired internal state.
2. It is easy to find a sequence of input patterns such that the resulting out- put sequence
will indicate the internal state of the circuit. In other words: the circuit has a distinguishing
sequence.

The basic idea is to add an extra input c to the memory excitation logic in order to control the
mode of a circuit, When c = 0, the circuit operates in its normal mode, but when c = 1, the
circuit enters into a mode in which the elements are connected together to form a shift
register. This facility is incorporated by inserting a double-throw switch in each input lead of
every memory element.

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All these switches are grouped together, and the circuit can operate either in its normal mode
or shift register mode. Figure 5.14 shows a sequential circuit using D flip-flops; the circuit is
modified as shown in Fig. 5.15, Each of the double throw switches may be realized as in Fig
5.16.

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In the shift register mode, the first flip-flop can be set directly from the primary inputs
(scan-in inputs) and the output of the last flip-flop can be directly monitored on the primary
output (scan-out output). This means that the circuit can be set to any desired state via the
scan- in inputs, and that the internal state can be determined via the scan-out output. The
procedure for testing the circuit is as follows:

1 Set c = 1 to switch the circuit to shift register mode.

2. Check operation as a shift register by using scan-in inputs, scan-out out-
put, and the clock.
3. Set the initial state of the shift register.
4. Set c = 0 to return to normal mode.
5. Apply test input pattern to the combinational logic.
6. Set c = 1 to return to shift register mode.
7. Shift out the final state while setting the Starting state for the next test.
8. Go to step 4.

The main advantage of the scan-path approach is that a sequential circuit can be
transformed into a combinational circuit, thus making test generation for the circuit relatively
easy. Besides, very few extra gates or pins are required for this transformation.

Another implementation of the scan-path technique has been described by Funatsu et al.
[5.5]. The basic memory element used in this approach is known as a raceless D-type flip-
flop with scan path [5.6] Figure 5.17(a) shows such a memory element, which consists of two
latches L/ and L2. The two clock signals Cl and C2 operate exclusively, During normal
operation, C2 remains at logic 1 and C/ is set to logic 0 for sufficient time to latch up the data
at the data input D1. The output of L1 is latched into L2 when C1 returns to logic 1.
Scan-in operation is realized by clocking the test input value at D2 into the latch L1
by setting C2 to logic 0. The output of the L1 latch is clocked into L2 when C2 returns to
logic 1.

The configuration of the scan-path approach used at logic card level is shown in Fig.
5.17(b). All the flip-flops on a logic card are connected as a shift register, such that for each
card there is one scan path. In addition, there is provision for selecting a specified card in a
subsystem with many cards by X-Y address signals (Fig. 5.17(b)). If a card is not selected, its
output is blocked; thus, a number of card outputs in a subsystem can be put together with
only a particular card having control of the test output for that subsystem. The Nippon
Electric Company in Japan has adopted this version of the scan path approach to improve the
testability of their FLT-700 processor system.

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5.5 Level-Sensitive Scan Design (LSSD)

One of the best known and the most widely practiced methods for synthesizing testable
sequential circuits is the IBM LSSD (level-sensitive scan design).

5.5.1 CLOCKED HAZARD-FREE LATCHES

In LSSD, all internal Storage is implemented in hazard-free polarity-hold latch. The

polarity-hold latch has two input signals as shown in Fig. 5.18(a). The latch cannot change
state if C = 0. If C is set to 1, the internal stateof the latch takes the value of the excitation
input D. A flow table for this sequential network, along with an excitation table and a logic
implementation shown in Fig. 5.18.

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The clock signal C will normally occur (change from 0 to 1) after the data signal D has
become stable at either a 1 or a 0. The output of the latch is set to the new value of the data
signal at the time the clock signal occurs. The correct changing of the latch does not depend
on the rise or fall time of the clock signal, only on the clock signal being 1 for a period equal
to or greater than the time Required for the data signal to propagate through the latch and
stabilize. A shift register latch (SRL) can be formed by adding a clocked input to the polarity-
hold latch L1 and including a second latch L2 to act as intermediate storage during shifting
(Fig. 5.19). As long as the clock signals A and B are both 0, the L1 latch operates exactly like
a polarity-hold latch. Terminal 1 is the scan-in input for the shift register latch and +L2 is the
output. The logic implementation of the SRL is shown in Fig. 5.20.

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When the latch is operating as a shift register, data from the preceding Stage are gated
into the polarity-hold switch via l, through a change of the clock A from 0 to 1. After A has
changed back to 0, clock B gates the data in the latch L1 into the output latch L2 Clearly, A
and B can never both be 1 at the same time if the shift register latch is to operate properly.
The SRLs can be interconnected to form a shift register as shown in Fig. 5.21. The
input l and the output +L2 are strung together in a loop, and the clocks A and B are connected
in parallel.

5.5.2 LSSD DESIGN RULES

A specific set of design rules has been defined to provide level-sensitive logic subsystems
with a scannable design that would aid testing [5.8).

Rule 1: All intemal storage is implemented in hazard-free polarity-hold latches.

Rule 2: The latches are controlled by two or more nonoverlapping clocks such that
(a) Two latches, where one feeds the other, cannot have the same clock (see Fig.
5.22(a)).

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Rule 3: It must be possible to identify a set of clock primary inputs from which the clock
inputs to SRLs are controlled either through simple powering trees or through logic that is
gated by SRLs and/or non-clock primary inputs (see Fig. 5.23). Given this structure, the
following rules must hold:

(a) All clock inputs to all SRLs must be at their OFF states when all clock primary inputs
are held to their OFF states (bee Fig. 5.23(a)).

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(b) The clock signal that appears at any clock input of any SRL must be controllable
from one or more clock primary inputs, such that it is possible to set the clock input of the
SRL to an ON state by turning any one of the corresponding clock primary inputs to its ON
state and also setting the required gating condition from SRLs and/or non-clock primary
inputs.

(c) No clock can be ANDed with either the true value or the complement value of another
clock (see Fig. 5.23(b)).

Rule 4: Clock primary inputs may not feed the data inputs to latches either directly or
through combinational logic, but they may only feed the clock input the latches or the
primary outputs. A sequential logic network designed in accordance with Rules 1-4 would be
level- sensitive. To simplify testing and minimize the primary inputs and outputs, it must also
be possible to shift data into and out of the latches in the system. Therefore, two more rules
must
be observed:

Rule 5: All SRLs must be interconnected into one or more shift registers, each of which has
an input, an output, and clocks available at the terminals of the module.

Rule 6: There must exist some primary input sensitizing condition (referred to as the scan
state) such that
(a) Each SRL or scan-out primary output is a function of only the preceding SRL or scan-
in primary input in its shift register during the shifting operation.
(b) All clocks except the shift clocks are held OFF at the SRL inputs.
(c) Any shift clock to an SRL may be turned ON and OFF by changing the
corresponding clock primary input for each clock.

A sequential logic network that is level-sensitive and also has the scan Capability as per
Rules 1 to 6 is called a level-sensitive scan design (LSSD). Figure 5.24(a) depicts a general
structure for an LSSD system in which all system Output are taken from the L2 latch; hence,
it is called a double-latch design. In the double-latch configuration, each SRL operates in a
master-slave mode. Data transfer occurs under system clock and scan clock B during normal
operation, and under scan clock A and scan clock B during scan-path operation. Both latches
are therefore required during system operation. In the single-latch configuration, the
combinational logic is partitioned into two disjoint sets, Comb1 and Comb2 (Fig. 5.24(b)).
The system clocks used for SRLs in. Comb1 and Comb2 are denoted by Clock1 and Clock2,
respectively; they are nonoverlapping.
The outputs of the SRLs in Comb1 are fed back as secondary variable inputs to Comb2, and
vice versa. This configuration uses this output of latch L1 as the system output;

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the £2

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The L2 latch is used only for shifting. In other words, the L2 latches are redundant and
represent an overhead for testability. However, the basic SRL design can be modified to
reduce the overhead. The modified latch galled the L1/L2* SRL is shown in Fig. 5.25. The
main difference between the basic SRL and the L1/L2* SRL is that L2* has an alternative
system data input D2 clocked in by a separate system clock C2. The original data input D in
Fig. 5.19 is also available and is now identified as D1 in Fig. 5.25. D1 is clocked in by the
original system clock, which is now called C1. Clock signals C1 and C2 are nonoverlapping.
The single-latch configuration of Fig. 5.25(b) can now be modified to the configuration of
Fig. 5.26, in which the system output can be taken from either the L1 output or the L2*
output. In other words, both L1 and L2* are utilized, which means fewer latches are required
in the system. As a result, there is a significant reduction in the silicon cost when L1/L2*
SRLs are used to implement the LSSD. Although both latches in L1/L2* SRLs can be used
for system functions, it is absolutely essential, as in conventional LSSD, that both L1 and L2*
outputs do not feed the same combinational logic.

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5.5.3 ADVANTAGES OF THE LSSD TECHNIQUE

The LSSD approach is very similar to the scan-path approach used by the NEC, except that it
has the level-sensitive attribute and requires two separate clocks to operate latches LJ and L2.
The use of LSSD alleviates the testing problems in the following ways:

1. The correct operation of the logic network is independent of a.c. characteristics such as
clock edge rise time and fall time.
2. Network is combinational in nature as far as test generation and testing is concerned.
3. The elimination of all hazards and races greatly simplifies both test gen eration and
fault simulation.

Any desired pattern of 1s and 0s can be shifted into the polarity-hold latches inputs to the
combinational network. For example, the combinational network of Fig. 5.24(a) is tested by
shifting part of each required pattern into the SRLs, with the remainder applied through the
primary inputs. Then the system clock is turned on for one cycle, the test pattern is
propagated through the combinational logic, and the result of the test is captured in the
register and at the primary outputs. The result of the test captured in the register is then
scanned out and compared with the expected response. The shift register must also be tested,
and accomplished by shifting a short sequence of 1s and 0s through the shifted latches.

5.6 Random Access Scan Technique

The design methods discussed in Secs. 5.4 and 5.5 use sequential access scan-in techniques to
improve testability; that is, all flip-flops are connected in testing to form a shift register or
registers. In an alternative approach, known as random access scan each flip-flop in a logic

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network is selected in an address for control and observation of its state [5.11]. The basic
memory element in a random access scan-in/scan-out network is an addressable latch. The
circuit diagram of an addressable latch is shown in Fig. 5.27. A latch Y address signals, the
state of which can then be controlled and scan-in/scan-out lines. When a latch is selected and
its scan 0 to 1, the scan data input is transferred through the network to output, where the
inverted value of the scan data can be observed. DATA line is transferred to the latch output
Q during the negative transition (1 to 0) of the clock. The scan data out lines from all latches
are produce the chip scan-out signal, the scan-out line of a latch remains at logic 1 unless the
latch is selected by the X-Y signals.
A different type of addressable latch—the set/reset type—is shown in Fig. 5.28. the
“clear” signal clears the latch during its negative transition. Prior to scan-in operation, all
latches are cleared. Then, a latch is addressed by the X-Y lines and the preset signal is
applied to set the latch state.

The basic model of a sequential circuit with random access scan-in/scan-out network is
shown in Fig. 5.29. The X- and Y-address decoders are used to access an addressable latch—
like a cell in random access memory. A tree of AND gates is used to combine all scan-out
signals. Clear input of all latches are tied together to form a master reset signal. Preset inputs
of all latches receive the same scan- in signal gated by the scan clock; however, only the latch
accessed by the X-Y addresses is affected
.

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The test procedure of a network with random access scan-in/scan-out network is us follows:

1. Set test input to all test points.

2. Apply the master reset signal to initialize all memory elements.
3. Set scan-in address and data, and then apply the scan clock.
4. Repeat step 3 until all internal test inputs are scanned in.
5. Clock once for normal operation.
6. Check states of the output points.
7. Read the scan-out states of all memory elements by applying appropriate X—Y signals.

The random access scan-in/scan-out technique has several advantages:

1. The observability and controllability of all system latches are allowed.

2. Any point in a combinational network can be observed with one additional gate and
one address per observation point.
3. A memory array in a logic network can be tested through a scan-in/scan- out network.
The scan address inputs are applied directly to the memory array. The data input and the
write- enable input of the array receive the scan data and the scan clock, respectively. The
output of the memory array is ANDed into the scan-out tree to be observed.

The technique has also a few disadvantages:

1. Extra logic in the form of two address gates for each memory element, plus the address
decoders and output AND trees, result in 3—4 gates overhead per memory element.
2. Scan control, data, and address pins add up to 10-20 extra pins. By using a serially
loadable address counter, the number of pins can be reduced to around 6.
3. Some constraints are imposed on the logic design, such as the exclusion of asynchronous
latch operation.

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5.7 Partial Scan

In full scan, all flip-flops in a circuit are connected into one or more shift registers: thus, the
states of a circuit can be controlled and observed via the primary inputs and outputs,
respectively. In partial scan, only a subset of the circuit flip-flops are included in the scan
chain in order to reduce the overhead associated with full scan design [5.12]. Figure 5.30
shows a structure of partial scan design. This structure has two separate clocks: a system
clock and a scan clock. The scan clock controls only the scan flip-flops. Note that the scan
clock is derived by gating the system clock with the scan-enable signal; no external clock is
necessary. During the normal mode of operation, namely, scan-enable signal at logic 0, both
scan and non-scan flip-flops update their states when the system clock is applied. In the scan
mode operation, only the state of the shift register (constructed from the scan flip-flops) is
shifted one bit with the application of the scan Nip-flop; the non-scan flip-flops do not change
their states.

The disadvantage of two-clock partial scan is that the routing of two separate clocks
with small skews is very difficult to achieve. Also, the use of a separate scan clock docs not
allow the testing of the circuit at its normal Operating speed. Cheng [5.13] proposed a partial
scan scheme, shown in Fig. 5.31, in which the system clock is also used as the scan clock.
Both scan and non-scan flip-flops move to their next states when the system clock is applied.

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A test sequence is derived by shifting data into the scan flip-flops. This data together with
the contents of non-scan flip-flops constitute the Starting state of the test sequence, The other
patterns in the sequence are obtained by single-bit shifting of the contents of scan flip-flops,
which form part of the required circuit states. The remaining bits of the states, that is, the
contents of non-scan flip-flops, are determined by the functional logic. Note that this form of
partial scan scheme allows only a limited methods. Trischler [5.14] has used testability
analysis to show that the fault coverage in a circuit can be significantly increased by
including 15-25% of the flip flops in the partial scan. Agrawal et al. [5.15] have shown that
the fault coverage can be increased to as high as 95% by including less than 65% of the flip-
flops in the partial scan.

5.8 Testable Sequential Circuit Design Using Non-scan Techniques

Full and partial scan techniques improve the controllability and observability of flip-flops in
sequential circuit, and therefore the test generation for such circuits is considerably
simplified. However, a scan-based circuit cannot be tested at its

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IMPORTANT QUESTIONS:

1) Define the terms controllability and observability with an example.

2) With a neat logic diagram, explain clocked hazard free latches used
in LSSD Technique.

3) Explain any two Adhoc design rules for improving testability.

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normal speed, because test data have to be shifted in and out via the scan path.

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