1.

Introduction

In the last lecture we have seen that the major problem in testing (and ATPG) of sequential
circuits is difficulty in controlling secondary inputs (i.e., outputs of flip-flops)
flip flops) and difficulty in
observing secondary outputs (i.e., inputs of flip-flops).
flops). In this lecture we will discuss various
techniques to make the flip-flops controllable and observable, which convert a sequential
circuit into virtual combinational one. Following that ATPG for combinational circuits would
suffice for sequential
ntial circuits. However, for achieving this, additional circuitry, called design
for test (DFT), will be put on-chip, which would add to extra area overhead.

In the next section we will explore different schemes to control and observe the flip-flops.
flip

2. Controllability
ontrollability and observability of flip-flops
flip

2.1 Set and reset lines

One of the simplest way to directly control flip-flops

flip is through set-reset
reset lines. Set-reset
Set lines
can directly make the output of a flip-flop
flip flop to be 1/0 without any input and clock pulse.
pul AD
flip-flop with set-reset
reset lines is shown in Figure 1 and its functionality is shown in Table 1.

Figure 1. D-Flip-flop
D with set and reset

Table 1. Truth table for D flip-flop

flip with set-reset lines

Input (D) Output (Q) set reset clock

Don't care 1 1 0 Don't care
Don't care 0 0 1 Don't care
Don't care Illegal 1 1 Don't care
1 1 0 0 Clock edge
0 0 0 0 Clock edge

From the truth table it may be observed that set (reset) lines makes the output 1(0)
irrespective of input D and clock pulse. However, both the set and reset lines cannot be
made high simultaneously. Also, when the D-flip-flop
D flop functions normally, both set and reset
lines are kept low.

Now we will see how use of this type of flip-flop

flip flop helps in testing the circuit given in exercise
of last lecture (Lecture 1, module 12). The circuit with a s-a-1
s 1 fault in the primary input line
is shown in Figure 2 (a). Also, the flip-flop
flip has set/reset lines. By D-algorithm,
algorithm, a test pattern
would be: primary input =0, secondary input (other input of XOR gate)=0 =0 and fault effect
at primary output = D. So in Step-1
Step (Figure 2 (b)), set =1 and reset =0 (and and primary
input =X); this makes output of flip-flop
flip flop (i.e., secondary input) to be 1. In Step-2
Step (Figure 2
(c)), set =0, reset =0 and primary input =0; this sensitizes fault location as D and its effect
propagates to the input of the flip-flop as D . Also a positive clock pulse is applied which
transfers D to output of the flip-flop (primary output). These two steps complete ATPG (and
testing) of the fault.

So it may be observed that the fault which was un-testable by time frame expansion method
becomes testable using set/reset flip-flop. Further, one pattern is required to set/reset the
flip-flops and another pattern (at primary inputs) is required to sensitize and propagate the
fault effect to a primary output. So, unlike time frame expansion method where dseq+1 test
patterns are required ( dseqpatterns to initialize the flip-flops and one pattern to
sensitize/propagate fault effects), in case of set/reset flip-flops only two patters are required
(one to set or reset the flops and one to sensitize/propagate fault effects). This saving in
number of test patterns (i.e., test time) is illustrated in the circuit example of Figure 10 of
the last lecture. The circuit (Figure 10 of Lecture 1, module 12) with set/reset flip flops is
shown in Figure 3(a).
Figure 2. Testing using set/reset flip-flops for a cyclic circuit
 Figure 3. Testing using set/reset flip-flops: illustration of saving in test patterns

As discussed in the last lecture, three patterns were required to test the s-a-0 fault at net j:
(i) a =X, b =X, c =1 and clock pulse (ii) a =X, b =1, c =1 and clock pulse and
(iii) a =1, b =1, c =X. Also it is to be noted that dseq=2, for the circuit.

Now, by using the set/reset flip-flops, we will see only two patterns are required to test the
fault. By ATPG using D-algorithm, nets d and i are to be 1 for testing the fault. So both the
flip-flops are set by the pattern: a =X, b =X, c =X, set (F1)=1, reset (F1)=0, set (F2)=1
and reset (F2)=0; this is shown in Figure 3(b). Finally,
pattern a =1, b =1, c =X, set (F1)=0, reset (F1)=0, set (F2)=0 and reset (F2)=0 is applied
to sensitize and propagate the effect of the fault to primary output; this is shown in Figure
3(c).
So, only two patterns can test the fault. However the most important point is Irrespective
of the value of dseq, only two patterns are required to test a sequential circuit with
set/reset flip-flops. The gain can be easily understood because any practical
pract circuit has
more than thousands of flip-flops.
flip flops. On the other hand, there is a big problem with the
scheme that makes it impractical to be applied in a practical system. An input output block
diagram of the circuit of Figure 3 is shown in Figure 4. It may
may be noted that it has 9 I/O pins
(3 primary inputs + 1 primary output +2 x nffs set-reset lines, where nffs is the number of
flip-flops
flops and a clock). The largest number of I/O pins supported in most complicated
packages is about 1024. So, for a circuit with
w thousands of flip-flops,
flops, this approach requires
a package of thousands of I/O pins (for the 2 x nffs factor) with makes it impractical.

Figure 4. Input output block diagram of the circuit shown in Figure 3.

2.2.Set
Set and reset by shift register

In the last sub-section

section we saw that flip-flops
flip flops with set/reset capability can ease the testing
and ATPG problem for sequential circuits. However, the main problem is the huge number of
I/O lines that gets added to the chip. To avoid this issue of high I/Os, anotheran technique
called set and reset by shift register is used which uses a shift register and loads itself with
the pattern required for setting the flip-flops.
flip flops. Now the set and reset lines of the flip-flops
flip of
the circuit (under test) are connected with the outputs of the flip-flops
flops of the shift resister.
The shift register has an input line and a separate clock (for shifting data) and an output
line. So in this case only three extra I/O lines are required. ATPG and testing for the circuit
shown in Figure e 3, using shift register is illustrated in Figure 5.

As there are two flip-flops

flops in the circuit under test, there are four flip-flops
flip in the shift
register. Now, set and reset lines of F1 (flip-flop)
(flip flop) of the circuit under test are connected to
output of SR1 and SR2 (flip-flops
flops of register), respectively. Similarly, set and reset lines of
F2 are connected to output of SR3 and SR4, respectively. As already discussed, testing the
fault (s-a-0 at j ) requires the two flip-flops
flip flops of the circuit to be set to 1. So the pattern
is set (F1)=1, reset (F1)=0, set (F2)=1 and reset (F2)=0, which when mapped to the flip- flip
flops of the shit register is SR1=1,SR2=0,SR3=1 and SR4=0. The pattern 1010 can be
inserted in the shift register using four clock edges of S_clock . Once the shift register is
loaded, the flip-flops F1 and F2 are set; this is shown in Figure 5(a). Now, another pattern
0000 is inserted in the shift register using four clock edges of S_clock; this makes the circuit
under test ready to be operational. Following that input pattern a =1, b =1, c =X is applied
to sensitize and propagate effect of the fault to primary output; this is shown in Figure 5(b).
The block diagram of the circuit (under test) with shift register is shown in Figure 6. So in
addition to original I/Os, three new I/Os get added namely, (i) S_clock , (ii) test in and
(iii) test out .
 Figure 5. Testing using set/reset flip-flops
flip flops and shift register

Figure 6. Input output block diagram of the circuit under test (Figure 5) with shift register

The
he following are the pros and cons of shift register based testing and ATPG.

Pros:

ATPG algorithm does not require time frame expansion approach and flip-flops
flip can be
directly controlled from the register. So ATPG complexity is lower than time frame expansion
exp
approach.

I/O requirements for testing is minimal (only 3)

Cons:

Area overhead of the shift register is high (twice the number of flip-flops
flip flops in the circuit)

Test pattern application time is almost same as in the time frame expansion approach.
approac
Applying bit sequence in the shift register (required for setting/resetting the flip-flops)
flip
takes 2 X nffs pulses of the clock of the register.

In the next section we will discuss another scheme similar to shift resister based testing
called scan chain. In scan chain based technique the flip-flops
flip flops are directly controllable and
I/O requirements are minimal. However, on the other side there is no requirement of the
additional shift register and separate set/reset lines in flip-flops;
flip flops; due to these two
tw points
scan chain based scheme is widely accepted in VLSI testing.

3. Scan Chain based Testing and ATPG for sequential circuits

In the last section we saw that shift register based testing of sequential circuits solved the
problem of a large number of I/Os.
I/Os. However, the major drawback of the scheme is due to
the huge area overhead; twice the number of flip-flops in the circuit under test is required in
the shift register. The concept of Scan chin is motivated from the idea of shift register based
testing, however, alleviates the problem of area overhead [1]. The basic idea in scan chain
is to convert the flip-flops in the circuit under test itself to a shift register, rather than using
a separate one. To elaborate, the circuit under test has two modes: (i) test (or scan chain)
and (ii) working (or normal). In test mode the flip-flops are decoupled from the circuit and
they are connected in form of a shift register (called scan chain). The input of the first flip-
flop in the scan chain is taken out as a special input test pin called Scan in and the output
of the last flip-flop in the scan chain is taken out as a special output test pin called Scan
out. Now all the flip-flops are set as required by shifting bit values in the scan chain. Once
the flip-flops are set they are removed from the scan chain and connected back to the
circuit. So another advantage of scan chain based testing over shift register based testing is
due to non requirement of set/reset lines. The basic concept of scan chain is shown in
Figure 7.

Figure 7. Scan chain in state flip-flop block

Figure 7 shows the state flip-flops with scan chain in a sequential circuit; other blocks are
not shown for clarity. As discussed, flip-flops with scan-chain take inputs from two parts of
the circuit (i) next state function block (when operating normally) and (ii) from the previous
flip-flop in the chain (when in test mode); the first flip-flop in the scan chain takes input
from a primary input Scan in. So in state flip-flop block with scan chain, all the flip-flops
must have a 2X1 multiplexer. One input is from the next state function block and the other
is from the previous flip-flop in the chain. The control input called mode basically decides
the mode of operation; 1 for scan-chain and 0 for normal operation. Figure 7 shows this
concept for a circuit with three flip-flops. Figure 8 shows a flip-flop used in scan chain
called scan flip-flop and Figure 9 shows the block diagram representation of scan flip-flop.
Figure 10 shows the flip-flops of Figure 7 in scan chain mode and Figure 11 shows the flip-
flops of Figure 7 in normal mode. Figure 12 shows the basic block diagram of a sequential
circuit with scan chain in both normal and test mode.

Figure 10. Flip-flops of Figure 7 in scan chain mode

Figure 11. Flip-flops of Figure 7 in normal mode
 Figure 12.Sequentail circuit with scan chain: normal and test mode

4. ATPG and testing using scan chain in a sequential circuit: An Example

In this section we will discuss ATPG and testing of the sequential circuit discussed in last
lecture (Module 12, Lecture 1, Figure 10), now with scan chain. The circuit with the flip-flops
having scan chain compatibility is shown in Figure 13(a). As discussed about the circuit (in
Module 12, Lecture 1, Figure 10), to test the s-a-0 fault at net j, the signal values at
nets d and i are to be 1. So both the flip-flops are to be set to 1; this was achieved by
making the set input as 1 and reset input as 0 in case of testing using set/reset flip-flops. In
case of scan chain, to set the flip-flops, in the first step mode (M) is made 1. Making M=1,
removes the next state function block from the circuit and the flip-flops are connected in a
chain; this is shown by dotted lines in Figure 13(b). Two 1s are applied in the Scan in input
at two clock pulses which makes d =1 and i =1. Now, the circuit is brought in normal mode
by making M=0. In this stage testing is performed by making a =1, b =1, c =X which
propagates the fault effect to the output; this is shown in Figure 13(c).

Figure 13. ATPG and testing of a sequential circuit (Figure 10, Module 12, Lecture 1) with
scan chain

In the last example we saw how scan chain can be used to set the flip-flops to desired value
for testing. However, D-algorithm is required on the entire circuit (after removing flip-flops)
to find the test pattern. Now we will see another advantage of scan chain, which eliminates
the need for performing ATPG on the whole circuit. One needs to consider input of the
nearest flip-flop from the fault site as an output line and perform ATPG on the sub-circuit
lying in the cone of influence of the output line (i.e., input of the nearest flip-flop). This
concept will be illustrated on a circuit example given in Figure 14.

Figure 14. A sequential circuit with scan chain and s-a-0 fault at d

We will first illustrate the scheme of testing using scan chain where D-algorithm is applied
on entire circuit and scan chain is used only to control the flip-flops; the procedure is shown
in Figure 15. Figure 15 (a) illustrates D-algorithm applied on the full circuit of Figure 14
(after removing the flip-flops) where fault propagation path is taken as d-i-o-p-m-n. D-
algorithm determines that h is to be 1 and g is to be 1; this implies that flip-flop F1 and F3
are to be set while F2 can be set or reset. Further, a =X, b =X, c =0 ,d =1, e =X would
apply the pattern to sensitize and propagate the fault effect. So to make flip-flops F1 and F3
to be 1 and F2 to be X, pattern 1X1 is applied at Scan in input with three clock pulses
keeping M=1; this is shown in Figure 15 (b). Finally, M is made 0 and test
pattern a =X, b =X, c =0 ,d =1, e =X is applied, which propagates fault effect through
primary output n; this is illustrated in Figure 15(c).
Figure 15. Testing using scan chain and fault propagation through circuit output
 Figure 16. Fault sensitization and effect propagation to input of nearest flip-flop
flip (of the
circuit of Figure 14)

As already discussed, even in ATPG for sequential circuits, D-algorithm

D algorithm is performed on the
full circuit with flip-flops
flops removed. In the last example we saw the use of scan chain only to
set/reset the flip-flops.
flops. Now we will see another use of scan chain in propagating the fault
effect. So we need to just bring the fault effect to the input of the nearestneare flip-flop. This in
turn requires ATPG on a sub-circuit
circuit whose output drives the input of the nearest flip-flop.
flip In
other words, ATPG is to be performed on the sub-circuit
sub circuit that lies in the cone of influence of
the nearest flip-flop's
flop's input. Figure 16 illustrates
illu that the nearest flip-flop
flop from the fault site
(s-a-0 at net d, of the circuit of Figure 14) is F2. So fault effect needs to be propagated to
net j (which is input of F2). So, APTG is to be performed on the sub-circuit
sub circuit which lies in the
cone of influence of net j, which includes inputs d,e and AND gate marked gray in Figure 16;
test pattern is d =1, e =1 and fault effect D is propagated to net j . Obviously ATPG
complexity is simplified. Now we will see how scan chain can propagate this fault effect eff out
of the circuit.

The whole testing procedure, when fault is propagated through scan chain (for the circuit of
Figure 16) is illustrated in Figure 17 I and Figure 17 II.
 Figure 17-I. Fault effect propagation through scan chain (Step a and Step b for circuit of
Figure 16)

In this case, as we are considering only a sub-circuit, so only F1 (i.e., net h ) needs to be
made 1; this is shown in Figure 16. This is achieved by making M=1, giving 1 in Scan in
input and a clock pulse; shown in Figure 17-I(a). After that M is made 0 and
pattern d =1, e =X is applied to sensitize the fault and propagate the effect ( D) to net j via
net i ; shown in Figure 17-I(b).
 Figure 17-II. Fault effect propagation through scan chain (Step c and Step d for circuit of
Figure 16)

Now the fault effect is to be brought out by the scan chain. This is achieved in two steps as
shown in Figure 17-II. First, the effect D is loaded into the nearest flip-flop (F2) by applying
a clock pulse keeping M=0; shown in Figure 17-II(a). Following that flip-flops are again
brought into chain mode (by setting M=1) and 1 clock pulse is applied (with Scan in input as
X), which brings the effect out through the Scan out output; shown in Figure 17-II(b).

5. ATPG and testing using partial scan chain in a sequential circuit: An Example

From the discussion in last lecture (Module 12, Lecture 1) we saw that a circuit with
sequential dept
dseq needs dseqclock pulses and patterns to set the flip-flops (to required values) when testing
is done using time frame expansion approach. In case of scan chain if there are nffflip-flops,
then nffclock pulses are required to set/reset the flip-flops. As dseq nff, test time is higher for
scan chain based testing compared to time frame expansion method. Also, multiplexers are
required in case of scan chains while no extra circuitry is required for time frame expansion
method. Only ATPG complexity is lower in case of scan based testing. It may be noted that
ATPG is off line exercise and test time is very expensive as patterns are applied by an
automatic test equipment. However, scan based testing is still the most widely accepted
technology. As discussed in the exercise of Lecture 1 Module 12, time frame expansion
scheme cannot set/reset flip-flops which are cyclic (i.e., whose input is dependent on its
own output). So scan based scheme or set/reset with shift register scheme is required for
cyclic circuits.

A new scheme called partial scan came up taking ideas from both time frame expansion
method and scan chain method [2]. The basic idea used in the scheme is to make scan
enable only in those flip-flops which are cyclic and keep the remaining ones as normal. So
we will have area overhead (because of MUX) only for those flip-flops which must be
controlled directly and for the others, time frame expansion based indirect control can be
used.

Circuit shown in Figure 18 will be used to illustrate the concept of partial scan.

Figure 18(a) shows a sequential circuit with D-algorithm applied after removing the flip-
flops; the positions of the flip-flops are marked by double ended vertical arrows. It may be
noted that two flip-flops are to be controlled to 1; net d is to be made 1 and net i is to be
made 1. Making net d =1 is simple and can be achieved by applying c =1 and a clock pulse;
this is shown in Figure 18(b). It may be noted that control of net d via F1 is by time frame
expansion method; as dseq=1 for F1, so one clock pulse and one pattern is enough to control
it. To make net i =1, we need b =1, d =1, m =1 (which makes f =1 via net e ) and a clock
pulse. However there is a problem here. To make net m =1 we need j =1 which can be
achieved by a =1, i =1. However to make i =1 we need m =1. This problem arises because
flip-flop F2 is cyclic, as shown in Figure 18(b). So F2 cannot be controlled by time frame
expansion method and it must have scan chain facility, as shown in Figure 18(c).
Figure 18. Cyclic circuits and requirement of scan chain
 Figure 19. ATPG and testing using partial scan technique

The procedure of testing the circuit of Figure 18(c) using partial scan is shown in Figure 19.
As shown in Figure 19(a), net i is set to 1 by making M=1 and applying 1 in Scan in input
with a clock pulse; F2 is set using scan chain. Now (Figure 19(b)) net d is set to 1 by making
M=0 and applying 1 in primary input c with a clock pulse; F1 is set using time frame
expansion. Finally after setting the flip-flops, test pattern a =1, b =1, c =X is applied, which
sensitizes and propagates the fault effect to the output k.
6. Conclusions

In the combined two lectures we have seen testing of sequential circuits with design for
testability techniques, namely set/reset lines, shift register with set/reset
set/reset lines, scan chain
and partial scan chain. Design for testability is additional resources like circuitry or I/O pins
used to make testing easier. Among all the techniques, we saw that partial scan is the most
efficient one as it uses additional resources
resources only when testing becomes infeasible due to
cyclic parts in a circuit. However, sometimes non-cyclic
non flip-flops
flops are also made scan enabled
(in partial scan technique) to minimize ATPG time; as shown in Figure 17 of this lecture,
propagating fault effects
fects by scan chains minimize ATPG effort. Another direction called
multiple chains is taken to minimize test time in scan chain based techniques. In this
scheme, instead of a single scan chain, the chain is broken into multiple parts. The start of
each chain is brought out as separate Scan in and end of the chain is brought out as
separate Scan out. This increases the number of I/Os, but all the smaller chains can be fed
with bits values concurrently, minimizing test time.

Questions and Answers

How can
n test time be reduced for the circuit with scan chain of Figure 14 of this lecture?

Answer:

The circuit in Figure 14 has a single scan chain with three flip-flops.
flip flops. So time taken to
set/reset all the flip-flops
flops is three clock pulses. To save test time the scan chain can be
divided into multiple sub-chains
chains with separate Scan in and Scan out pins. In this case we
have divided the chain into 2 partsone
parts one has F1 and F2 and the second has F3 only. So we
have two sets of Scan in and Scan out pins. The design is illustrated
illustrated in the figure below.
Now both the chains can be loaded concurrently. So, only two clock pulses are required to
set/reset all the flip-flops.

flops themselves be tested in a scan chain based testing?

2. How can the flip-flops
Answer:

An advantage of scan chain based testing over time frame expansion and shift register
technique is the ability to test the flip-flops in the circuit under test. A toggle sequence,
00110011 . . ., of length nff + 4 , where nff is the total number of flip-flops, is applied at
Scan in. This sequence produces all four transitions 00, 01, 11 and 11 in all the flip-
flops. The sequence is brought out through the Scan out pin. So if a correct toggle sequence
is observed in the Scan out pin, then the flip-flops are working normally. It is shown in stuck
at fault model that toggle sequence covers almost all stuck at faults in the flip-flops.