CHAPTER 6

MEMORY INTERFACING
Issues
• Memory Devices
• Address Decoding
• 8086 (8-bit) Memory Interface
 Memory device

Memory unit:

✓A collection of cells capable of storing a large quantity of binary information and

• to which binary information is transferred for storage
• from which information is available when needed
✓Together with associated circuits needed to transfer
information in and out of the device
• write operation: storing new information into memory
• read operation: transferring the stored information out of the memory

Two major types:

RAM (Random-access memory):

Read + Write (RW)
For storing temporary working data
ROM (Read-only memory): …is also random access
Perform only read operation
PROM: Programmable ROM(one time programmable-OTP)
EPROM: Erasable & Programmable ROM
EEPROM (FLASH): Electrically erasable PROM
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Random vs. Sequential memory and Static vs. Dynamic
Random-Access Memory:
• Each word is separately accessible
• Equal access time
e.g. Semiconductor memories, like RAM
Sequential-Access Memory:
• Information stored is not immediately accessible
• Access time is variable
e.g. Magnetic/optical disks
SRAM: (Static RAM)
• Consists of flip-flop latches......takes more chip area
• Shorter read and write cycle….faster
DRAM: (Dynamic RAM)
• Data is stored as charge on capacitors…less chip area
• Each capacitor is controlled by a MOS transistor
• Capacitors tend to discharge with time…needs a periodic re-charge (refresh)…more
power consumption
• Requires complex address decoding & control…slow

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n+1 byte of SRAM & DRAM internally

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 DRAM:
Pros:
• High density (capacity) -> 1GB x 8, currently
• Cheaper cost per bit
Cons:
• Has to be refreshed every 2ms – 4ms
• While it is being refreshed, data can’t be accessed
• Larger access times
• Complex address decoding
• Higher power consumption

DRAM…addressing

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DRAM…timing

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DRAM…packaging
DRAMs are typically placed on SIMM (Single In-line Memory Modules) boards.

Refresh time example:

For a 256K DRAM with 256 rows, a refresh must occur every 15.6µs (4ms/256)
For the 8086, a read or write occurs every 800ns, This allows 19 memory reads/writes per refresh
or 5% of the time

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DRAM refresh logic

A7-A13 A7-A13 A7-A13 A7-A13 A7-A13 A7-A13 A7-A13 A7-A13

A0-A6 A0-A6 A0-A6 A0-A6 A0-A6 A0-A6 A0-A6 A0-A6
16K*1B 16K*1B 16K*1B 16K*1B 16K*1B 16K*1B 16K*1B 16K*1B
𝐎𝐄 CE 𝐎𝐄 CE 𝐎𝐄 CE 𝐎𝐄 CE 𝐎𝐄 CE 𝐎𝐄 CE 𝐎𝐄 CE 𝐎𝐄 CE
A[7:13]

A7-A13 A7-A13 A7-A13 A7-A13 A7-A13 A7-A13 A7-A13 A7-A13

A0-A6 A0-A6 A0-A6 A0-A6 A0-A6 A0-A6 A0-A6 A0-A6
16K*1B 16K*1B 16K*1B 16K*1B 16K*1B 16K*1B 16K*1B 16K*1B
𝐎𝐄 CE 𝐎𝐄 CE 𝐎𝐄 CE 𝐎𝐄 CE 𝐎𝐄 CE 𝐎𝐄 CE 𝐎𝐄 CE 𝐎𝐄 CE

7-bit
bus mux
A[0:6]
Ar[0:6]

CE1 CE2
Ref.Address REFRESH ADDRESS
TIMER DECISION LOGIC
counter Refresh signal

To transreceivers A[14:15]

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 Volatile vs. Non-volatile
Volatile:
• stored information is lost when power is turned off. Typical example: RAM
Non-volatile:
• Data is retained even after power is off. suitable for permanent storage
• Typical example: ROM devices
•
Memory capacity:
• The number of bits that a memory device can store; for semiconductor memories:
• In parallel mode:
• Each memory chip contains 2𝑥 locations x = number of address pins on the chip
• Each location contains y bits: y = number of data pins on the chip Thus, the entire chip will contain
2𝑥 * y bits
• In serial mode:
• two pins are required (data & clock)
• address and Data are time-multiplexed
• (x + y) times slower…x, y as defined above.
Memory control:
• Each memory device has at least one Chip select (CS) or Chip enable (CE) pin that enables the memory
device.
• Each memory device has at least one control pin:
• For ROMs, an output enable (OE) is present. The OE pin enables and disables a set of tri-state buffers.
• For RAMs, a read-write (R/W) or write enable (WE) and read enable (RE) are present
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Interfacing memory with the 8086 microprocessor involves several key steps to ensure proper
communication and data transfer. Here's a structured approach:

1. Demultiplex the Address/Data Bus

AD0–AD15: These pins carry both addresses (A0–A15) and data (D0–D15). Use a 74LS373 latch
controlled by the ALE (Address Latch Enable) signal to separate the address from the data.
A16–A19: These are dedicated address pins (no multiplexing) and directly connect to memory.

2. Address Decoding
Generate Chip Select (CS): Use higher address lines (A16–A19) and logic gates (e.g., 74LS138 decoder)
to activate memory chips when the address falls within their designated range.

Example: For a 64KB RAM at 00000H–0FFFFH, decode A19–A16 = 0000.

Combine with M/IO: Ensure memory access (not I/O) by including the M/IO signal (high for memory).

3. Bank Selection (Even/Odd)

Byte/Word Access: The 8086 uses two 8-bit memory banks:
Lower Bank (Even): Selected when A0 = 0, connected to D0–D7.
Upper Bank (Odd): Selected when BHE (Bus High Enable) = 0, connected to D8–D15.
Control Logic:
Lower Bank CS = Memory_CS AND (A0 = 0)
Upper Bank CS = Memory_CS AND (BHE = 0)

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4. Control Signals
Read/Write Operations:
OE (Output Enable): Connect to RD (Read) and CS for read operations.
WE (Write Enable): Connect to WR (Write) and CS for write operations.
Direction Control: Use bidirectional buffers (e.g., 74LS245) if needed for data bus isolation.

5. Timing Considerations
Access Time: Ensure memory chips meet the 8086’s timing requirements. Use the READY signal to
insert wait states if memory is slower than the CPU clock.

6. Memory Organization
8-bit Memory Chips: Use two chips in parallel (lower and upper banks) for 16-bit data.
Address Lines: Connect A1–A19 (latched) to memory chips, with A0/BHE handling bank selection.

Example Circuit
Demultiplexing: AD0–AD15 → 74LS373 (latched by ALE) → A0–A15.
Address Decoder: A16–A19 + M/IO → 74LS138 → Memory_CS.
Bank Selection: Memory_CS + A0/BHE → AND gates → Lower/Upper Bank CS.
Data Bus: D0–D15 directly connected to memory banks.
Control Signals: RD → OE, WR → WE (gated by CS).

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Key Points
• Alignment: Word accesses at even addresses use both banks; odd addresses require two cycles.
• Overlap Prevention: Ensure address decoding is precise to avoid memory conflicts.
• Mode Dependency: Adjust control signals if using 8086 in maximum mode (requires 8288 bus
controller).

• By following these steps, you can interface memory with the 8086, ensuring correct addressing,
data transfer, and timing. Always verify timing diagrams and datasheets for compatibility between
components.

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Min mode 8086 µp system memory circuitry

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ADDRESS BUS
SYSTEM:

LATCHED
ADDRESS BUS:

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• Before going to the address decoder logic, we have to revise the 8086 memory addressing
scheme
• Memory address is 20-bit and I/O address is 16-bit wide
• There are reserved locations, like interrupt vector table…
• A given memory device can be mapped to any address space by properly designing the address
decoder logic.

Address Bus system…Address Selection:

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Address decoder:
E.g. 1 A 32KB RAM is to be interfaced to an 8086 based system, so that the first address of the RAM is
at 48000H.
• What is the entire range of the RAM Address?
• How is the address bus used to enable the RAM?
• What address lines should be used?

Address decoder for:

48000h – 4FFFFh range

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E.g. 2 Given a 2K x 8 (2KB) EPROM, 27C16 for storing the BIOS How would you decode the address to
map this EPROM in an 8086 system?

The BIOS should be located starting at FFFF0H: i.e. CS: F000h IP: FFF0h

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E.g. 3 Now assume you have eight 8K x 8 (8KB) EPROMs 27C64 to be mapped from F0000h to FFFFFh to
form a total of 64KB:

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Address decoder…74138 (3 to 8 decoder)
• A13, A14, A15 selects one of the memory chips at a time
• G1, G2A and G2B enables the decoder, thus address lines A16-A19 enable the decoder
• In this case A16-A19 = 1111 (b/c the mapping starts at F0000)
• Therefore, data can be latched to the selected memory chip (one of the eight) at the desired
address.

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