1
Memory &
Programmable Logic Devices
▪ ROM & RAM
▪ PLA & PAL
1
Memory
▪ Memory: A collection of cells capable of storing binary
information (1s or 0s) – in addition to electronic circuit
for storing (writing) and retrieving (reading) information.
n data
input lines
n
k
k address lines Memory unit
2k words
• n data lines (input/output) n bits per word
Read/Write
• k address lines
• 2k words (data unit) n
• Read/Write Control n data
• Memory size = 2k X n output lines
Digital Logic & Computer Design
by M. Morris Mano 3
Memory
Two Types of Memory:
▪ Random Access Memory (RAM):
❖ Write/Read operations
❖ Volatile: Data is lost when power is turned off
▪ Read Only Memory (ROM):
❖ Read operation (no write)
❖ Non-Volatile: Data is permanent.
❖ PROM is programmable (allow special write)
Digital Logic & Computer Design
by M. Morris Mano 4
2
Types of Memories
◼ In random-access memory, the word locations may be
thought of as being separated in space, with each word
occupying one particular location.
◼ In sequential-access memory, the information stored in
some medium is not immediately accessible, but is
available only certain intervals of time. A magnetic disk
or tape unit is of this type.
Digital Logic & Computer Design
by M. Morris Mano 5
Types of Memories
◼ In a random-access memory, the access time is always
the same regardless of the particular location of the
word.
◼ In a sequential-access memory, the time it takes to
access a word depends on the position of the word with
respect to the reading head position; therefore, the
access time is variable.
Digital Logic & Computer Design
by M. Morris Mano 6
3
Programmable Logic Devices
▪ Programmable Logic Device (PLD) is an integrated
circuit with internal logic gates and/or connections that
can in some way be changed by a programming
process
▪ Examples:
❖ PROM
❖ Programmable Logic Array (PLA)
❖ Programmable Array Logic (PAL) device
❖ Complex Programmable Logic Device (CPLD)
❖ Field-Programmable Gate Array (FPGA)
▪ A PLD’s function is not fixed
▪ Can be programmed to perform different functions
Digital Logic & Computer Design
by M. Morris Mano 7
Why PLDs?
▪ Fact:
❖ It is most economical to produce an IC in large volumes
▪ But:
❖ Many situations require only small volumes of ICs
❖ Many situations require changes to be done in the field, e.g.
Firmware of a product under development
▪ A programmable logic device can be:
❖ Produced in large volumes
❖ Programmed to implement many different low-volume designs
Digital Logic & Computer Design
by M. Morris Mano 8
4
PLD Hardware Programming Technology
▪ In the Factory - Cannot be erased/reprogrammed by
user
❖ Mask programming (changing the VLSI mask) during
manufacturing
▪ Programmable only once
❖ Fuse
❖ Anti-fuse
▪ Reprogrammable (Erased & Programmed many times)
❖ Volatile - Programming lost if chip power lost
• Single-bit storage element
❖ Non-Volatile - Programming survives power loss
• UV Erasable
• Electrically Erasable
• Flash (as in Flash Memory)
Digital Logic & Computer Design
by M. Morris Mano 9
Used Symbol in PLD
There is a connection
Multi-input OR gate There is no connection
conventional symbol array logic symbol
▪ Most PLD technologies have gates with very high fan-in
▪ Fuse map: graphic representation of the selected
connections
Digital Logic & Computer Design
by M. Morris Mano 10
5
Programmable Logic Devices
Fuses Fused
Fixed programmable
Inputs Outputs
AND array OR array
Programmable Read Only Memory (PROM)
Fuses Fused
Fixed
Inputs programmable Outputs
OR array
AND array
Programmable Array Logic (PAL)
Fuses Fused Fuses Fused
Inputs programmable programmable Outputs
AND array OR array
Programmable Logic Array (PLA)
Digital Logic & Computer Design
by M. Morris Mano 11
Programmable Logic Devices
▪ “Programming” an array – blowing the fuses.
A A' B B' A A' B B'
x1 x1 = A.B
x2 x2 = A’.B
x3 x3 = A.B’
(a) Unprogrammed (b) Programmed
Example of a basic AND array
Digital Logic & Computer Design
by M. Morris Mano 12
6
Read-Only Memory (ROM)
▪ A device in which “permanent” binary information is
stored using a special device (programmer)
k inputs 2k x n n outputs
(address) ROM (data)
▪ k inputs (address) → 2k words each of size n bits (data)
▪ ROM DOES NOT have a write operation ➔ ROM DOES
NOT have data inputs
Word: group of bits stored in one location
Digital Logic & Computer Design
by M. Morris Mano 13
Read-Only Memory (ROM)
▪ Logically, this memory device can be regarded as a table
of memory cells (data).
0 1-word data
1
Addresses 2
3
:
: : 1-bit data
: :
:
n
word size
Digital Logic & Computer Design
by M. Morris Mano 14
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Read-Only Memory (ROM)
▪ Different types of ROM devices available:
❖ ROM: Read-Only Memory
Data written into memory by mask programming during
manufacturing time. Expensive start-up cost but economical for
high volume. Cannot be erased after data are programmed in.
❖ PROM: Programmable ROM
Semi-custom chip. Fuses can be broken by special hardware
programmer unit. Cost-effective for low volumes. Cannot be
erased after programming.
Digital Logic & Computer Design
by M. Morris Mano 15
Read-Only Memory (ROM)
❖ EPROM: Erasable PROM
Similar to PROM except that data can be completely erased by
exposure to ultra-violet light.
❖ EEPROM: Electrically Erasable PROM
A PROM where data can be selectively erased by hardware
programmer unit, rather than by ultra-violet light. Useful for
remote devices which can be re-programmed from a distance.
Digital Logic & Computer Design
by M. Morris Mano 16
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Programming a ROM
▪ Every ONE in truth table specifies a closed circuit
▪ Every ZERO in truth table specifies an OPEN circuit
▪ Example: At address 00011 → The word 10110010 is
stored
Digital Logic & Computer Design
by M. Morris Mano 17
Programmable Read-Only Memory (PROM)
▪ Devices with fixed AND array (which is a decoder) and
programmable OR array.
▪ The AND array (decoder) generates all 2n possible
minterm products of its n inputs (often referred to as n-
to-2n decoder).
▪ n input lines, m output lines.
▪ Bit combination of input variables – address.
▪ Bit combination of output lines – word (each word
contains m bits).
Digital Logic & Computer Design
by M. Morris Mano 18
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Programmable Read-Only Memory (PROM)
I0 X X X X
AND array
X X X X
Fixed
I1 X X X X
X X X X
I2 X X X X
X X X X
Programmable
O1
OR array
O2
. .
Ok
m0 m1 m2 m3 m4 m5 m6 m7
Minterms
Programmable read-only memory (PROM) can realize K functions f(I2,I1,I0).
Digital Logic & Computer Design
by M. Morris Mano 19
Programmable Read-Only Memory (PROM)
Minterms
Address
input
0
A0 1
A1 2
A2 5 x 32 .
.
A3 decoder .
A4
31
... ... ... ...
128 fuses
F1 F2 F3 F4
Logic construction of a 32 x 4 ROM.
Digital Logic & Computer Design
by M. Morris Mano 20
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Realising Logic Functions with PROMs
▪ Example (8 x 3 ROM):
f1(A,B,C) = A.B + B’.C
f2(A,B,C) = (A+B’+C).(A’+B)
f3(A,B,C) = A + B.C
▪ First, we convert each function to canonical SOP form.
f1(A,B,C) = A.B + B’.C = A.B.C’ + A.B.C + A’.B’.C + A.B’.C
= S m(1,5,6,7)
f2(A,B,C) = (A+B’+C).(A’+B)
= (A+B’+B).(A’+B+C’).(A’+B+C)
= P M(2,4,5) = S m(0,1,3,6,7)
f3(A,B,C) = A + B.C = A.B’.C’ + A.B’.C + A.B.C’ + A.B.C + A’.B.C
= S m(3,4,5,6,7)
Digital Logic & Computer Design
by M. Morris Mano 21
Realising Logic Functions with PROMs
C X X X X
AND array
X X X X
Fixed
B X X X X
X X X X
A X X X X
X X X X
Programmable
X X X X f1 = S m(1,5,6,7)
OR array
X X X X X f2 = S m(0,1,3,6,7)
X X X X X f3 = S m(3,4,5,6,7)
m0 m1 m2 m3 m4 m5 m6 m7
Minterms
Digital Logic & Computer Design
by M. Morris Mano 22
11
Realising Logic Functions with PROMs
Minterms
Address
input
C 0
3x8 1
B 2
A decoder 3
4
5
6
7
8 x 3 ROM
0: 0 1 0
1: 1 1 0
2: 0 0 0
3: 0 1 1
4: 0 0 1 f1 = Sm(1,5,6,7) f3 = Sm(3,4,5,6,7)
5: 1 0 1
f2 = Sm(0,1,3,6,7)
6: 1 1 1
7: 1 1 1
Digital Logic & Computer Design
by M. Morris Mano 23
Combinational Circuit Implementation with ROM
▪ ROM = Decoder + OR gates
▪ Implementation of a combinational circuit is easy
❖ Store the truth table by programming the ROM
▪ Only need to provide the truth table
Digital Logic & Computer Design
by M. Morris Mano 24
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Combinational Circuit Implementation with ROM
Example: Design a combinational circuit using ROM. The
circuit accepts a 3-bit number and generates an output
binary number equal to the square of the number.
Solution: Derive truth table:
Inputs Outputs
A2 A1 A0 B5 B4 B3 B2 B1 B0 SQ
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0 4
0 1 1 0 0 1 0 0 1 9
1 0 0 0 1 0 0 0 0 16
1 0 1 0 1 1 0 0 1 25
1 1 0 1 0 0 1 0 0 36
1 1 1 1 1 0 0 0 1 49
Digital Logic & Computer Design
by M. Morris Mano 25
Combinational Circuit Implementation with ROM
Inputs Outputs
A2 A1 A0 B5 B4 B3 B2 B1 B0 SQ
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0 4
0 1 1 0 0 1 0 0 1 9
1 0 0 0 1 0 0 0 0 16
1 0 1 0 1 1 0 0 1 25
1 1 0 1 0 0 1 0 0 36
1 1 1 1 1 0 0 0 1 49
ROM truth table – specifies the required connections B0
0 B1
B1 is ALWAYS 0 ➔ no need to generate it using the ROM A0 B2
B3
B0 is equal to A0 ➔ no need to generate it using the ROM A1 8 X 4 ROM
B4
Therefore: The minimum size of ROM needed is 23X4 or A2 B5
8X4
Digital Logic & Computer Design
by M. Morris Mano 26
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Sequential Circuit Implementation with ROM
inputs X Combinational outputs Z
Circuits
present state next state
FFs
▪ Sequential circuit = Combinational circuit + Memory
▪ Combinational part can be built with a ROM as shown
previously
▪ Number of address lines = No. of FF + No. of inputs
▪ Number of outputs = No. of FF + No. of outputs
Digital Logic & Computer Design
by M. Morris Mano 27
Sequential Circuit Implementation with ROM
◼ Example: Design a sequential circuit whose state table
is given, using a ROM and a register.
We need a 8x3 ROM (why?)
3 address lines and 3 data lines
Digital Logic & Computer Design
by M. Morris Mano 28
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Programmable Logic Array (PLA)
▪ Combination of a programmable AND array followed by
a programmable OR array.
▪ Example: Design a PLA to realise the following three
logic functions and show the internal connections.
f1(A,B,C,D,E) = A’.B’.D’ + B’.C.D’ + A’.B.C.D.E’
f2(A,B,C,D,E) = A’.B.E + B’.C.D’.E
f3(A,B,C,D,E) = A’.B’.D’ + B’.C’.D’.E + A’.B.C.D
Digital Logic & Computer Design
by M. Morris Mano 29
Realizing Logic Functions with PLA
f1(A,B,C,D,E) = A'.B'.D' + B'.C.D' + A'.B.C.D.E'
f2(A,B,C,D,E) = A'.B.E + B'.C.D'.E
f3(A,B,C,D,E) = A'.B'.D' + B'.C'.D'.E + A'.B.C.D
A
X X X X
X X X
Programmable
B
X X X X
AND array
C X X X X
X
D X X
X X X X
E X X X
X
Programmable
OR array
A'.B'.D'XB'.C.DX' A'.BX.C.D.E' f1
X X f2
X X X f3
P1 P2 P3 P4 P5 P6 P7
A'B'D' A'BCDE' B'CD'E A'BCD
B'CD' A'BE B'C'D'E
Digital Logic & Computer Design
by M. Morris Mano 30
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Random Access Memory (RAM)
▪ A memory unit stores binary information in groups of bits
called words.
▪ The data consists of n lines (for n-bit words). Data input
lines provide the information to be stored (written) into
the memory, while data output lines carry the
information out (read) from the memory.
▪ The address consists of k lines which specify which
word (among the 2k words available) to be selected for
reading or writing.
▪ The control lines Read and Write (usually combined into
a single control line Read/Write) specifies the direction
of transfer of the data.
Digital Logic & Computer Design
by M. Morris Mano 31
RAM Architecture
Digital Systems – Principles & Applications
by R. J. Tocci 32
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Random Access Memory (RAM)
▪ Content of a 1024 x 16-bit memory:
Memory address
binary decimal Memory content
0000000000 0 1011010111011101
0000000001 1 1010000110000110
0000000010 2 0010011101110001
: : :
: : :
1111111101 1021 1110010101010010
1111111110 1022 0011111010101110
1111111111 1023 1011000110010101
Digital Logic & Computer Design
by M. Morris Mano 33
Random Access Memory (RAM)
▪ The Write operation:
❖ Transfers the address of the desired word to the address lines
❖ Transfers the data bits (the word) to be stored in memory to the
data input lines
❖ Activates the Write control line (set Read/Write to 0)
▪ The Read operation:
❖ Transfers the address of the desired word to the address lines
❖ Activates the Read control line (set Read/Write to 1)
Digital Logic & Computer Design
by M. Morris Mano 34
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Random Access Memory (RAM)
▪ The Read/Write operation:
▪ Two types of RAM: Static and dynamic.
❖ Static RAMs use flip-flops as the memory cells.
❖ Dynamic RAMs use capacitor charges to represent data.
Though simpler in circuitry, they have to be constantly
refreshed.
Digital Logic & Computer Design
by M. Morris Mano 35
Random Access Memory (RAM)
▪ A single memory cell of the static RAM has the following
logic and block diagrams.
Select
Select
R
Input S Q Output Input BC Output
Read/Write
Read/Write
Logic diagram Block diagram
Digital Logic & Computer Design
by M. Morris Mano 36
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Random Access Memory (RAM)
▪ Logic construction of a 4 x 4 RAM (with decoder and OR
gates):
Digital Logic & Computer Design
by M. Morris Mano 37
Random Access Memory (RAM)
◼ Dynamic RAM stores data as charges on capacitors,
which gradually disappear due to capacitor discharge.
❖ It is necessary to refresh the data periodically by recharging
capacitors—typically every 2, 4, or 8 ms.
During a WRITE operation, switches SW1 and SW2 are closed.
During a read operation, all switches are closed except SW1.
Digital Systems – Principles & Applications
by R. J. Tocci 38
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Random Access Memory (RAM)
▪ An array of RAM chips: memory chips are combined to
form larger memory.
▪ A 1K x 8-bit RAM chip:
RAM 1K x 8
Input data 8 DATA (8) 8
(8) Output data
Address 10 ADRS (10)
Chip select CS
Read/write RW
Block diagram of a 1K x 8 RAM chip
Digital Logic & Computer Design
by M. Morris Mano 39
Random Access Memory (RAM)
Address
Input data
Lines Lines 8 lines
11 10 0–9 0–1023
DATA (8) (8)
ADRS (10)
2x4 CS
decoder 1K x 8
RW
S0 0 1024 – 2047
1 DATA (8) (8)
S1 2 ADRS (10)
3 CS
1K x 8
RW
2048 – 3071
Read/write DATA (8) (8)
ADRS (10)
CS
1K x 8
RW
3072 – 4095
DATA (8)
▪ 4K x 8 RAM
(8)
ADRS (10)
CS
1K x 8 Output
RW
data
Digital Logic & Computer Design
by M. Morris Mano 40
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The End
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