4 Ω RON, 4-/8-Channel,

±15 V/+12 V/±5 V iCMOS Multiplexers

Data Sheet ADG1408/ADG1409
FEATURES FUNCTIONAL BLOCK DIAGRAMS
4.7 Ω maximum on resistance at 25°C ADG1408 ADG1409
0.5 Ω on-resistance flatness S1 S1A
Up to 190 mA continuous current DA
Fully specified at ±15 V/+12 V/±5 V S4A

3 V logic-compatible inputs D
Rail-to-rail operation
S1B
Break-before-make switching action DB
16-lead TSSOP and 4 mm × 4 mm LFCSP S8 S4B

APPLICATIONS 1-OF-8 1-OF-4

DECODER DECODER
Relay replacement

04861-001
Audio and video routing
A0 A1 A2 EN A0 A1 EN
Automatic test equipment
Figure 1.
Data acquisition systems
Temperature measurement systems
Avionics
Battery-powered systems
Communication systems
Medical equipment

GENERAL DESCRIPTION The ultralow on resistance and on resistance flatness of these

The ADG1408/ADG1409 are monolithic iCMOS® analog multip- switches make them ideal solutions for data acquisition and
lexers comprising eight single channels and four differential gain switching applications where low distortion is critical.
channels, respectively. The ADG1408 switches one of eight iCMOS construction ensures ultralow power dissipation,
inputs to a common output, as determined by the 3-bit binary making the devices ideally suited for portable and battery-
address lines, A0, A1, and A2. The ADG1409 switches one of powered instruments.
four differential inputs to a common differential output, as PRODUCT HIGHLIGHTS
determined by the 2-bit binary address lines, A0 and A1. An EN 1. 4 Ω on resistance.
input on both devices is used to enable or disable the device. 2. 0.5 Ω on-resistance flatness.
When disabled, all channels are switched off. 3. 3 V logic compatible digital input, VIH = 2.0 V, VIL = 0.8 V.
The industrial CMOS (iCMOS) modular manufacturing process 4. 16-lead TSSOP and 4 mm × 4 mm LFCSP.
combines high voltage complementary metal-oxide semiconductor
(CMOS) and bipolar technologies. It enables the development Table 1. Related Devices
of a wide range of high performance analog ICs capable of 33 V Device No. Description
operation in a footprint that no other generation of high voltage ADG1208/ADG1209 Low capacitance, low charge injection,
and low leakage 4-/8-channel ±15 V
devices has been able to achieve. Unlike analog ICs using
multiplexers
conventional CMOS processes, iCMOS components can tolerate
high supply voltages while providing increased performance,
dramatically lower power consumption, and reduced package size.

Rev. D Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADG1408/ADG1409 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Continuous Current per channel, S or D ...................................8
Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................9
Functional Block Diagrams ............................................................. 1 Thermal Resistance .......................................................................9
General Description ......................................................................... 1 ESD Caution...................................................................................9
Product Highlights ........................................................................... 1 Pin Configurations and Function Descriptions ......................... 10
Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 12
Specifications..................................................................................... 3 Terminology .................................................................................... 16
15 V Dual Supply .......................................................................... 3 Test Circuits ..................................................................................... 17
12 V Single Supply ........................................................................ 5 Outline Dimensions ....................................................................... 19
5 V Dual Supply ............................................................................ 7 Ordering Guide .......................................................................... 19

REVISION HISTORY
6/2016—Rev. C to Rev. D
Changes to Analog Inputs Parameter, Table 6 .............................. 9
Added Digital Inputs Parameter, Table 6 ...................................... 9

5/2016—Rev. B to Rev. C
Changed CP-16-13 to CP-16-26 .................................. Throughout
Changes to Figure 3 ........................................................................ 10
Changes to Figure 5 ........................................................................ 11
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20

3/2009—Rev. A to Rev. B
Change to IDD Parameter, Table 2 ................................................... 4
Change to IDD Parameter, Table 3 ................................................... 6

8/2008—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Added Table 5; Renumbered Sequentially .................................... 8
Changes to Table 6 ............................................................................ 9
Added Exposed Pad Notation to Figure 3 ................................... 10
Added Exposed Pad Notation to Figure 5 ................................... 11
Added Exposed Pad Notation to Outline Dimensions ............. 19

8/2006—Revision 0: Initial Version

Rev. D | Page 2 of 19
Data Sheet ADG1408/ADG1409

SPECIFICATIONS
15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 2.
−40°C to −40°C to
Parameter +25°C +85°C +125°C1 Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS to VDD V
On Resistance (RON) 4 Ω typ VS = ±10 V, IS = −10 mA; see Figure 26
4.7 5.7 6.7 Ω max VDD = +13.5 V, VSS = −13.5 V
On Resistance Match Between 0.2 Ω typ VS = ±10 V, IS = −10 mA
Channels (ΔRON)
0.78 0.85 1.1 Ω max
On-Resistance Flatness (RFLAT(ON)) 0.5 Ω typ VS = ±10 V, IS = −10 mA
0.72 0.77 0.92 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off ) ±0.04 nA typ VS = ±10 V, VD = ∓10 V; see Figure 27
±0.2 ±0.6 ±5 nA max
Drain Off Leakage, ID (Off ) ±0.04 nA typ VS = ±10 V, VD = ∓10 V; see Figure 27
±0.45 ±2 ±30 nA max
Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = ±10 V; see Figure 28
±1.5 ±3 ±30 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current ±0.005 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 4 pF typ
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION 140 ns typ RL = 100 Ω, CL = 35 pF
170 210 240 ns max VS = 10 V, see Figure 29
Break-Before-Make Time Delay, tBBM 50 ns typ RL = 100 Ω, CL = 35 pF
30 ns min VS1 = VS2 = 10 V; see Figure 30
tON (EN) 100 ns typ RL = 100 Ω, CL = 35 pF
120 150 165 ns max VS = 10 V; see Figure 31
tOFF (EN) 100 ns typ RL = 100 Ω, CL = 35 pF
120 150 170 ns max VS = 10 V; see Figure 31
Charge Injection −50 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32
Off Isolation −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33
Channel-to-Channel Crosstalk −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34
Total Harmonic Distortion Plus 0.025 % typ RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz;
Noise (THD + N) see Figure 36
−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 35
ADG1408 60 MHz typ
ADG1409 115 MHz typ
Insertion Loss 0.24 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
CS (Off ) 14 pF typ f = 1 MHz
CD (Off ) f = 1 MHz
ADG1408 80 pF typ
ADG1409 40 pF typ

Rev. D | Page 3 of 19
ADG1408/ADG1409 Data Sheet
−40°C to −40°C to
Parameter +25°C +85°C +125°C1 Unit Test Conditions/Comments
CD, CS (On) f = 1 MHz
ADG1408 135 pF typ
ADG1409 90 pF typ
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 0.002 μA typ Digital inputs = 0 V or VDD
1 μA max
220 μA typ Digital inputs = 5 V
380 μA max
ISS 0.002 μA typ Digital inputs = 0 V, 5 V or VDD
1 μA max
VDD/VSS ±4.5/±16.5 V min/max
1
Temperature range: Y version: −40°C to +125°C.
2
Guaranteed by design, not subject to production test.

Rev. D | Page 4 of 19
Data Sheet ADG1408/ADG1409
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.
−40°C to −40°C to
Parameter +25°C +85°C +125°C1 Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to VDD V
On Resistance (RON) 6 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 26
8 9.5 11.2 Ω max VDD = 10.8 V, VSS = 0 V
On-Resistance Match Between 0.2 Ω typ VS = 0 V to 10 V, IS = −10 mA
Channels (ΔRON)
0.82 0.85 1.1 Ω max
On-Resistance Flatness (RFLAT(ON)) 1.5 Ω typ VS = 0 V to 10 V, IS = −10 mA
2.5 2.5 2.8 Ω max
LEAKAGE CURRENTS VDD = 13.2 V
Source Off Leakage, IS (Off ) ±0.04 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27
±0.2 ±0.6 ±5 nA max
Drain Off Leakage, ID (Off ) ±0.04 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27
±0.45 ±1 ±37 nA max
Channel On Leakage, ID, IS (On) ±0.06 nA typ VS = VD = 1 V or 10 V; see Figure 28
±0.44 ±1.3 ±32 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current ±0.005 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION 200 ns typ RL = 100 Ω, CL = 35 pF
260 330 380 ns max VS = 8 V; see Figure 29
Break-Before-Make Time Delay, tBBM 90 ns typ RL = 100 Ω, CL = 35 pF
40 ns min VS1 = VS2 = 8 V; see Figure 30
tON (EN) 160 ns typ RL = 100 Ω, CL = 35 pF
210 250 285 ns max VS = 8 V; see Figure 31
tOFF (EN) 115 ns typ RL = 100 Ω, CL = 35 pF
145 180 200 ns max VS = 8 V; see Figure 31
Charge Injection −12 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32
Off Isolation −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33
Channel-to-Channel Crosstalk −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34
−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 35
ADG1408 36 MHz typ
ADG1409 72 MHz typ
Insertion Loss 0.5 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
CS (Off ) 25 pF typ f = 1 MHz
CD (Off ) f = 1 MHz
ADG1408 165 pF typ
ADG1409 80 pF typ
CD, CS (On) f = 1 MHz
ADG1408 200 pF typ
ADG1409 120 pF typ

Rev. D | Page 5 of 19
ADG1408/ADG1409 Data Sheet
−40°C to −40°C to
Parameter +25°C +85°C +125°C1 Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = 13.2 V
IDD 0.002 μA typ Digital inputs = 0 V or VDD
1 μA max
220 μA typ Digital inputs = 5 V
380 μA max
VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V
1
Temperature range for Y version: −40°C to +125°C.
2
Guaranteed by design, not subject to production test.

Rev. D | Page 6 of 19
Data Sheet ADG1408/ADG1409
5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.

Table 4.
−40°C to −40°C to
Parameter +25°C +85°C +125°C1 Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS to VDD V
On Resistance (RON) 7 Ω typ VS = ±4.5 V, IS = −10 mA; see Figure 26
9 10.5 12 Ω max VDD = +4.5 V, VSS = −4.5 V
On-Resistance Match Between 0.3 Ω typ VS = ±4.5 V, IS = −10 mA
Channels (ΔRON)
0.78 0.91 1.1 Ω max
On-Resistance Flatness (RFLAT(ON)) 1.5 Ω typ VS = ±4.5 V; IS = −10 mA
2.5 2.5 3 Ω max
LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V
Source Off Leakage, IS (Off ) ±0.02 nA typ VS = ±4.5 V, VD = ∓4.5 V; see Figure 27
±0.2 ±0.6 ±5 nA max
Drain Off Leakage, ID (Off ) ±0.02 nA typ VS = ±4.5 V, VD = ∓4.5 V; see Figure 27
±0.45 ±0.8 ±20 nA max
Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = ±4.5 V; see Figure 28
±0.3 ±1.1 ±22 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current ±0.005 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION 330 ns typ RL = 100 Ω, CL = 35 pF
440 530 550 ns max VS = 5 V; see Figure 29
Break-Before-Make Time Delay, tBBM 100 ns typ RL = 100 Ω, CL = 35 pF
50 ns min VS1 = VS2 = 5 V; see Figure 30
tON (EN) 245 ns typ RL = 100 Ω, CL = 35 pF
330 400 440 ns max VS = 5 V; see Figure 31
tOFF (EN) 215 ns typ RL = 100 Ω, CL = 35 pF
285 335 370 ns max VS = 5 V; see Figure 31
Charge Injection –10 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32
Off Isolation –70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33
Channel-to-Channel Crosstalk –70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34
Total Harmonic Distortion Plus 0.06 % typ RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz;
Noise (THD + N) see Figure 36
−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 35
ADG1408 40 MHz typ
ADG1409 80 MHz typ
Insertion Loss 0.5 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
CS (Off ) 20 pF typ f = 1 MHz
CD (Off ) f = 1 MHz
ADG1408 130 pF typ
ADG1409 65 pF typ
CD, CS (On) f = 1 MHz
ADG1408 180 pF typ
ADG1409 120 pF typ

Rev. D | Page 7 of 19
ADG1408/ADG1409 Data Sheet
−40°C to −40°C to
Parameter +25°C +85°C +125°C1 Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
ISS 0.001 μA typ Digital inputs = 0 V, 5 V or VDD
1 μA max
VDD/VSS ±4.5/±16.5 V min/max
1
Temperature range for Y version: −40°C to +125°C.
2
Guaranteed by design, not subject to production test.

CONTINUOUS CURRENT PER CHANNEL, S OR D

Table 5.
Parameter 25°C 85°C 125°C Unit Test Conditions/Comments
CONTINUOUS CURRENT, S or D1
15 V Dual Supply VDD = +13.5 V, VSS = −13.5 V
ADG1408 190 105 50 mA max
ADG1409 140 85 45 mA max
12 V Single Supply VDD = 10.8 V, VSS = 0 V
ADG1408 160 95 50 mA max
ADG1409 120 75 40 mA max
5 V Dual Supply VDD = +4.5 V, VSS = −4.5 V
ADG1408 155 90 45 mA max
ADG1409 115 70 40 mA max
1
Guaranteed by design, not subject to production test.

Rev. D | Page 8 of 19
Data Sheet ADG1408/ADG1409

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
Table 6. stress rating only; functional operation of the product at these
Parameter Rating or any other conditions above those indicated in the operational
VDD to VSS 35 V section of this specification is not implied. Operation beyond
VDD to GND −0.3 V to +25 V the maximum operating conditions for extended periods may
VSS to GND +0.3 V to −25 V affect product reliability.
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V
or 30 mA, whichever Only one absolute maximum rating can be applied at any
occurs first one time.
Digital Inputs1 GND − 0.3 V to VDD + 0.3 V THERMAL RESISTANCE
or 30 mA, whichever
occurs first θJA is specified for the worst-case conditions, that is, a device
Continuous Current, S or D Table 5 data + 10% soldered in a circuit board for surface-mount packages.
Peak Current, S or D (Pulsed at 1 ms, 350 mA
10% Duty Cycle Maximum) Table 7. Thermal Resistance
Operating Temperature Range Package Type θJA θJC Unit
Industrial (Y Version) −40°C to +125°C 16-Lead TSSOP 150.4 50 °C/W
Storage Temperature Range −65°C to +150°C 16-Lead LFCSP 30.4 °C/W
Junction Temperature 150°C
Reflow Soldering Peak Temperature 260(+0/−5)°C
(RoHS Compliant) ESD CAUTION
1
Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.

Rev. D | Page 9 of 19
ADG1408/ADG1409 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

16 EN
15 A0
14 A1
13 A2
A0 1 16 A1
EN 2 15 A2
VSS 3 14 GND
ADG1408 VSS 1 12 GND
S1 4 TOP VIEW 13 VDD S1 2 ADG1408 11 VDD
(Not to Scale)
S2 5 12 S5 S2 3 TOP VIEW 10 S5
(Not to Scale)
S3 6 11 S6 S3 4 9 S6
S4 7 10 S7

04861-002

S7 8
S8 7
S4 5
D 6
D 8 9 S8

NOTES
1. THE EXPOSED PAD IS
CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM

04861-003
THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SUBSTRATE, VSS.

Figure 2. ADG1408 Pin Configuration (TSSOP) Figure 3. ADG1408 Pin Configuration (LFCSP)

Table 8. ADG1408 Pin Function Descriptions

Pin No.
TSSOP LFCSP Mnemonic Description
1 15 A0 Logic Control Input.
2 16 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
3 1 VSS Most Negative Power Supply Potential. In single supply applications, it can be connected to ground.
4 2 S1 Source Terminal 1. Can be an input or an output.
5 3 S2 Source Terminal 2. Can be an input or an output.
6 4 S3 Source Terminal 3. Can be an input or an output.
7 5 S4 Source Terminal 4. Can be an input or an output.
8 6 D Drain Terminal. Can be an input or an output.
9 7 S8 Source Terminal 8. Can be an input or an output.
10 8 S7 Source Terminal 7. Can be an input or an output.
11 9 S6 Source Terminal 6. Can be an input or an output.
12 10 S5 Source Terminal 5. Can be an input or an output.
13 11 VDD Most Positive Power Supply Potential.
14 12 GND Ground (0 V) Reference.
15 13 A2 Logic Control Input.
16 14 A1 Logic Control Input.
Not 0 EPAD Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
applicable maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.

Table 9. ADG1408 Truth Table

A2 A1 A0 EN On Switch
X X X 0 None
0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8

Rev. D | Page 10 of 19
Data Sheet ADG1408/ADG1409

13 GND
16 EN
15 A0
14 A1
A0 1 16 A1
EN 2 15 GND
VSS 3 14 VDD
ADG1409
TOP VIEW VSS 1 12 VDD
S1A 4 13 S1B
(Not to Scale) S1A 2 11 S1B
S2A 5 12 S2B ADG1409
TOP VIEW 10 S2B
S2A 3
S3A 6 11 S3B (Not to Scale)
S3A 4 9 S3B
S4A 7 10 S4B

04861-004
DA 8 9 DB

S4B 8
DB 7
S4A 5
DA 6
NOTES
1. THE EXPOSED PAD IS
CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM

04861-005
THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SUBSTRATE, VSS.

Figure 4. ADG1409 Pin Configuration (TSSOP) Figure 5. ADG1409 Pin Configuration (LFCSP)

Table 10. ADG1409 Pin Function Descriptions

Pin No.
TSSOP LFCSP Mnemonic Description
1 15 A0 Logic Control Input.
2 16 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
3 1 VSS Most Negative Power Supply Potential. In single supply applications, it can be connected to ground.
4 2 S1A Source Terminal 1A. Can be an input or an output.
5 3 S2A Source Terminal 2A. Can be an input or an output.
6 4 S3A Source Terminal 3A. Can be an input or an output.
7 5 S4A Source Terminal 4A. Can be an input or an output.
8 6 DA Drain Terminal A. Can be an input or an output.
9 7 DB Drain Terminal B. Can be an input or an output.
10 8 S4B Source Terminal 4B. Can be an input or an output.
11 9 S3B Source Terminal 3B. Can be an input or an output.
12 10 S2B Source Terminal 2B. Can be an input or an output.
13 11 S1B Source Terminal 1B. Can be an input or an output.
14 12 VDD Most Positive Power Supply Potential.
15 13 GND Ground (0 V) Reference.
16 14 A1 Logic Control Input.
Not 0 EPAD Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints
applicable and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.

Table 11. ADG1409 Truth Table

A1 A0 EN On Switch Pair
X X 0 None
0 0 1 1
0 1 1 2
1 0 1 3
1 1 1 4

Rev. D | Page 11 of 19
ADG1408/ADG1409 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

6 7
TA = 25°C VDD = +15V
VSS = –15V
6
5

ON RESISTANCE (Ω)
ON RESISTANCE (Ω)

4
3
3

2
2
VDD = +15V, VSS = –15V
VDD = +13.5V, VSS = –13.5V TA = +25°C
1 1
VDD = +12V, VSS = –12V TA = +85°C
VDD = +10V, VSS = –10V TA = –40°C
VDD = +16.5V, VSS = –16.5V TA = +125°C
0 0

04861-008
04861-006
–16.5 –12.5 –8.5 –4.5 –0.5 3.5 7.5 11.5 15.5 –15 –10 –5 0 5 10 15
SOURCE OR DRAIN VOLTAGE (V) SOURCE OR DRAIN VOLTAGE (V)

Figure 6. On Resistance vs. VD, VS; Dual Supply Figure 9. On Resistance vs. VD, VS for Different Temperatures;
15 V Dual Supply

9 12
TA = 25°C VDD = +5V
VSS = –5V
8
10
7
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)

6 8

5
6
4

3 4

2
VDD = +7V, VSS = –7V TA = +25°C
2
VDD = +5.5V, VSS = –5.5V TA = +85°C
1
VDD = +5V, VSS = –5V TA = –40°C
VDD = +4.5V, VSS = –4.5V TA = +125°C
0 0

04861-009
04861-036

–7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 –5 –4 –3 –2 –1 0 1 2 3 4 5

SOURCE OR DRAIN VOLTAGE (V) SOURCE OR DRAIN VOLTAGE (V)

Figure 7. On Resistance vs. VD, VS; Dual Supply Figure 10. On Resistance vs. VD, VS for Different Temperatures;
5 V Dual Supply

13 10
TA = 25°C VDD = 12V
12 VSS = 0V 9 VSS = 0V
11
8
10
7
ON RESISTANCE (Ω)

9
ON RESISTANCE (Ω)

8 6
7
5
6
4
5
4 3
3 VDD = 12V
2 TA = +25°C
VDD = 13.2V
2 TA = +85°C
VDD = 10.8V
1 TA = –40°C
1 VDD = 8V
VDD = 5V TA = +125°C
0 0
04861-010

0 2 4 6 8 10 12
04861-007

0 1 2 3 4 5 6 7 8 9 10 11 12 13
SOURCE OR DRAIN VOLTAGE (V) SOURCE OR DRAIN VOLTAGE (V)

Figure 8. On Resistance vs. VD, VS; Single Supply Figure 11. On Resistance vs. VD, VS for Different Temperatures;
12 V Single Supply

Rev. D | Page 12 of 19
Data Sheet ADG1408/ADG1409
1.0 18
IS (OFF) +– VDD = +15V IS (OFF) +– VDD = 12V
0.8 ID (OFF) +– VSS = –15V 16 ID (OFF) +– VSS = 0V
IS (OFF) –+ VBIAS = +10V/–10V IS (OFF) –+ VBIAS = 1V/10V
0.6 ID (OFF) –+ ID (OFF) –+
14
ID, IS (ON) ++ ID, IS (ON) ++
LEAKAGE CURRENT (nA)

LEAKAGE CURRENT (nA)

0.4 ID, IS (ON) –– ID, IS (ON) ––
12

0.2 10

0 8

–0.2 6

–0.4 4

–0.6 2

–0.8 0

–1.0 –2

04861-011

04861-013
0 10 20 30 40 50 60 70 80 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 12. Leakage Current vs. Temperature; Figure 15. Leakage Current vs. Temperature;
15 V Dual Supply 12 V Single Supply

14 70
IS (OFF) +– VDD = +15V IDD PER CHANNEL
ID (OFF) +– VSS = –15V TA = 25°C
12
IS (OFF) –+ VBIAS = +10V/–10V 60
ID (OFF) –+
10 ID, IS (ON) ++
LEAKAGE CURRENT (nA)

ID, IS (ON) –– 50
8
VDD = +15V
6
IDD (µA) 40 VDD = +12V VSS = –15V
VSS = 0V
4 30

2
20
0
10 VDD = +5V
–2 VSS = –5V

–4 0
04861-012

04861-034
0 20 40 60 80 100 120 0 2 4 6 8 10 12 14
TEMPERATURE (°C) LOGIC, AX (V)

Figure 13. Leakage Current vs. Temperature; Figure 16. Positive Supply Current vs. Logic Level
15 V Dual Supply

10 200
IS (OFF) +– VDD = +5V TA = 25°C
9 ID (OFF) +– VSS = –5V
IS (OFF) –+ VBIAS = +4.5V/–4.5V 150
8 ID (OFF) –+
ID, IS (ON) ++ 100
CHARGE INJECTION (pC)
LEAKAGE CURRENT (nA)

7 ID, IS (ON) ––
6 50

5 VDD = +5V
0 VSS = –5V
4 VDD = +12V
–50 VSS = 0V
3

2 –100 VDD = +15V

VSS = –15V
1
–150
0

–1 –200
04861-014
04861-015

0 20 40 60 80 100 120 –15 –10 –5 0 5 10 15

TEMPERATURE (°C) VS (V)

Figure 14. Leakage Current vs. Temperature; Figure 17. Charge Injection vs. Source Voltage
5 V Dual Supply

Rev. D | Page 13 of 19
ADG1408/ADG1409 Data Sheet
450 0
VDD = +15V
–10 VSS = –15V
400 TA = 25°C
VDD = +5V –20
350 VSS = –5V
–30
300 VDD = 12V

CROSSTALK (dB)
VSS = 0V –40
TIME (ns)

250 –50 ADJACENT

CHANNEL
200 –60

–70
150 VDD = +15V
VSS = –15V –80 NONADJACENT
100 CHANNEL
–90
50 –100

0 –110

04861-033

04861-018
–40 –20 0 20 40 60 80 100 120 1k 10k 100k 1M 10M 100M 1G
TEMPERATURE (°C) FREQUENCY (Hz)

Figure 18. Transition Time vs. Temperature Figure 21. ADG1409 Crosstalk vs. Frequency

0 0
VDD = +15V
–10 VSS = –15V
TA = 25°C –0.5
–20
–1.0
–30
OFF ISOLATION (dB)

BANDWIDTH (dB)

–40 –1.5
–50
–2.0
–60

–70 –2.5

–80
–3.0
–90
–3.5 VDD = +15V
–100 VSS = –15V
TA = 25°C
–110 –4.0
04861-016

04861-019
1k 10k 100k 1M 10M 100M 1G 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 19. Off Isolation vs. Frequency Figure 22. ADG1408 On Response vs. Frequency

0 0
VDD = +15V
–10 VSS = –15V
TA = 25°C –0.5
–20
–1.0
–30
CROSSTALK (dB)

BANDWIDTH (dB)

–40 –1.5
–50
–2.0
–60

–70 –2.5

–80
–3.0
–90
–3.5 VDD = +15V
–100 VSS = –15V
TA = 25°C
–110 –4.0
04861-017

04861-031

1k 10k 100k 1M 10M 100M 1G 100 1k 10k 100k 1M 10M 100M 1G

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 20. ADG1408 Crosstalk vs. Frequency Figure 23. ADG1409 On Response vs. Frequency

Rev. D | Page 14 of 19
Data Sheet ADG1408/ADG1409
0.10 0
LOAD = 110Ω VDD = +15V
0.09 TA = 25°C –10 VSS = –15V
TA = 25°C
0.08 –20 V p-p = 0.63V
–30
0.07
VDD = +5V, VSS = –5V, VS = +5V p-p
–40

ACPSRR (dB)
0.06
THD + N (%)

–50 NO DECOUPLING
0.05 CAPACITORS
–60
0.04
–70
0.03 VDD = +15V, VSS = –15V, VS = +15V p-p
–80 DECOUPLING
0.02 CAPACITORS
–90 ON SUPPLIES
0.01 –100

0 –110

04861-032

04861-035
10 100 1k 10k 100k 100 1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 24. Total Harmonic Distortion Plus Noise vs. Frequency Figure 25. AC Power Supply Rejection Ratio vs. Frequency

Rev. D | Page 15 of 19
ADG1408/ADG1409 Data Sheet

TERMINOLOGY
RON tBBM
Ohmic resistance between D and S. Off time measured between the 80% point of both switches
ΔRON when switching from one address state to another.
Difference between the RON of any two channels. VINL
RFLAT(ON) Maximum input voltage for Logic 0.
Flatness is defined as the difference between the maximum and VINH
minimum value of on resistance as measured. Minimum input voltage for Logic 1.
IS (Off) IINL, IINH
Source leakage current when the switch is off. Input current of the digital input.
ID (Off) IDD
Drain leakage current when the switch is off. Positive supply current.
ID, IS (On) ISS
Channel leakage current when the switch is on. Negative supply current.
VD (VS) Off Isolation
Analog voltage on Terminal D and Terminal S. A measure of unwanted signal coupling through an off channel.
CS (Off) Charge Injection
Channel input capacitance for off condition. A measure of the glitch impulse transferred from the digital
CD (Off) input to the analog output during switching.
Channel output capacitance for off condition. Bandwidth
CD, CS (On) Frequency at which the output is attenuated by 3 dB.
On switch capacitance. On Response
CIN Frequency response of the on switch.
Digital input capacitance. Total Harmonic Distortion Plus Noise (THD + N)
tON (EN) Ratio of the harmonic amplitude plus noise of the signal to the
fundamental.
Delay time between the 50% and 90% points of the digital input
and switch on condition. AC Power Supply Rejection Ratio (ACPSRR)

tOFF (EN) A measure of the ability of a device to avoid coupling noise and
Delay time between the 50% and 90% points of the digital input spurious signals that appear on the supply voltage pin to the
and switch off condition. output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of
tTRANSITION signal on the output to the amplitude of the modulation is
Delay time between the 50% and 90% points of the digital the ACPSRR.
inputs and the switch on condition when switching from one
address state to another.

Rev. D | Page 16 of 19
Data Sheet ADG1408/ADG1409

TEST CIRCUITS
V

IS (OFF) ID (OFF) ID (ON)

S D S D S D
A A NC A

IDS
VS VS VD VD

04861-021

04861-022
04861-020
NC = NO CONNECT

Figure 26. On Resistance Figure 27. Off Leakage Figure 28. On Leakage

VDD VSS

3V tr < 20ns
tf < 20ns VDD VSS
ADDRESS 50% 50%
DRIVE (VIN) A0
S1 VS1
0V VIN A1
50Ω
S2 TO S7
A2
tTRANSITION tTRANSITION
S8 VS8
90% ADG14081 OUTPUT
OUTPUT 2.4V EN D

GND 100Ω 35pF

90%

04861-023
1SIMILAR CONNECTION FOR ADG1409.

Figure 29. Address to Output Switching Times, tTRANSITION

VDD VSS

3V
VDD VSS
ADDRESS A0
DRIVE (VIN)
S1 VS
VIN A1
0V 50Ω
S2 TO S7
A2

S8
80% 80% ADG14081 OUTPUT
OUTPUT 2.4V EN D

GND 100Ω 35pF

tBBM

04861-024
1SIMILAR CONNECTION FOR ADG1409.

Figure 30. Break-Before-Make Delay, tBBM

VDD VSS

3V VDD VSS

ENABLE A0
50% 50%
DRIVE (VIN) S1 VS
A1
S2 TO S8
0V A2

tON (EN) tOFF (EN) ADG14081

OUTPUT
0.9VO 0.9VO EN D
OUTPUT VIN 35pF
50Ω 100Ω
GND
04861-025

1SIMILAR CONNECTION FOR ADG1409.

Figure 31. Enable Delay, tON (EN), tOFF (EN)

Rev. D | Page 17 of 19
ADG1408/ADG1409 Data Sheet
VDD VSS

VDD VSS
3V A0

A1
VIN
A2

ADG14081
RS S D
VOUT ΔVOUT VOUT
EN
CL
QINJ = CL × ΔVOUT VS GND 1nF
VIN

04861-026
1SIMILAR CONNECTION FOR ADG1409.

Figure 32. Charge Injection

VDD VSS
VDD VSS
0.1µF 0.1µF
0.1µF 0.1µF

NETWORK
VDD VSS ANALYZER NETWORK
VDD VSS ANALYZER

S 50Ω
50Ω S 50Ω
VS
VS
D
D
VOUT
RL VOUT
RL
50Ω
GND 50Ω
GND
04861-027

VOUT

04861-029
OFF ISOLATION = 20 log VOUT WITH SWITCH
VS INSERTION LOSS = 20 log
VOUT WITHOUT SWITCH

Figure 33. Off Isolation Figure 35. Insertion Loss

VDD VSS
0.1µF 0.1µF

NETWORK VDD VSS

ANALYZER VDD VSS 0.1µF
0.1µF
VOUT
RL S1
50Ω AUDIO PRECISION
VDD VSS
D R
RS
S2 50Ω
S
VS IN
VS
GND V p-p
D
VIN VOUT
RL
10kΩ
04861-028

VOUT GND
04861-030

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

VS

Figure 34. Channel-to-Channel Crosstalk Figure 36. THD + N

Rev. D | Page 18 of 19
Data Sheet ADG1408/ADG1409

OUTLINE DIMENSIONS
5.10
5.00
4.90

16 9

4.50
6.40
4.40 BSC
4.30
1 8

PIN 1
1.20
MAX
0.15 0.20
0.05 0.09 0.75
0.30 8° 0.60
0.65 0.19 0° 0.45
SEATING
BSC PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 37. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)
Dimensions shown in millimeters
4.10 0.35
4.00 SQ 0.30
PIN 1 3.90 0.25
INDICATOR PIN 1
13 16 INDICATOR
0.65
12 1
BSC
EXPOSED 2.60
PAD
2.50 SQ
2.40

9 4
8 5
0.50
TOP VIEW 0.40 BOTTOM VIEW
0.30
0.80 FOR PROPER CONNECTION OF
0.75 THE EXPOSED PAD, REFER TO
0.05 MAX THE PIN CONFIGURATION AND
0.70 FUNCTION DESCRIPTIONS
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
SEATING 0.08
PLANE 0.20 REF 042709-A

COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.

Figure 38. 16-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-26)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
ADG1408YRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1408YRUZ-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1408YRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1408YCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-26
ADG1409YRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1409YRUZ-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1409YRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1409YCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-26
1
Z = RoHS Compliant Part.

©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D04861-0-6/16(D)

Rev. D | Page 19 of 19