PIC Microcontroller

Architecture

Prof. M. N. KAKATKAR
 Syllabus

Features, comparison & selection of PIC series as per

application. PIC18FXX architecture- MCU, Program
and Data memory organization, Pin out diagram,
Reset operations, Oscillator options (CONFIG),
BOD, power down modes & configuration bit
settings, timer and its programming, Brief summary
of Peripheral support, Overview of instruction set.
 Choosing a uController

 The major 8-bit

 Freescale Semiconductor’s (formerly Motorola)
 68HC08/68HC11

 Intel’s 8051

 Atmel’s AVR

 Zilog’s Z8

 PIC from Microchip Technology

 Criteria for Choosing
uController

 Meeting the computing needs of the task at hand

efficiency and cost effectively
 Availability of SW and HW development tools
 Compilers

 Assemblers

 Debuggers

 Emulators

 Wide availability and reliable source

 Criteria for Choosing
uController

 Meeting the computing needs of the task at hand

efficiency and cost effectively
 Determine its type, 8-bit,16-bit or 32-bit
 Speed

 Packaging (40-Pin or QFP)

 Power consumption

 The amount of RAM and ROM

 The number of I/O pins and the timer

 Cost per unit

 Ease of upgrade.
 RISC vs CISC: Characteristics

RISC CISC
1. Simple Instruction taking 1 cycle 1. Complex Instruction taking multiple cycles

2. Only LOADs, STOREs access memory 2. Any Instruction. may access memory

3. Designed around pipeline 3. Designed around Instruction. Set

4. Instruction. executed by h/w 4. Instruction interpreted by micro program

5. Fixed format Instruction 5. Variable format Instruction

6. Few Instruction and modes 6. Many Instruction and modes

7. Complexity in the compiler 7. Complexity in the micro program

8. Multiple register sets 8. Single register set

9. Operates at 50-150 MHz 9. Operates at 33-50 MHz

 Von Neumann Architecture --- CISC
Von Neumann Architecture:
Fetches instructions and data from
a single memory space
Limits operating bandwidth

Address
Address

Input Control CPU ALU Output

Data Data

Address Data

Memory
(Program and Data)
 Harvard Architecture -- RISC
Harvard Architecture:
Uses two separate memory
spaces for program instructions
and data
Improved operating bandwidth
Allows for different bus widths
Address
Address
Input Control CPU ALU Output

Data Data Data

Address Data Address Data

Program Data
Memory Memory
9 Prof. M. N. Kakatkar S.C.O.E , Pune 10/5/2024
 PIC Microcontroller– General features

• PIC 16CXX, PIC17CXX are 8-bit microcontroller by Microchip

• They use CMOS technology
• PIC are popular due to High performance, Low cost,& small Size
• It uses High speed RISC Architecture --33 Single word instructions
• Operating frequency for 16CXX – DC to 20 MHz
• Can add external program memory up to 64 K words
• Some advanced versions include ADC with 4-8 Channels
• General features includes Timers, Watch dog timers, Embedded ADC,
• Extended Instruction / Data memory , Serial communications , PWM outputs ,
ROM, EPROM, and EEPROM memories

I/O
Memory CPU (Ports A, B & C)

Timer Timer Timer PWM PWM 10-bit

0 1 2 1 2 A/D USART
 PIC 18F452/458

High-Performance, Enhanced Flash

Microcontrollers with CAN
 Features of IC 18F452/458

 It uses RISC architecture

 8 bit data bus
 16 bit instructions
 2MBytes of program ROM [21 Address line]
 4KBytes of Data RAM [12 Address lines]
 32 K flash ROM
 1536 bytes SRAM –Scratch Pad
 256 bytes – EEPROM – for storing critical
information
 Features of IC 18F452/458

 10 bit, 8 channel ADC

 USART , 4 Timers/ Counters
 5 ports A[6], B,C,D[8], E[3] =33 IO lines
 DC-40 MHz clock Input
 Has 16 bank registers with 256 entries
 Has GPR [variable] and SFR [fixed locations]
 Features of IC 18F452/458– High performance

High-Performance RISC CPU:

 Linear program memory addressing up to2 Mbytes

 Linear data memory addressing to 4 Kbytes

 Up to 10 MIPS operation

 DC – 40 MHz clock input

 4 MHz-10 MHz oscillator/clock input with PLL active

 16-bit wide instructions, 8-bit wide data path

 Priority levels for interrupts

 8 x 8 Single-Cycle Hardware Multiplier

 Features of IC 18F452/458 -- Peripherals

Peripheral Features:
• High current sink/source 25 mA/25 mA.
• Three external interrupt pins.
• Four Timer modules (Timer0 to Timer3).
• Timer0 module: 8-bit/16-bit timer/counter with 8-bit
programmable prescaler
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter with 8-bit period
register (time base for PWM)
• Timer3 module: 16-bit timer/counter
• Secondary oscillator clock option – Timer1/Timer3
 Features of IC 18F452/458 -- Peripherals

Peripheral Features:
• Capture/Compare/PWM (CCP) modules;
• CCP pins can be configured as:
• Capture input: 16-bit, max resolution 6.25 ns
• Compare: 16-bit, max resolution 100 ns (TCY)
• PWM output: PWM resolution is 1 to 10-bit
• Max. PWM freq. @:8-bit resolution = 156 kHz
10-bit resolution = 39 kHz
 Features of IC 18F452/458 -- Peripherals

• Enhanced CCP module which has all the features of the

standard CCP module, but also has the following features for
advanced motor control:
- 1, 2 or 4 PWM outputs
- Selectable PWM polarity
- Programmable PWM dead time
• Master Synchronous Serial Port (MSSP) with two modes of
operation:
- 3-wire SPI™ (Supports all 4 SPI modes)
- I2C™ Master and Slave mode
• Addressable USART module:- Supports interrupt-on-
address bit
 Features of IC 18F452/458 -- Analog

 10-bit, up to 8-channel Analog-to-Digital Converter

module (A/D) with:
- Conversion available during Sleep
- Up to 8 channels available
 Analog Comparator module:
- Programmable input and output multiplexing
 Comparator Voltage Reference module
 Programmable Low-Voltage Detection (LVD) module:
- Supports interrupt-on-Low-Voltage Detection
 Programmable Brown-out Reset (BOR)
 Features of IC 18F452/458 -- CAN Bus

 Complies with ISO CAN Conformance Test

 Message bit rates up to 1 Mbps
 Conforms to CAN 2.0B Active Spec with:
- 29-bit Identifier Fields
- 8-byte message length
- 3 Transmit Message Buffers with prioritization
- 2 Receive Message Buffers
- 6 full, 29-bit Acceptance Filters
- Prioritization of Acceptance Filters
- Multiple Receive Buffers for High Priority Messages to prevent
loss due to overflow
- Advanced Error Management Features
 Features of IC 18F452/458 -- µc, Flash

 Power-on Reset (POR), Power-up Timer (PWRT) and

Oscillator Start-up Timer (OST)
 Watchdog Timer (WDT) with its own on-chip RC oscillator
 Programmable code protection
 Power-saving Sleep mode
 Selectable oscillator options, including:
- 4x Phase Lock Loop (PLL) of primary oscillator
- Secondary Oscillator (32 kHz) clock input
 Features of IC 18F452/458 -- µc, Flash

 In-Circuit Serial Programming TM (ICSPTM) via two pins

 Low-power, high-speed Enhanced Flash technology
 Fully static design
 Wide operating voltage range (2.0V to 5.5V)
 Industrial and Extended temperature ranges
Features of IC 18F452/458 - comparison
Architecture PIC18f452
 PIC18F Microcontroller-- Architecture

 PIC microcontrollers are designed using the Harvard

Architecture which includes:
 Microprocessor unit (MPU)
 Program memory for instructions

 Data memory for data

 I/O ports

 Support devices such as timers

 Support for serial communication

 Working Register (WREG)

 8-bit WREG is most widely used register in the PIC

microcontroller.
 WREG is same as an Accumulator.
 It is used for all Arithmetic and Logical operations.
 To understand the use of WREG, let us see examples
of two instructions
 MOVLW instruction

 It moves 8-bit data into WREG.

MOVLW 8-bit_data
 8-bit data value that can range from 0-255 in decimal,
00H-FFH in hexadecimal.
 L stands for literal, which means instruction is dealing
with actual value.
 It is similar to immediate value used (#value) in 8051.
 W stands for WREG.
MOVLW 25H ; move value 25H into W
; i.e. W=25H
 ADDLW instruction

ADDLW 8-bit_data
 Add 8-bit literal value into WREG and store result into
WREG.
 To perform addition of 25H+34H=59 we can use
above instructions as
MOVLW 25H ; move value 25H into W
; i.e. W=25H
ADDLW 34H ; W=W+34H
; W=25H+34H=59H
 File Register

 The PIC microcontroller has many other registers.

 They are called as data memory space.
 In PIC literature, the data memory is also called as File
Registers.
PIC 18F452 General Architecture
Instruction Register
 Part of CPUs control unit which holds the instruction
currently being executed.
 In instruction cycle the instruction is loaded from
program memory(flash ROM) into instruction register.

Instruction Decoder
 Decodes instruction in instruction register.
 Decoding includes determining where its operands are
in memory, retrieving operands from memory,
allocating resources to execute the command
PIC18F – MCU and Memory

16 bit

2 MB
221

8 bit

4 KB
212
 Microprocessor Unit (MCU)

 It includes
 ALU
 Registers
 Control Unit
Arithmetic Logic Unit (ALU)
Example
ADDWF F, d ; Add WREG to File (Data) Reg.
;Save result in W if d =0
;Save result in F if d = 1
 Arithmetic & Logic Unit(ALU)

 Working register (WREG): Working Register 8-bit long

 Status Register: Stores Flag, 8-bit long
 Instruction Decoder: When instruction is fetched it goes
into instruction decoder.

 It performs Arithmetic and logical operations.

 While performing operations one of the operand is from
the program memory(8-bit literal from instruction)
multiplexed with other input from SFRs and other is
from working register (W).
 Arithmetic & Logic Unit(ALU)

 The result of operation may be stored either in working

register(W) or file register according to the direction of
direction bit ‘d’.
 If d=0, result is stored in WREG.
 If d=1, result is stored in file register.
 MEMORY ORGANIZATION

 Types of memory in PIC18 enhanced microcontroller

devices:
 ProgramMemory
 Data RAM
 Program Memory Organization

 PIC18 microcontrollers implement a 21-bit program

counter =addressing a 2-Mbyte program memory
space
 The PIC18F252 and PIC18F452 each have 32
Kbytes of FLASH memory
 The Reset vector address is at 0000h and the interrupt
vector addresses are at 0008h and 0018h
 Program Memory-organization

The RESET vector address

A 21-bit program counter is
is at 0000h and the capable of addressing the
interrupt vector 2-Mbyte program memory
addresses are at 0008h space.
and 0018h.

PIC18F452 each have 32

Kbytes of FLASH memory.
This means that it can store Accessing a location
up to 16K of single word between the physically
instructions implemented memory
and the 2-Mbyte
address will cause a
read of all ’0’s (a
NOP instruction).
 PROGRAM COUNTER

 The Program Counter (PC) specifies the address of

the instruction to fetch for execution.
 The PC is 21 bits wide and is contained in three
separate 8-bit registers
 The low byte, known as the PCL register, is both
readable and writable.
 The high byte, or PCH register, contains the PC<15:8>
bits; it is not directly readable or writable
 The upper byte is called PCU. This register contains
the PC<20:16> bits; it is also not directly readable or
writable.
 STACK

 The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack

Pointer, STKPTR.
 It is initialized to 00000 after reset.
 During subroutine call stack pointer is first incremented & memory
location it points to is written with the contents of program counter.
 During return stack is decremented by one and return back to the location
of program counter.
 The stack space is not part of either program or data space.
 Data Memory Organization

 Read/Write =>Static RAM

 Used for data storage, scratch pad and registers for
internal use and function
 8-bit width
 Data Memory organization FFFh
Access SFR
FFF=212=16x256=4096=4K F80h
F7Fh Data Memory also known
Bank 15GPR as “Register File”
F00h
 Data Memory up to 4k bytes EFFh
Bank 14
 Data register map - with 12- GPR
bit address bus 000-FFF E00h
DFFh
 Divided into 256-byte banks Bank 13
GPR Access Bank
 There are total of F (16)banks D00h
FFh
Access SFR 80h
 Half of bank 0 and half of
7Fh
bank 15 form a virtual bank 2FFh
Access RAM(GPR)
00h
that is accessible no matter Bank 2
256 Bytes
GPR
which bank is selected 200h
1FFh GPR=General Purpose Reg.
SFR=Special Function Reg.
BSR holds 4 bit bank address 0-F Bank 1
GPR
and remaining 8 bits points to 256 100h
locations in selected bank 0FFh
Bank 0 GPR
These registers are always
080h accessible regardless which
07Fh
Access RAM
bank is selected – acting as
000h a virtual memory -
 BANK SELECT REGISTER (BSR)

 This BSR holds the 4 Most Significant bits of a

location’s address; the instruction itself includes the
eight Least Significant bits
 The BSR can be loaded directly by using the
MOVLB instruction
 In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers
 ACCESS BANK

 While the use of the BSR, with an embedded 8-bit address, allows users to
address the entire range of data memory, it also means that the user must
always ensure that the correct bank is selected.
 To streamline access for the most commonly used data memory locations,
the data memory is configured with an Access Bank, which allows users to
access a mapped block of memory without specifying a BSR.
 The Access Bank is used by core PIC18 instructions that include the
Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to
‘1’, the instruction uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’, however, the
instruction is forced to use the Access Bank address map; the current value
of the BSR is ignored entirely.
 Accessing Data Memory
 The machine code for a PIC18 instruction has only 8 bits
for a data memory address which needs 12 bits. The Bank
Select Register (BSR) supplies the other 4 bits.
 Registers

 Bank select register (BSR): Bank select register, 4-bit

register. Provides upper 4-bits of 12-bit address of data
memory.
 File select register (FSR): File select registers FSR0,
FSR1, FSR2
 FSR composed of two 8-bit registers: FSRH & FSRL
 Holds 12-bit address for data register.
 Program Counter (PC): 21-bit register holds the
program memory address while executing programs.
 Control Unit

 Provides timing and control signals to various read and write

operations. Control Signals: Read and Write.
 Address Bus:
 21-bit address bus for program memory
 12-bit address bus for data memory

 Data Bus:
 16-bit instruction/data memory for program.
 8-bit data bus for data memory.
 PIC18F458 –Memory Data and Address Bus
16 bit

2 MB
221

8 bit

4 KB
212

Address bus:
 21-bit address bus for program memory addressing capacity: 2 MB of memory
 12-bit address bus for data memory addressing capacity: 4 KB of memory
Data bus: 16-bit instruction/data bus for program memory
8-bit data bus for data memory
 Flags in Status Register

 N (Negative Flag)
 Set when bit B7 is one as the result of an arithmetic/logic operation
 OV (Overflow Flag)
 Set when result of an operation of signed numbers goes beyond 7-bits
 Z (Zero Flag)
 Set when result of an operation is zero
 DC (Digit Carry Flag) (Half Carry)
 Set when carry generated from Bit3 to Bit4 in an arithmetic operation
 C (Carry Flag)
 Set when an addition generates a carry
 PIC Registers- Program Counter
10/5/2024

 The PC is used by the CPU to point to the address of the

instruction to be executed
 The wider the PC more the memory locations a CPU can
access
 That means that a 14 bit program counter can
accesses a maximum of 16K (214 = 16K) of code from
addresses 0000H – 3FFFH
 The PC in the PIC 18 family is 21 bit
 This means that the PIC 18 family can accesses
program addresses 000000 to 1FFFFFH a total of 2M
code

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Prof. A. V. Bankar
 Stack & Stack Pointer
10/5/2024

Stack Pointer (SP)

5-bit register used to point to the stack
Stack
31 bit registers used for temporary storage of
memory addresses during execution of a program
 21 bit stack can take values from 000000 to

1FFFFFH
 PIC 18 has a stack pointer of 5 bit that can take
values from 00 to 1FH
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 PIC Registers

10/5/2024

BSR: Bank Select Register

 8-bit Register
 only 4 least significant bits are used and upper 4
bits are set to zero and ignored by PIC 18

FSR: File Select Registers: FSR0, FSR1, and

FSR2.
FSR is composed of two 8-bit registers i.e.
FSRH and FSRL
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 Used as pointers for data registers
Prof. M. N. Kakatkar S.C.O.E , Pune
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 Holds 12-bit address of data register Prof. A. V. Bankar
 Oscillator
10/5/2024

 OSC1 & OSC2:

Quartz crystal oscillator is
connected to input pins OSC1 &
OSC2 (Pin 13 & Pin 14)
 The quartz crystal oscillator
connected to the OSC1 & OSC2
pins also needs two capacitors
 One side of each capacitor is
connected to the ground
 PIC 18f microcontroller can have
speeds of 0 Hz to 40 MHz
 We can choose options for the
clock frequency by setting bits
in the configuration register
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 Minimum Connection For PIC18f 458
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 Reset
10/5/2024

 Power On Reset:
 MCLR:
Pin 1 is the MCLR (Master Clear Input) pin. It is
active low and when a low pulse is applied to the
pin, the microcontroller will reset and terminate
all activities. This is often referred as power on
reset (POR)

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 Reset

10/5/2024
 Power up Timer (PWRT):
1.The power up timer provides a fixed nominal time out ,
only on power up from the Power on reset
2.The power up timer operates on an internal RC
Oscillator
3.The chip is kept in reset as long as the PWRT is
active
4.The PWRT time delay allows Vdd to rise to an
acceptable level
5.A configuration bit PWERTEN is provided to
enable/ disable the PWRT
6.The power up time delay will vary from chip to chip
due to Vdd , Temperature and process variation

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 Reset

10/5/2024

 Watchdog Timer:
1. Function: Watchdog timer is a device whose function is to
reset the system after a predefined timeout
2. We can use the watchdog timer to force the microcontroller
into the known state of reset when the system is hung up or
out of control due to execution of an incorrect sequence of
codes
3. To prevent a system from going into an infinite loop due to
a software bug
4. Catch the events that cause the system to hang
( These problem can happen due to corruption of the
ROM caused by a power surge, an electrically noisy
environment, or inadvertent changes to the program
counter )

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 Continue…..
10/5/2024

 Watchdog Timer:
5. The system can be put to sleep if there is no
activity, there by saving battery power , in such
applications one can use the watchdog timer to
monitor the keyboard and when there is activity
on the keyboard to awaken the system to process
the information

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 Reset
 Brown Out Reset:
10/5/2024

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 Continue…..
10/5/2024

 Brown Out Reset:

1. Occasionally the power source provided to the Vcc (Vdd ) pin
fluctuates, causing the CPU to malfunction
2. The PIC 18 family has a provision for this which is called
Brown out reset voltage
3. The Brown out reset voltage bits in CONFIG2L allow us to
set the minimum voltage for Vdd. If it falls below that, the
CPU will go into the reset state and stop all activities
4. At the high frequency of 40 MHz with Vdd = 5v we set
BORV to 4.5 v
5. That means that if Vdd falls below the 4.5v , the CPU will
go into the reset state and stop execution of programs
without losing any data in registers

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 Special Function Register

 These registers are used to control the operation of

Timers/Counters, interrupts, serial interface, and ports.
 The location of each SFR is fixed and accessed by use of direct
addressing mode.
 The data registers associated with I/O ports, support devices and
processes of data transfer are
 I/O port (A to E)
 Interrupt
 EEPROM
 Timers
 Serial I/O
 Capture/ Compare/ PWM (CCP)
 ADC
10/5/2024

PIC 18 Configuration
Registers

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 Configuration Registers
10/5/2024

 There are some features of PIC 18 that we can

choose by programming the bits of the configuration
registers
 These features will reduce system cost by eliminating
any need for external components
 The configuration registers are located at the address
starting at 300001H

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 Configuration Registers

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 Description of the Configuration Registers
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 CONFIG1H Configuration Register
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 CONFIG2L Register for Reset voltage
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 Input Output Ports
10/5/2024

 PIC Microcontroller has 5 ports namely port A, Port

B, Port C, Port D and Port E
 Each port has three registers for its operation:
1. TRIS register( Data direction register)
2. PORT register( reads the levels on the
pins of device)
3. LAT register (output latch)

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 Data Memory Addressing - Direct
 Operand address(es) embedded in the opcode
 8 bits of the 16-bit instruction specify any one of 256 locations
 The 9th bit specifies either the Access Bank (=0) or one of the
banks (=1)
 Data Memory Addressing - Direct

 ADDLW f, d, a

 ADDLW 0x30, 0, 0

 ADDLW 0x30

 MOVWF 0X22
 Data Memory Addressing - Indirect

FSR – (File Select Register): Special Purpose Register

 Indirect addressing.

 8-bit register file - address pointer

 any address is first written in FSR access entire register

file.
INDF – (Indirect File): Special Purpose Register
 Is not a Physical Register
 Addressing INDF - Addresses Register address in FSR .

Register File Register File

05h 06h
• 0
inc f • 10 A
FSR = 05 INDF =
INDF = 0A
10
FSR = 06
 Data Memory Addressing - Indirect

 In register indirect addressing mode, a register is used as

pointer to the data RAM location.
 There are three registers are used for this purpose
 FSR0
 FSR1
 FSR2
 FSR stands for File Select Register.
 It is 12-bit register.
 LFSR (load FSR) instruction is used to load address of
RAM.
 Data Memory Addressing - Indirect

 As FSR is 12-bit register it can not fit into SFR address

space.
 Hence is split into lower 8-bits (FSRxL) and upper 4-bits
(FSRxH).
 Upper 4-bits are not used.
 Another register associated with the register indirect
addressing mode is INDF (indirect register).
 Each FSR has its associated INDF register.
 When we move the data to INDF we actually move data to
the RAM location pointed by FSR associated to INDF and
vice versa.
 Data Memory Addressing - Indirect

 LFSR 0, 0x30 // Load FSR0 with 0x30

 LFSR 1, 0x40 // Load FSR1 with 0x40
 LFSR 2, 0x6F // Load FSR2 with 0x50

 MOVWF INDF0 // copy contents of WREG into

// RAM Location whose address
is held by 12-bit FSR0 register
 Data Memory Addressing - Indirect
 3 File Select Registers (FSR) as a pointer to the data memory location that is to be
read or written.
 Each FSR has an INDF register associated with it
 The INDFn register is not a physical register. Addressing INDFn actually addresses
the register whose address is contained in the FSRn register.